Computer Architecture I Lecture Presentation 2

Computer Architecture I

Lecture Notes

Dr. Ali Muhtaroğlu

Fall 2009

METU Northern Cyprus Campus

References:

Patterson&Hennessy, “Computer Organization and Design” (3rd Ed.), Kaufmann, 2007.

Stallings, “Computer Organization & Architecture” (7th Ed.), Pearson, 2006.

Mano & Kime, “Logic and Computer Design Fundamentals”, 4th Ed., Prentice Hall, 2008.

Brown & Vranesic, “Fund. Of Dig. Logic with VHDL Design” (2nd Ed.), McGraw Hill, 2005.

Dr. Patterson’s and Dr. Mary Jane Irwin’s (Penn State) Lecture notes

The Computer Components and Program Concept

Lecture 3

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Some Terminology: Structure and Function

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• The computer is a hierarchical system, where each level ofthe hierarchy can be defined by the designer in terms of astructure and the function of components within thatstructure.

• Structure is the way in which components relate to eachother

• Function is the operation of individual components as part ofthe structure

Functional View

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4 computer functions:

1. Data processing– The main purpose of a computer

2. Data storage– Short or long term memory

3. Data movement– Input/Output (I/O): Direct connection

– Data communications: Remote

4. Control− Orchestrates the operation of

functional parts

Functional View: Basic Computer Operations

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a) Data Movement b) Storage

c) Processing from/tostorage

d) Processing en routebetween storage and I/O

Structural View : Top Level

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Computer

Main Memory

InputOutput

SystemsInterconnection

Peripherals

Communicationlines

CentralProcessing Unit

Computer

Structural View : Central Processing Unit

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Computer Arithmeticand Logic Unit

ControlUnit

Internal CPUInterconnection

Registers

CPU

I/O

Memory

SystemBus

CPU

Control Unit: Controls the operation of the CPU and hence the computer

Arithmetic and Logic Unit (ALU): Performs the computer’s data processing functions

Registers: Provide storage internal to the CPU

CPU interconnection: Provides for communication among the control unit, ALU, and

registers

Structural View : Control Unit

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Below is one possible structure of control unit, which isimplemented using microprogramming – details to come later.

CPU

ControlMemory

Control Unit Registers and Decoders

SequencingLogic

ControlUnit

ALU

Registers

InternalBus

Control Unit

Hardwired Program Example

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Logic: Timing Diagram:

• The logic constructed to solve a particular problem can bethought of as a hardware “program”. The solution issometimes referred to as hardwired program.

• This example has data and clock inputs, and an output toreport the data back.

• What are the advantages and disadvantages of this solution?

clk

IN1

IN2

IN3

IN4

R1

R2

R3

R4

R5

B

C

D

A

B

C

D

A

A-((B+C)-D)

OUT

clk

IN1 IN2

IN3

IN4

x+y

x y

x-y

x y

x-y

x y

R1 R2

R3

R4

R5

OUT

A more Generalized Solution

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Logic:

• In this particular design, control signals (SEL1, SEL2, A/S) can be sequenced tosolve a variety of problems involving addition and subtraction.

• An instruction set can be defined to allow software sequencing of the controlsignals. e.g. ADDR1R2 : R3 R1+R2 ; SUBR1R3 : R3 R1-R3 … etc.

• Need hardware to interpret each instruction and generate the correct controlsignals i.e. Control Unit. Also need storage for instructions, and perhaps data i.e.Memory.

clk

IN1 IN2

ADD:x+y

SUB:x-y

x y

A(0)/S(1)

OUT

SEL1 SEL2

R1 R2

R3

0 1 0 1


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Logic:




clk

IN1 IN2

ADD:x+y

SUB:x-y

x y

A(0)/S(1)

OUT

SEL1 SEL2

R1 R2

R3

0 1 0 1

How do we do the same

operation with this

hardware?

A-((B+C)-D)


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clk

IN1 IN2

ADD:x+y

SUB:x-y

x y

A(0)/S(1)

OUT

SEL1 SEL2

R1 R2

R3

0 1 0 1

clk

IN1

IN2

SEL1

SEL2

R1

R2

R3

B A

C D

B A

C D

OUT1 OUT2

A/S

(B+C) (B+C)-D

OUT3

A-((B+C)-D)


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• What are the advantages and disadvantages of this solution?

clk

IN1 IN2

ADD:x+y

SUB:x-y

x y

A(0)/S(1)

OUT

SEL1 SEL2

R1 R2

R3

0 1 0 1

clk

IN1

IN2

SEL1

SEL2

R1

R2

R3

B A

C D

B A

C D

OUT1 OUT2

A/S

(B+C) (B+C)-D

OUT3

A-((B+C)-D)

Program Concept

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Sequence of arithmetic and logic functions

Data Results

Programming in Hardware:

• Inflexible

General-purpose arithmetic and logic functions

Data Results

Instruction Interpreter

Instructioncodes

Programming in software:

• General purpose hardware cando different tasks, given correctcontrol of signals.

• Instead of rewiring, supply anew set of control signals

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What is a program?

• A sequence of steps

• For each step, an arithmetic or logical (or simple movement)operation is done

• For each operation, a different set of control signals is needed

Function of Control Unit

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• For each operation a unique code is provided

– e.g. ADD, MOVE

• A hardware segment accepts the code and issues the control signals

• We have a computer!

What is a program?

• A sequence of steps

• For each step, an arithmetic or logical (or simple movement)operation is done

• For each operation, a different set of control signals is needed

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Computer Components

• The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit

• Data and instructions need to get into the system and results out

– Input/output

• Temporary storage of code and results is needed

– Main memory

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Computer Components: Top Level View

* Assumes Isolated I/O (vs. Memory Mapped I/O)

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Instruction Cycle

• Two steps (three steps if you also count Decode):

– Fetch

– (Decode)

– Execute

• Fetch/(Decode)/Execute cycle will continue till the machine is turned off, an error has occurred, or a HALT (or similar) instruction has been encountered.

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Fetch Cycle• Program Counter (PC) holds address of next instruction to fetch

• Processor fetches instruction from memory location pointed to by PC

• Increment PC

– Unless told otherwise

• Instruction loaded into Instruction Register (IR)

• Processor interprets (decodes) instruction and performs required actions

Execute Cycle• Processor-memory

– data transfer between CPU and main memory

• Processor I/O

– Data transfer between CPU and I/O module

• Data processing

– Some arithmetic or logical operation on data

• Control

– Alteration of sequence of operations e.g. jump

• Combination of above

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Example: Hypothetical Machine

Opcode Address

0 3 4 15

Instruction Format:

Magnitude

0 15

Integer Format:

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Opcode Address

0 3 4 15

Instruction Format:

Magnitude

0 15

Integer Format:

Program Counter (PC) = Address of instruction

Instruction Register (IR) = Instruction being executed

Accumulator (AC) = Temporary storage

Internal CPU Registers:

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Opcode Address

0 3 4 15

Instruction Format:

Magnitude

0 15

Integer Format:





0001 = Load AC from memory

0010 = Store AC to memory

0101 = Add to AC from memory (result goes back to AC)

Partial list of opcodes:

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Opcode Address

0 3 4 15

Instruction Format:

Magnitude

0 15

Integer Format:





0001 = Load AC from memory

0010 = Store AC to memory

0101 = Add to AC from memory (result goes back to AC)

Partial list of opcodes:

Note: There can be 24 different opcodes

212=4096 memory words are directly accessible by the instruction.

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Example Program Execution

Micro-Operation:

Fetch 1st Instruction

MAR & MBR data

transfers are not shown

(ignored for now.)

Opcode List:

0001 = Load AC from

memory

0010 = Store AC to

memory

0101 = Add to AC from

memory

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Micro-Operation:


Decode and Execute

MAR & MBR data


(ignored for now.)

Opcode List:

0001 = Load AC from

memory

0010 = Store AC to

memory


memory

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Micro-Operation:


Decode and Execute

Fetch 2nd Instruction

MAR & MBR data


(ignored for now.)

Opcode List:

0001 = Load AC from

memory

0010 = Store AC to

memory


memory

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Micro-Operation:


Decode and Execute


Decode and Execute

MAR & MBR data


(ignored for now.)

Opcode List:

0001 = Load AC from

memory

0010 = Store AC to

memory


memory

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Micro-Operation:


Decode and Execute


Decode and Execute

Fetch 3rd Instruction

MAR & MBR data


(ignored for now.)

Opcode List:

0001 = Load AC from

memory

0010 = Store AC to

memory


memory

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Micro-Operation:


Decode and Execute


Decode and Execute

Fetch 3rd Instruction

Decode and Execute

Opcode List:

0001 = Load AC from

memory

0010 = Store AC to

memory


memory

MAR & MBR data


(ignored for now.)

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Instruction Cycle State Diagram

This diagram incorporates the most flexible machine type where there may be

multiple operands in a single instructoin referencing the memory for multiple

data reads or writes.

Processor and

Memory or I/O

Data exchange

Internal

Processor

Operations

Documents

Computer Architecture I Lecture Presentation 2