Computer Arithmatic

1Computer Arithmetic

Computer Organization Computer Architectures Lab

• Arithmetic with Signed-2's Complement Numbers

• Multiplication and Division

• Floating-Point Arithmetic Operations

• Decimal Arithmetic Unit

• Decimal Arithmetic Operations

COMPUTER ARITHMETIC



SIGNED MAGNITUDEADDITION AND SUBTRACTION

Addition and Subtraction

(+A) + (+B)(+A) + (- B)(- A) + (+B)(- A) + (- B)(+A) - (+B)(+A) - (- B)(- A) - (+B)(- A) - (- B)

+(A + B)

- (A + B)

+(A + B)- (A + B)

+(A - B)- (A - B)

+(A - B)

- (A - B)

- (B - A)+(B - A)

- (B - A)

+(B - A)

+(A - B)+(A - B)

+(A - B)

+(A - B)

Operation Magnitude When A>B When A<B When A=BAdd Subtract Magnitude

Hardware Implementation Bs B Register

Complementer M(Mode Control)AVF

E OutputCarry

Parallel Adder InputCarry

S

As A Register Load Sum

Addition: A + B ; A: Augend; B: AddendSubtraction: A - B: A: Minuend; B: Subtrahend



SIGNED 2’S COMPLEMENT ADDITION AND SUBTRACTION

Addition and Subtraction

Hardware

AlgorithmSubtract Add

B Register

Complementer andParallel Adder

V

Overflow

AC

Minuend in ACSubtrahend in B

Augend in ACAddend in B

AC AC + B’+ 1V overflow

AC AC + BV overflow

END END



MULTIPLICATION

Multiplication: B * A; B: Multiplicand; A: Multiplier; P: Partial Product

Multiplication

Multiplication of Unsigned Positive Numbers

A = An-1An-2 ... A0

B = Bn-1Bn-2 ... B0

P = B * A= B * (

i=0

n-1

= An-1 * (B2n-1) + An-2 * (B2n-2) + ... + A0 * (B20)B shifted left B shifted left B shifted leftn-1 bits n-2 bits 0 bits = A

Or B shifted (n-1) bits to the left

P = An-1*(B2n-1 * 20) + An-2*(B2n-1 * 2-1) + ... + A0*(B2n-1 * 2-(n-1))

B2n-1 B2n-1 shifted right B2n-1 shifted right 1 bit (n-1) bits

2i * Ai )



EXAMPLE

Multiplicand B=10111 E A Q SC

Multiplier in QQ0 = 1; add BFirst partial productShift right EAQQ0 = 1; add BSecond Partial ProductShift right EAQQ0 = 0; shift right EAQQ0 = 0; shift right EAQQ0 = 1; add BFifth partial productShift right EAQFinal Product in AQ = 0110110101

0 00000 10011 101 101110 101110 01011 11001 100 101111 000100 10001 01100 0110 01000 10110 0100 00100 01011 001 101110 110110 01101 10101 000

Multiplication



SIGNED MAGNITUDE MULTIPLICATIONMultiplication

Hardware Bs

B Register Sequence Counter

Complementer andParallel Adder

As

0 E AC Q Register

QsQn

Algorithm

EAQ

B <- Multiplicand BQ <- MultiplierA

As,Qs <- Qs Bs

A <- 0, E <- 0SC <- n-1

Q0

EA <- A + B

shr EAQSC <- SC+1

= 0 =1

SC=0

= 0ENDProductin AQ



BOOTH MULTIPLICATION ALGORITHM FOR SIGNED 2’S COMPLEMENT

Multiplication

Multiplier Strings of 0’s: No addition; Simply shifts Strings of 1’s: String of 1’s from mp to mq: 2p+1 - 2q

Example 001110 (14) -> p = 3, q = 1 001110 = 23+1 - 21

M * 14 = M24 - M21

Algorithm [1] Subtract multiplicand for the first least significant 1

in a string of 1’s in the multiplier [2] Add multiplicand for the first 0 after the string of 1’s in the multiplier [3] Partial Product does not change when the multiplier bit is identical to the previous bit

110010 = -24 + 22 - 21 = -16 + 4 - 2 = -14

subtract subtract 24 21

Add 22



BOOTH ALGORITHM FOR SIGNED 2’S COMPLEMENT

Multiplication

AC <- 0Q-1 <- 0SC <- n

B <- Multiplicand BQ <- Multiplier A

AC<-AC+B’+1 AC <- AC + B

10 01Q-1 : shifted out bit on shr of Q

Q0Q-1

?

ashr(AC&Q)SC <- SC + 1

SC?

=0

END

0

1100



EXAMPLE OF BOOTH MULTIPLIERMultiplication

B = 10111Q0Q-1 B’+1=01001 AC Q Q -1 SC

10

1101

0010

InitialSubtract B

ashrashrAdd B

ashrashrSubtract B

ashr

00000 10011 0 101010010100100100 11001 1 10000010 01100 1 011101111100111100 10110 0 01011110 01011 0 00101001 0011100011 10101 1 000



ARRAY MULTIPLIERMultiplication

A = a1a0: MultiplierB = b1b0: Multiplicand

C = B * A = c3c2c1c0

c3 c2 c1 c0

b1 b0

a1 a0

a1b1 a1b0

a0

a1

b1 b0

b1 b0

HA HAC S C S

c3 c2 c1 c0

a0b1 a0b0



ARRAY MULTIPLIER 4-BIT X 3-BITMultiplication

a0

a1

a2

b3 b2 b1 b0

Addend Augend

4-bit AdderSum and Carry Outputs

Sum and Carry Outputs

4-bit AdderAddend Augend

0

c6 c5 c4 c3 c2 c1 c0

b3 b2 b1 b0

b3 b2 b1 b0



DIVISIONDivision

A / B = Q + R A: Dividend; B: Divisor; Q: Quotient; R: Remainder

Divisor B = 10001, B’+ 1 = 01111

Dividend:shl EAQadd B’+1E=1Set Q0=1shl EAQAdd B’+1E=1Set Q0=1shl EAQadd B’+1E=0; Q0=0add Brestore remaindershl EAQadd B’+1E=1 Set Q0=1shl EAQadd B’+1E=0; Q0=0add Brestore remainderneglect Eremainder in Aquotient in Q

01110 00000 50 11100 00000 011111 010111 01011 00001 40 10110 00010 011111 001011 00101 00011 30 01010 00110 011110 11001 00110 100011 01010 20 10100 01100 011111 000111 00011 01101 10 00110 11010 011110 10101 11010 100011 00110 11010 0

00110 11010

E A Q SC



FLOWCHART OF DIVIDE OPERATION

Dividend in AQDivisor in B

Qs As Bs

SC<- n - 1shl EAQ

E

EA A+B Q0 1

SC SC-1

EA A+B EA A+BDVF 1 DVF 0

END(Divide overflow)

END(Quotient in Q

Remainder in R)

1

0(A<B) A B

0

Division

EA A + B’+1

A B A<B

E1 0EA A+B’+1 A A+B’+1

E

SC 0



FLOATING POINT ARITHMETIC OPERATIONSFloating Point Arithmetic

Bs B b BR

F = m x re

where m: Mantissa r: Radix e: Exponent

Registers for Floating Point Arithmetic

Parallel AdderEParallel Adder

and Comparator

As A1 A a AC

Qs Q q QR



FLOATING POINT ADD AND AUBTRACTFloating Point Arithmetic

BR AC

A<-A’+1As<-A’s

E

A1 AC<-0

shr AA1<-Ea<-a+1

shl Aa<-a+1

END

0 0

1 1

sub add

a<b a>b

add

sub

=0

=0

AlignMantissa

+ or - ofmantissa

Normalization

CHECK

FOR 0

0 0

AC<-BR

op

As<-A’s

a:b

shr Aa <- a+1

shr Bb <- b+1

op

As Bs As Bs

EA<-A+B’+1 EA<-A+B

A

0

1=0 0

E



FLOATING POINT MULTIPLICATIONFloating Point Arithmetic

AC <- 0

shl AQa <- a-1

END(Product is in AC)

=0

=0

0

1

BR <- MultiplicandQR <- Multiplier

BR

0

QR

0

a <- qa <- a+ba <- a-bias

Multiply mantissa(finxed point multiplication)

A1



FLOATING POINT DIVISIONFloating Point Arithmetic

QR <- 0

divideby 0

=0

0

=0

0

1

A>=B A<B

BR<-DivisorAC<-Dividend

BR

0AC

Qs <- As + BsQ<-0

SC<-n-1

EA <- A+B’+1

E

A <- A+Bshr A

a <- a+1

A <- A+B

a <- a+b’+1a <- a+bias

q <- a

Divide Magnitude of mantissa as in fixed point numbers



BCD ADDBCD Arithmetic

BCD digit < 10BCD digit + BCD digit + carry =< 19

Binary Sum BCD SumK Z8 Z4 Z2 Z1 C S8 S4 S2 S1 Decimal0 0 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 0 0 1 10 0 0 1 0 0 0 0 1 0 20 0 0 1 1 0 0 0 1 1 30 0 1 0 0 0 0 1 0 0 40 0 1 0 1 0 0 1 0 1 50 0 1 1 0 0 0 1 1 0 60 0 1 1 1 0 0 1 1 1 70 1 0 0 0 0 1 0 0 0 80 1 0 0 1 0 1 0 0 1 90 1 0 1 0 1 0 0 0 0 100 1 0 1 1 1 0 0 0 1 110 1 1 0 0 1 0 0 1 0 120 1 1 0 1 1 0 0 1 1 130 1 1 1 0 1 0 1 0 0 140 1 1 1 1 1 0 1 0 1 151 0 0 0 0 1 0 1 1 0 161 0 0 0 1 1 0 1 1 1 171 0 0 1 0 1 1 0 0 0 181 0 0 1 1 1 1 0 0 1 19



BCD ADDER

If we can convert Binary Sums to BCD Sum ,we can use a binary adder to add two BCD numbers

BCD Arithmetic

4-bit Binary Add

0

0

1

00

BCD Sum<-Sum + 0110BCD C<-Carry(BCD Sum)

1

1

1

Take nexthigher digit

done?

BCD Sum = SumBCD C<-Carry(Sum)

END

19 >= SUM > 9 BCD Sum = Binary Sum + 0110 BCD Carry = Carry(Binary Sum + 0110)

SUM =< 9 BCD Sum = Binary Sum BCD Carry = Binary Carry

K

Z8

Z4

Z2



BCD ADDER HARDWAREBCD Arithmetic

Carry In

Addend Augend

4-bit Binary AddrKCarry Out

Z8 Z4 Z2 Z1

BCD Carry

0

0 1 1 0

4-bit Binary Adder

S8 S4 S2 S1



DECIMAL ARITHMETIC OPERATIONSDecimal Arithmetic

Addition

- Identical to the BCD addition - 9’s complement and 10’s complement are identical to 1’s complement and 10’s complement, respectively

Documents

Computer Arithmatic