Digital Design Review

Carlos Luis Bernal

Basic Logic Gates

Designing with NAND and NOR

Gates

Implementation of NAND and NOR

gates is easier than that of AND and

OR gates (e.g., CMOS)OR gates (e.g., CMOS)

Implementation

VDDVDD

A+B

B

A

B

A

A&BA+B

A

Designing with NAND and NOR

Gates

a ~& b

a ~| b

1

a & b

a | b

a ^ b 1

0

~a

a ^ b

a ~^ b

Y = ( A | B )

A

B

Y = ( A & B )AB

Y = ~( A & B )AB

A Y = ~A

B

Y = ~ ( A | B )

A

Y = ~ ( A ^ B )

AB

Y = ( A ^ B )

A

B

Combinational Logic

Has no memory => present state depends

only on the present input

X = x x ... x

))t(X(F)t(Z =

x1x2

xn

z1z2

zm

X = x1 x2... xn

Z = z1 z2... zm

Combinational-Circuit Building

Blocks

Multiplexers

Decoders

Encoders Encoders

Code Converters

Comparators

Adders/Subtractors

Multipliers

Shifters

Multiplexer

Have number of data inputs, one or more select

inputs, and one output

It passes the signal value on one of data inputs to

the output

s w0

(a) Graphical symbol

f

s

w0

w1

0

1fs

w0

w1

(c) Sum-of-products circuit

(b) Truth table

0

1

fs

w0

w1

10 sww'sf +=

4 To 1 MuxS0

S1

D0

D1 Y

Combinational circuit that selects binary information from one of many inputs lines

Selection of a particular input line is controlled by a set of selection input variables

There are 2n input lines and n selection inputs

D2

D3

F( X, Y, Z) = m(1, 2, 6, 7)

X Y Z F

m0 0 0 0 0

m1 0 0 1 1

m2 0 1 0 1

m3 0 1 1 0

m4 1 0 0 0

S0

S1

D0

D1

D2 F = m1 + m2 + m6 + m7

X

Y

Z

Using Multiplexers for

combinational functions

m4 1 0 0 0

m5 1 0 1 0

m6 1 1 0 1

m7 1 1 1 1

D2

D3F = m1 + m2 + m6 + m7

0

1

Multiplexer provides a method of implementing any a Boolean function of n variables with a multiplexer that has n - 1 selection inputs

The first n - 1 variables of the function are connected to the selection inputs of the multiplexer.

The remaining single variable of the function is used for the data inputs. If the single variable is denoted by Z, each data input of the multiplexer will be either Z, Z, 1, or 0

Multiplexers: 4-to-1 Multiplexer

f

s 1

w 0 w 1

00

01

w 0 w 1

s 0

w 2 w 3

10

11

0

0

1

1

1

0

1

f s 1

0

s 0

w 2 w 3

s 1

w 0

w 1

s 0

(b) Truth table

1 1 3

f

(c) Circuit

w 1

w 2

w 3

(a) Graphic symbol

301201101001 '''' wsswsswsswssf +++=

Multiplexers: Building Larger

Mulitplexers

0

w 0 0

s 1

s

s 1

w 0

s 0

w 3

w 4 s 2 0

w 1

0

1

w 2

w 3

0

1

f 0

1

w 8

w 11

4

w 7

w 12

w 15

s 3

2

f

(a) 4-to-1 using 2-to-1

(b) 16-to-1 using 4-to-1

Synthesis of Logic Functions

Using Muxes

f

w 1

0

1

0

1

w 2

1

0

0

0

1

1

1

0

1

f w 1

0

w 2

1

0

(a) Implementation using a 4-to-1 multiplexer

(b) Modified truth table

0

1

0

0

1

1

1

0

1

f w 1

0

w 2

1

0

f

w 2

w 1

0

1

f w 1

w 2

w 2

(c) Circuit

Synthesis of Logic Functions

Using Muxes

w3

w3

w

00

0

1

1

0

fw1

0

w2

0 0

0 1

1 0

0

0

0

w1 w2 w3 f

0

0

03

f

w1

0

w2

1

(a) Modified truth table (b) Circuit

1

1

0

1 11 1 1

0 0

0 1

1 0

1 1

0

1

1

1

0

1

1

1

1

w3

D0

D1

D2

D3

S0

Y

Demultiplexers

D3

S1

The data input Y has a path to all four outputs, but the input information is directed to only one of the outputs, as specified by the two selection lines S1 and S0

The demultiplexer circuit shows that it is identical to a 2 to 4 line decoder with enable input, with F as the enable input Although the two circuits have different applications, their logic diagrams are exactly the same. For this reason, a decoder with enable input is referred to as a decoder/demultiplexer

Half Adder

Half

Adder

X

Y

S

C

(X + Y)

C = X.Y

S = X'.Y + X.Y' = XY

X Y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

X

YS

C

Full Adder

Module Truth table

XYCin'Cin'XY'YCin'XCin'Y'XSum +++=XYCin'XYCinCin'XYYCin'XCout +++=

(XY)X

Y S

(XY)

C = X.Y + (XY).Z

S = (XY)Z

C

Z

N bits Adder

C1

Y1 X1

FA

C2

C5

Y2 X2

FA

C3

Y3 X3

FA

C4

Y4 X4

FA

Ci+1 = Xi .Yi + (Xi Yi ) .Ci

Si = Xi Yi Ci

S1

C5

S2S3S4

Output

Input

Adder cum Substractor

X2 X1

Y4 Y3 Y2 Y1

X4 X3

S

Analysis:

If S=1, then

X + (1's complement of Y) +1

appears as the result.

If S=0, then X+Y appears as

the result.

4-bit

parallel adder

S2 S1S4 S3

C CinCout

A 4-bit adder cum subtractor

ComparatorsLet A = A3A2A1A0 , B = B3B2B1B0; xi = Ai.Bi + Ai'.Bi'

A2

A3

B3

x3

x2

A3'.B3A3.B3'

A3'.B3 + x3.A2'.B2

+ x3.x2.A1'.B1

B2

A0

B0

A1

B1

(A < B)

(A > B)

(A = B)

x2

x1

x0

+ x3.x2.A1'.B1

+ x3. x2.x1.A0'.B0

A3.B3' + x3.A2.B2'

+ x3.x2.A1.B1'

+ x3. x2.x1.A0.B0'

x3. x2.x1.x0

Decoders: n-to-2n Decoder Decode encoded information: n inputs, 2n

outputs

If En = 1, only one output is asserted at a time

One-hot encoded output One-hot encoded output m-bit binary code where exactly one bit is set to

1

0

w n 1

n

inputs

EnEnable

2 n

outputs

y 0

y 2 n 1

w

Enww...wy

...

En'ww'...wy

Enw'w'...wy

En'w'w'...wy

n

n

n

n

n 01112

0112

0111

0110

=

=

=

=

Decoders: 2-to-4 Decoder

y w w En y y y

0

0

1

1

0

0 1

0

0

1

1

1

0

0

1

1

1

0

0

2

0

1

0

3

0

0

0

w 1

w 0

y 0

y 1 1

1

0

1

x x 0

1

1

0

0

0

0

0

0

1

0

0

0

1

0

(a) Truth table

w 0

En

y 0 w 1 y 1

y 2 y 3

(b) Graphic symbol

(c) Logic circuit

y 2

y 3

En

Decoders: 3-to-8 Using 2-to-4

w 2

w 0 y 0 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

w 1

3 En 3

w 0

En

y 0 w 1 y 1

y 2 y 3

y 4 y 5 y 6 y 7

En

Decoders: 4-to-16 Using 2-to-4

w 0 y 0 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

w 0 y 0 w 1 y 1

y 2

y 4 y 5 y 6

w 1

w 0

En

y 0 w 1 y 1

y 2 y 3

y 8 y 9 y 10y 11

w 2 En

y 2 y 3

y 6 y 7

w 0

En

y 0 w 1 y 1

y 2 y 3

y 12y 13y 14y 15

w 0

En

y 0 w 1 y 1

y 2 y 3

w 3

En

Encoders Opposite of decoders

Encode given information into a more compact form

Binary encoders

2n inputs into n-bit code

Exactly one of the input signals should have a value of 1,

and outputs present the binary number that identifies which input is equal to 1

Use: reduce the number of bits (transmitting and storing information)

2 n

inputs

w 0

w 2 n 1

y 0

y n 1

n outputs

Encoders: 4-to-2 Encoder

0

0 1

w 3 y 1

0

y 0

w 1

w 0

0

0

w 2

0

0

w 1

1

0

w 0

0

1

y 0

1

1

0

1

(b) Circuit

0

1

1

0

0

0

0

0 w 2

w 3 y 1

(a) Truth table

Priority Encoders

Each input has a priority level associated

with it

The encoder outputs indicate the active

inputinput

that has the highest priority

d

0

0

1

0

1

0

w0 y1

d

y0

1 1

0

1

1

1

1

z

1

x

x

0

x

w1

0

1

x

0

x

w2

0

0

1

0

x

w3

0

0

0

0

1

(a) Truth table for a 4-to-2 priority encoder

Code Converters

Convert from one type of input encoding to a

different output encoding

E. g., BCD-to-7-segment decoder

c e

(a) Code converter

w 0

a

w 1

b

c

d w 2 w 3

e

f

g

a

g

b f

d

(b) 7-segment display

1

0

1

1

1

1

1

w 0 a

1

b

0 1

1

1

1

0

1

1

0

1

0

0

w 1

0

1

1

0

0

w 2

0

0

0

0

1

w 3

0

0

0

0

0

c

1

0

1

0

0

1

1

0

1

1

1

0

0

0

0

1

1 0 0 1

1

1

1

1

0

1

1

0

1 1

1

1

1

1

1

0

1

1

1

d

0

1

0

0

1

0

e

1

0

1

1

1

0

1

0

0

1

0

0

0

1

f

1

0

0

1

1

1

g

1

0

1

1

1

1

1

1

0

1

(c) Truth table

Connecting Building Blocks: Tristate

Logic and Busses

Four kinds of tri-state buffers

B is a control input used to enable and

disable the outputdisable the output

Data Transfer Using Tristate Bus

Laws and Theorems of Boolean

Algebra

Laws and Theorems of Boolean

Algebra

Sequential Circuits

Circuits with Feedback

Outputs = f(inputs, past inputs, past outputs)

Basis for building "memory" into logic circuits

Door combination lock is an example of a sequential Door combination lock is an example of a sequential

circuit

State => memory

State is can be "output" and "input" to combinational

logic or to other sequential logic

"1"

"stored value"

Simplest Circuits with Feedback Two inverters form a static memory cell

Will hold value as long as it has power applied

"remember"

"load""data"

"stored value"

"0"

"stored value"

How to get a new value into the memory

cell?

Selectively break feedback path

Load new value into cell

Combinational

Logic: :inputs outputs: :

General CircuitM

Mem

ory

Clocks

Used to keep time

Wait long enough for inputs to settle

Then allow to have effect on value stored

period

duty cycle (in this case, 50%)

Clocks are regular periodic signals

Period (time between ticks)

Duty-cycle (time clock is high between ticks -

expressed as % of period)

Edge-Triggered Flip-Flops

Positive edge-triggered

Inputs sampled on rising edge; outputs change after

rising edge

Negative edge-triggered flip-flops

positive edge-triggered FF

negative edge-triggered FF

D

CLK

Qpos

Qpos'

Qneg

Qneg'

100

Inputs sampled on falling edge; outputs change after

falling edge

D Q

CLK

positiveedge-triggered

flip-flop

D

CLK

Comparison of Latches and

Flip-Flops

behavior is the same unless input changeswhile the clock is high

flip-flop

D QG

CLK

transparent(level-sensitive)

latch

Qedge

Qlatch

Timing Methodologies

Rules for interconnecting components and clocks Guarantee proper operation of system when strictly

followed

Approach depends on building blocks used for memory elementsmemory elements Focus on systems with edge-triggered flip-flops

Found in programmable logic devices

Basic rules for correct timing: (1) Correct inputs, with respect to time, are provided to

the flip-flops

(2) No flip-flop changes state more than once per clocking event

Definition of terms

clock: periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level

setup time: minimum time before the clocking event by which the input must be stable (Tsu)

hold time: minimum time after the clocking event until which the

there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized

clock

data

changingstable

input

clock

Tsu Th

clock

dataD Q D Q

hold time: minimum time after the clocking event until which the input must remain stable (Th)

Typical Timing Specifications

Positive edge-triggered D flip-flop

Setup and hold times

Minimum clock width

Propagation delays (low to high, high to low, max and

typical)

all measurements are made from the clocking event that is,

the rising edge of the clock

typical)

Th5ns

Tw 25ns

Tplh25ns13ns

Tphl40ns25ns

Tsu20ns

D

CLK

Q

Tsu20ns

Th5ns

Synchronous vs.

Asynchronous Designs Clocked synchronous circuits

Inputs, state, and outputs sampled or changed in relation to a

common reference signal (the clock)

Asynchronous circuits

Inputs, state, and outputs sampled or changed independently

of a common reference signal (glitches/hazards a major of a common reference signal (glitches/hazards a major

concern)

Stay away from asynchronous designs!

Asynchronous inputs to synchronous circuits

Inputs can change at any time, will not meet setup/hold times

Dangerous, synchronous inputs are greatly preferred

Cannot be avoided (e.g., reset signal, memory wait, user

input)

Solution: synchronize with clock as early as possible !

S

R

Q

Q

S R Q Q

0 1 1 0

1 1 1 0

1 0 0 1

1 1 0 1

Latches

0 0 1 1 (forbidden)

D

E

Q

Q

E D Q Q

1 0 0 0

1 1 1 0

0 x no change

S

C

R

S

C

R

Q

Q

D

Clk E D Q Q

1 0 0 0

1 1 1 0

0 x no change

Flip Flops

CLK E

CLK

CLK

E

Flip Flops

JK Flip-Flop SR Flip-Flop J K Q+ Operation S R Q+ Operation

0 0 Q no change 0 0 Q no change

0 1 0 Reset 0 1 0 Reset

1 0 1 Set 1 0 1 Set

1 1 Q Complement 1 1 ? Undefined 1 1 Q Complement 1 1 ? Undefined

D Flip-Flop SR Flip-Flop

D Q+ Operation T Q+ Operation

0 0 Reset 0 Q no change 1 1 Set 1 Q Complement

Q0

Q1

D Q

C

D Q

Load

D0

Registers with Parallel load

Q2

Q3

D Q

C

D Q

C

D Q

C

D1

D2

D3

Clock

SERIN

CLOCK

Shift registers

CLOCK

SEROUT

Shift registers with parallel load

Used in serial communications applications

0

1

2

3

D Q

S0

S1

S0

S1

Q0/Sup

D0

S1 S2 Operation

0 0 0 No change

1 0 1 Shift down

2 1 0 Shift up

3 1 1 Parallel load

Bidirectional shift register with

parallel load

0

1

2

3

D Q

0

1

2

3

D Q

S0

S1

0

1

2

3

D Q

S0

S1

Q3/SDW

Q1

Q2

S3

S2

D1

Ring Counters

Johnson Counter

Binary Counters

Using Serial Enable logic Using Parallel Enable logic