Datapath Architecture

Department of Computer ScienceSouthern Illinois University Edwardsville

Fall, 2015

Dr. Hiroshi FujinokiE-mail: hfujino@siue.edu

DatapathArchitecture/001

CS 312 Computer Organization and Architecture

Processor

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What is “datapath”?

Memory

Instructions(Machine Code)

Datapath

Datapath: The way instructions are beingexecuted inside a processor

CS 312 Computer Organization and Architecture

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The four datapath architectureswe are going to review in this Chapter (Chapter 3)

The two datapath architecturesWe are going to review in Chapter 8.

Six different datapath architectures

(1) General-Purpose CISC/special-purpose RISC Processors:

(2) Super Computers/Mainframes:

Scalar Processors

Pipeline Processors

Super-Scalar Processors

(i8086)

(i80486)

Super-Pipeline Processors (i80586 – P54)

Vector Processors

VLIW Processors

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1. Scalar Datapath Processors

Processor

IF ID EX ME WB

Datapath

• The datapath includes the five circuit units

• All five units are implemented as single monolithic unit

• When an instruction is being executed, no other instruction can enter the datapath

IF: Instruction Fetch ID: Instruction Decode EX: Execution

ME: Memory access WB: Write Back to registers

CS 312 Computer Organization and Architecture

IF ID EX ME WB

Clock Cycles1 2 3 4 5 6 7 8 9 10

IF ID EX ME WBIF ID EX ME WB

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CPI = 5.0

1. Scalar Datapath Processors (continued)

Representative processors in this generation

i4004, i8080, i8086, i80816, Z80, MC68000

CS 312 Computer Organization and Architecture

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2. Pipeline Datapath Processors

Processor

• All five units are implemented as independent units

• When an instruction is completed in a unit, the instruction can be forwarded to the next unit

• All five units can be occupied by different instructions

IF ID EX ME WB

Datapath

CS 312 Computer Organization and Architecture

Representative processors in this generation

i80386, i40846, MC68040, ….

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Clock Cycles1 2 3 4 5 6 7 8 9 10

IF ID EX ME WBIF ID EX ME WB

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CPI = 2.0

8 cycles / 4 instructions

2. Pipeline Datapath Processors (continued)

CPI for these only forthese four instructions

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3. Super-Scalar Datapath Processors

Processor

IF ID EX ME WB

Datapath #1

• Multiple Scalar Datapath

IF ID EX ME WB

Datapath #2

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IF ID EX ME WB

Clock Cycles1 2 3 4 5 6 7 8 9 10

IF ID EX ME WB

IF ID EX ME WBIF ID EX ME WB

IF ID EX ME WBIF ID EX ME WB

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CPI = 2.5

15 cycles / 6 instructions

3. Super-Scalar Datapath Processors (continued)

CS 312 Computer Organization and Architecture

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4. Super-Pipeline Datapath Processors

Processor

• A combination of super-scalar and pipeline

IF ID EX ME WB

Datapath #1

IF ID EX ME WB

Datapath #2

CS 312 Computer Organization and Architecture

IF ID EX ME WBIF ID EX ME WB

Clock Cycles1 2 3 4 5 6 7 8 9 10

IF ID EX ME WBIF ID EX ME WB

IF ID EX ME WBIF ID EX ME WB

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CPI = 1.16

7 cycles / 6 instructions

4. Super-Pipeline Datapath Processors (continued)

Representative processors in this generation

Pentiums (54, P55C), MIPS R10000, ….CPI for these only forthese six instructions

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Representative processors in this generation

C-90 and Y-MP (Cray), VAX 9000 (Digital), …

Clock Cycles1 2 3 4 5 6 7 8 9 10

EX2

EX3

EX4

EX5

EX6

EX2

EX3

EX4

EX5

EX2

EX3

EX4

IF ID EX1 ME WBIF ID EX1 ME WB

IF ID EX1 ME WB

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5. Vector Datapath Processors (continued)

CS 312 Computer Organization and Architecture

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Processor

• An extension of scalar datapath architecture

• Multiple execution units

IF ID ME WB

Datapath

EX1

EX2

EX3

EX4

EX5

CS 312 Computer Organization and Architecture

6. VLIW Datapath Processors (continued)

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• Each instruction has to have multiple operations in it

OPEX1

OPEX2

P11 P12 P21 P22

256 bits in Transmeta Crusoe TM8000

Operator 1 Operator 2

OPEX5

P52P51

Operator 5

• Each operator corresponds to an instruction in scalar machine

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6. VLIW Datapath Processors (continued)

Representative processors in this generation

TI TMS320C6200, Philips TM1000, Transmeta Crusoe, …

1 2 3 4 5 6 7 8 9 10

EX2

EX3

EX4

EX5

EX6

EX2

EX3

EX4

EX5

EX2

EX3

EX4

IF ID EX1 ME WBIF ID EX1 ME WB

IF ID EX1 ME WB

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6. VLIW Datapath Processors (continued)

1 2 3 4 5 6 7 8 9 10

EX2

EX3

EX4

EX5

EX6

EX2

EX3

EX4

EX5

EX2

EX3

EX4

IF ID EX1 ME WBIF ID EX1 ME WB

IF ID EX1 ME WB

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6. VLIW Datapath Processors (continued)

• Processor resources are very efficiently used

• Only if most of the execution units are used

Who should make sure this?

VLIW can be pipelined ….

Very low CPI (< 1.0) possible

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