Decoders and Trees

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4#תרגול

Decoder’(n)

Decoder(n) design shown and proven in class:

for k = n-1:

Decoder(1)

Decoder’(n)

Decoder’(n) is a private case of Decoder(n) design. (k = n-1 or k = 1)

Decoder’(n) is a correct implementation of a decoder.

otherwise22)1(

1n if1 INVcANDcnc

INVcnc n

Cost analysis:

Solving the recurrence:

INVcANDcncnc n 21

INVcnANDcc nn 12221 21

ANDcINVcnn

1212

21

2

ANDcINVcn n 42 1

n2

:1n

asymptotics

otherwise1,max

1n if)(

ANDdndINVd

INVdnd

ANDdndINVdnd 1,max

ANDdnd 1

ANDdnd 11

ANDdnINVd 1

n Linear Delay!!!

Delay analysis:

Solving the recurrence:

:1n

otherwise0

0:10:112,mod 222

nn xIiA

n

otherwise0

:1:11

2

22

2

nn nxnIiB n

Decoder(n) for k = n/2

Consider the top two recursion steps:

each AND-gate in the “AND-gates array” of the second recursion step, i.e. Decoder(n/2), feeds 2n/2 AND-gates in the “AND-gates array” of the primary recursion step, i.e. Decoder(n).

22 net a offanout Maximumn

otherwise22

1n if

2 ANDcc

INVcnc nn

n2

otherwise

1n if)(

2 ANDdd

INVdnd

n nlog

Design

n

Decoder(n)

k=n/2

Decoder’(n)

111

233

457

8715

16931

Design

n

Decoder(n)

k=n/2

Decoder’(n)

111

21010

45260

86161024

16132304262152

Cost

Delay

Balanced Trees

OR

OR-Tree(n/2) OR-Tree(n/2)

2n

2n

otherwise

1n if0

2 ORddnd

n

ORdnnd 2log

Logarithmic Delay Lower Bound Theorem: Let C = < G , N > denote a combinational circuit that implements a non-constant Boolean function f: {0,1}n → {0,1}.If the fan-in of every gate in G is at most c, then the delay of C is at least logc|cone(f)|.

cone(ORn) = n

fan-in ≤ 2delay(ORn) ≥ log2(n)·d(OR)

Delay of the balanced tree is minimized.

Recursive algorithm for computing an OR-tree(n)

1. The case that n ≤ 2 is trivial.

2. If n > 2, then let a, b be any pair of positive integers such that

(i) n = a + b and (ii) max{log2a , log2b} ≤ log2n - 1.3. Compute an OR-tree(a) and an OR-tree(b).

Connect their outputs to an OR-gate to obtain an OR-tree(n).

Claim: the above algorithm computes a minimum delay OR-tree.

We first show that for every n > 2 there exist a pair of positive numbers a, b such that:

nba (i)

1loglog,logmax (ii) 222 nba

kn 2 if

1loglog,logmax obviously, 222 nba

1k 1k

1k 22 if kn ka 2 ka 2log

kknb 22 kb 2log

1log2 kn

122

:pairsuch one exists there knba

:set

Note that this is the most unbalanced partition of n, and still we get the minimal delay.

Proof:

Induction hypothesis:

Induction step: we prove the claim for n,

ORdbtreeORdatreeORdntreeORd ,max

ORdORdba 22 log,logmax

ORdORdn 1log2

ORdkktreeORdnk 2log.

ORdn 2log

hypothesis induction

We prove by induction on n that the delay of the computed OR-tree is log2n ·d(OR) to obtain delay minimality.

Induction basis: n = 1 or n = 2 are trivial cases.

11 bufferc

11 bufferd

2fanout

A balanced tree structure minimizes the delay and cost.

The tree is a binary tree due to fan-out limitations.

buffer1

bufferdnnd 11log2

buffercnnc 12

Notice: * The leaves of the tree feed the gate outputs.

* The root of the tree is fed by the gate input.

* The first branching is free → no need for a “root” gate.

Buffers

bufctreebufc

INVcANDcncncn

n

1212

211

bufc

INVcANDcncn

n

132

21

Cost analysis:

1-buf-trees

INVcc 1

:1n

:1n

Fanout limitation effect on design2fanout

ANDd

nd

treebufdbufd

treebufdINVd

nd n

n

1

211

21

max 1

1

Delay analysis:

INVdd 11-buf-trees

ANDd

nd

bufdn

bufdnINVd

1

1

11

max

:1n

:1n

ANDdtreebufddndn

n 2212

22 2122

22 2

nn

treebufc

ANDccnc nn

Cost analysis:

Delay analysis:

bufc

ANDccnn

nn

1222

22

221

2

INVcc 1

INVdd 1

ANDdbufdd nn 1122

:1n

:1n

:1n

:1n

1-buf-trees

Cost Decoder(n):n=1: 1n=2: 10n=4: 52n=8: 616n=16: 132304n=32: 8.5902e+009n=64: 3.68935e+019n=128: 6.80565e+038

Cost Decoder‘(n):n=1: 1n=2: 10n=4: 60n=8: 1024n=16: 262152n=32: 1.71799e+010n=64: 7.3787e+019n=128: 1.36113e+039

Cost Decoder‘(n), Fanout<=2:n=1: 1n=2: 11n=4: 79n=8: 1511n=16: 393175n=32: 2.57698e+010n=64: 1.1068e+020n=128: 2.04169e+039

Cost Decoder(n), Fanout<=2:n=1: 1n=2: 10n=4: 68n=8: 1096n=16: 263312n=32: 1.71801e+010n=64: 7.3787e+019n=128: 1.36113e+039

Delay Decoder(n):n=1: 1n=2: 3n=4: 5n=8: 7n=16: 9n=32: 11n=64: 13n=128: 15

Delay Decoder‘(n):n=1: 1n=2: 3n=4: 7n=8: 15n=16: 31n=32: 63n=64: 127n=128: 255

Delay Decoder‘(n), Fanout<=2:n=1: 1n=2: 4n=4: 8n=8: 16n=16: 32n=32: 64n=64: 128n=128: 256

Delay Decoder(n), Fanout<=2:n=1: 1n=2: 3n=4: 6n=8: 11n=16: 20n=32: 37n=64: 70n=128: 135