Embed Size (px)
Citation preview
Design/Technology Co-Optimisation (DTCO) in the Presence of Acute
Variability A. Asenov1,2, E. A. Towie1!
!1Gold Standard Simulations Ltd
2Glasgow University !
Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!! 10nm FinFETs: Si vs. Ge !! Conclusions!
Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!! 10nm FinFETs: Si vs. Ge !! Conclusions!
The semiconductor industry is facing atomic scale limitations !
!!
The simulation!Paradigm now
A 22 nm MOSFET!In production 2013
A 4.2 nm MOSFET!In production ???? A. Asenov 1998!
Statistical variability is one of the major challenges associated with scaling !
Variability results in higher parametric yield loss!
After K. Takeuchi (NEC)!
Random dopants! Metal Gate Granularity! Line edge roughness!
Main sources of statistical variability
Statistical variability in 20nm CMOS
0
20
40
60
80
100
σV T [m
V]
RDDLERMGGRDD+LER Gate LastCOMBINED Gate First
NMOS PMOS
0.05 1.0 -0.05 -1.0Drain Bias [V]
P. Zuber, IMEC!
Saturation in performance and increasing variability drives the CMOS innovations!
M Bohr (Intel)!
FinFETs improve performance and can reduce statistical variability!
Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!! 10nm FinFETs: Si vs. Ge !! Conclusions!
Intel 22nm FinFETs
Intel 22nm FinFETs
3D Ensemble MC simulation provide predictability
Quantum confinement!is important !
DD! MC!
Non-equilibrium transport !is also important!
Electron energy! Electron velocity!
Intel 22nm FinFETs
Intel 22nm FinFETs
Intel 22nm FinFETs
10 15 20 25 30 35 40L [nm]
707580859095
100
I ON [μA
]
Fin 1Fin 2Fin 3Rect (W=10nm)Rect (W=8nm)
Rectangular fins have 15% higher performance for equivalent width and height.!
Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!
" Predictive TCAD simulation!" Statistical CM extraction!" Statistical Circuit simulation!
! 10nm FinFETs: Si vs. Ge !! Conclusions!
The GSS Tool Suite that enables the Design Technology Co-Optimization flow
8!
MYSTIC!
Statistical Compact
Model Extractor!
RANDOM SPICE!
Statistical Circuit
Simulator!
3D !DD/MC/NEGF! Simulator!!
GARAND!
Structure! translator from! TCAD process!simulator!
MONOLITH!
FLOW CONTROL!Input files generator, job submission, execution monitoring!
DATABASE CONTROL!Data harvesting, annotation, storage!
The GSS Tool Suite that enables the Design Technology Co-Optimization flow
8!
MYSTIC!
Statistical Compact
Model Extractor!
RANDOM SPICE!
Statistical Circuit
Simulator!
3D !DD/MC/NEGF! Simulator!!
GARAND!
Structure! translator from! TCAD process!simulator!
MONOLITH!
FLOW CONTROL!Input files generator, job submission, execution monitoring!
DATABASE CONTROL!Data harvesting, annotation, storage!
The statistical device simulator GARAND
14nm DG FinFET specification
Wfin
tox
Hfin
LG
BURIED OXIDE
SUBSTRATE
SOURCE
GATE
DRAIN
HM
Dimension! Min (nm)! Max (nm)!
Fin Width! 8! 12!Fin Height! 22! 28!
Gate Length! 18! 22!
T=85°C VDD = 0.9V! NMOS! PMOS!
ION (mA/µm )! 0.9! 0.8!IOFF (nA/µm )! 10! 10!DIBL(mV/V) ! 56! 65!SS(mV/Dec) ! 86! 88!
" Double gate FinFETs targeted at 14nm technology node.
" Devices targeted for high performance SRAM application.
" Process variation aware design.
10!
The role of predictive MC simulations
0 10 20 30 40 50 60X Position [nm]
0.0
0.5
1.0
1.5
2.0
2.5
Veloc
ity [x
107 cm
s-1 ]
DDMC
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9VG [V]
0.0001
0.001
0.01
0.1
1I D
[mA
/m
]MCDD (calibrated)DD (default)
0.0
0.5
1.0
1.5
2.0
LG = 20nm
" Only EMC simulations can predict performance.
" Quantum corrections are essential.
" DD simulations can be calibrated to EMC.
Quantum effects
are very important 11!
Process induced variability
0.0392
0.0394
0.0396
0.03960.0398
0.0398
0.04
0.04
0.04
0.0402
0.0402
0.040
2
Gate length (nm)
Fin
wid
th (n
m)
18 19 20 21 228
8.5
9
9.5
10
10.5
11
11.5
12
IODsat (mA)
" Captured by experiment design.
" Dependence on L, HF, WF, TOX.
12!
Statistical Variability Simulations RDD!
GER+FER!
MGG!
15!
Nominal Device Statistical Variability!
Correlation between subthreshold figure of merits, such as IOFF and DIBL, can be a good indicator to show whether MGG is an active variability source.
17!
Correlation between process and statistical variability
18!
Statistical aspects of Reliability
Fresh!
With degradation!
0.1 0.15 0.2 0.25 0.3 0.35 0.4VT (V)
-4
-2
0
2
4
Nor
mal
Qua
ntile
01E115E111E12
Trapping Density (cm-2)
19!
Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!
" Predictive TCAD simulation!" Statistical CM extraction!" Statistical Circuit simulation!
! 10nm FinFETs: Si vs. Ge !! Conclusions!
The GSS Tool Suite that enables the Design Technology Co-Optimization flow
8!
MYSTIC!
Statistical Compact
Model Extractor!
RANDOM SPICE!
Statistical Circuit
Simulator!
3D !DD/MC/NEGF! Simulator!!
GARAND!
Structure! translator from! TCAD process!simulator!
MONOLITH!
FLOW CONTROL!Input files generator, job submission, execution monitoring!
DATABASE CONTROL!Data harvesting, annotation, storage!
Statistical Compact Modeling Procedure!
Process Variaiton
Aware Device TCAD
Design
Process Variation
Aware Statistical
Device Simulation
Extended Uniform
Device Compact
Modelling
Extended
Statistical Device
Compact Modelling
Unified Statistical Compact Model Libraries
21!
The Statistical Compact Model Extractor Mystic
Advanced Data Preprocessing
Multi-Stage Fitting Strategy
Mystic Optimisation Engine
Mystic Device DatabaseDevice Measurement
Advanced Data Preprocessing
Statistical Fitting Strategy
Statistical Device
Measurement
Uniform Compact Model
Averaged Compact Model
Uniform Compact Model
Uniform Compact Model
RandomSpice Model Library
P
P
P
O P OP
PO
Extended Uniform Model – Group 1 Parameter!
22!
Statistical Compact Modeling!
Strong correlation between statistical compact model parameter and device figure of merit demon-strates that extraction is physics based !
25!
Statistical Compact Modeling – Group 2 parameter!
27!
Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!
" Predictive TCAD simulation!" Statistical CM extraction!" Statistical Circuit simulation!
! 10nm FinFETs: Si vs. Ge !! Conclusions!
The GSS Tool Suite that enables the Design Technology Co-Optimization flow
8!
MYSTIC!
Statistical Compact
Model Extractor!
RANDOM SPICE!
Statistical Circuit
Simulator!
3D !DD/MC/NEGF! Simulator!!
GARAND!
Structure! translator from! TCAD process!simulator!
MONOLITH!
FLOW CONTROL!Input files generator, job submission, execution monitoring!
DATABASE CONTROL!Data harvesting, annotation, storage!
The Statistical Circuit Simulation Engine RandomSpice
Statistical Parameter Generation
Compact Model Library
TemplateCircuit
RandomSpice Engine
Statistical Enhancement
Engine
AnalysisDatabase
SPICE
-+
PerformancePower Yield
FinFET based SRAM design
29!
1-1-1 Cell! 2-3-3 Cell!
Cell design trade off
Metal Gate Work-Function Engineering!
31!
Interplay between CD and statistical variation !
" Slow corner has the best SNM performance.
" CD variation can introduce 10% degradation on standard deviation of SNM.
34!
Reliability Aspect of SRAM Performance!
" Under N/PBTI stress condition, SNM can be degraded by more than 25%
" However, write operation can be improved under stress condition
35!
Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!! 10nm FinFETs: Si vs. Ge !! Conclusions!
10nm FinFET options: FinFET design
Wfin
tox
Hfin
LG
STI
SUBSTR
ATE
SOURCE
GATE
DRAIN
Band structure in UTB devices (in collaboration with A. Asluger & P. Sushko, UCL)
1.2 nm! 2.9 nm! 12.1 nm!
First-Principles Informed Simulations
DG quantum corrections Base on 1D Poisson-Schrodinger solver
Performance based on MC simulations
Carrier velocities
Simulation of statistical variability
Simulation of statistical variability
Nominal compact models
0"
0.5"
1"
1.5"
2"
2.5"
3"
3.5"
4"
Intrinsic"Transistors"
Extracted"netlists"
100"M1"track"wire"
load"
500"M1"track"wire"
load"
Normalized
+Delay+
Inverter+
Si"
Ge"
0"
0.5"
1"
1.5"
2"
2.5"
3"
3.5"
4"
4.5"
Intrinsic"Transistors"
Extracted"netlists"
100"M1"track"wire"
load"
500"M1"track"wire"
load"
Normalized
+Delay+
23Input+NOR+
Si"
Ge"
Ge is 0.38% faster
Ge is 2.26% slower
Ge is 2% faster
Ge is 3.5% slower
Impact of Extraction and Wire-load
Extracted netlists generated using the ARM 10nm Predictive Technology Modeling toolset!!!
Delay vs. Supply Voltage
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
Normalized
Delay
Supply Voltage (V)
Si Ge
Conclusions
! FinFET complexity Motivates Design/Technology Co-Development.!
– 22nm Intel FinFET example ! !! !! We have studied in detail a full DTCO flow for 14nm
FinFETs, showing how GSS simulation platform can help designers from process to devices up to circuit level.!
! We have show an example of applicability of GSS platform for evaluating different option for future FinFETs technology generations. !
!
Thanks for your attention!
You will find this presentation and additional material on our webpage
www.goldstandardsimulations.com
[email protected][email protected]!
!
