Development Tools for the Cal Poly SuPER Project

Using the Digilent Spartan 3E FPGA Board

By

Khanh Van Nguyen

Senior Project

COMPUTER ENGINEERING DEPARTMENT

California Polytechnic State University

San Luis Obispo

2009

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TABLE OF CONTENTS

Section Page

List of Tables and Figures …………………………………………………… 3

Acknowledgements ………………………………………………………….. 4

I. Introduction ……………………………………………………………… 5

II. Background ……………………………………………………….……… 6

III. Requirements ……………………………………………………..……… 8

IV. Hardware Design and Configuration ……………………………..……… 10

A. Universal Asynchronous Receive/Transmit ………………….……… 12

B. PS/2 Keyboard Port …………………………………………..……… 16

C. RS-232 Serial Port …………………………………………………… 17

D. Testing and Verification ……………………………………………… 17

E. Software Integration Recommendations ……………………………… 18

V. Graphic User Interface Overview ………………………………………… 20

A. Design and Construction ……………………………………………… 20

B. Testing and Verification ………………………………………………. 24

C. Future Recommendations ……………………………………………... 25

VI. Conclusion ………………………………………………………………… 26

Appendices

A: Bibliography ………………………………………………………………. 27

B: UCF File ……………………………………………………………………28

C: C Language Source Code …………………………………………………. 29

D: C# Language Source Code …………………………………………………32

E: SuPER Sample Output File ……………………………………………….. 33

F: SuPER Simulated Output File …………………………………………….. 34

G: Senior Project Analysis ……………………………………………………. 35

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LIST OF FIGURES

Figures Page

2.1 – Phase 1 Block Diagram of the SuPER ………………………………………… 7

2.2 – Digilent Spartan 3E Development Board ……………………………………... 7

3.1 – Development Tools Flow Diagram …………………………………………… 9

4.1 – Xilinx EDK Target Device Settings …………………………………………..10

4.2 – System Assembly View of Xilinx EDK System ………………………………11

4.3 – UART Connections within the Xilinx EDK Environment…………………….13

4.4 – Oscilloscope Capture of Keyboard’s Data Line ………………………………13

4.5 – UART OPB Clock Frequency ………………………………………………...14

4.6 – IP Bus Address Assignment …………………………………………………..14

4.7 – External Ports, GPIO, and UART IP Connections ……………………………15

5.1(a) – PV Panel Tab of the Data Analyzer ………………………………………. 21

5.1(b) – Load 1 Tab of the Data Analyzer …………………………………………. 22

5.2 – Data Analyzer File Menu …………………………………………………….. 22

5.3 – The Data Analyzer Program Displaying Graphs …………………………….. 24

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Acknowledgements

I would like to first thank Professor Jim Harris for allowing me to work on

this amazing project. This project teaches me that with a little thought and creativity,

an idea can grow to become a big thing for the benefit of others. Secondly, I would

like to thank Matt Staniszewski for introducing me to this project and also Frank

Scarfo for participating on the same project. Lastly, I would like to thank my family

for all their support as I finish my college career at Cal Poly and move onto the next

part of my life.

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I. Introduction

In July of 2005, Dr. James G. Harris proposed the development of a low-cost,

sustainable source of electrical power with a 20-year life cycle [1]. The project

would utilize solar energy to provide people in underdeveloped countries a power

source without having to go through governmental aid programs. This project came

to be known as the Cal Poly Sustainable Power for Electrical Resources (SuPER).

With Dr. Harris and Dr. Ali Shaban, many electrical and computer engineers

have taken this simple idea and began prototyping this product. The SuPER Project

consists of four subsystems that utilize current technology: fixed solar power panels,

a power control system, energy storage in the form of a car battery, and direct current

(DC) electrical power output interfaces. The idea is that in accordance with Moore’s

Law, as technology advances, the components of the SuPER will be easily obtainable

and affordable, supplying a low-cost source of energy [1].

The SuPER Project is heading towards its next phase of development as the

initial prototype goes through improvements and adjustments to further its progress.

This project contributes to the development into the next stage of the SuPER Project

reducing power consumption from the current laptop and moving towards using the

Digilent Spartan 3E FPGA Development Board.

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II. Background

The system is currently within Development Phase 1 where most of the

modules are designed and created at the California Polytechnic State University. The

exception to this is the PV solar panel, the 12V battery, and the laptop computer. The

laptop computer is used for data sampling as well as power control of the PIC

microcontroller, DC-to-DC converter, and the MOSFET switches as shown in Figure

2.1 [2].

Stated within Brian Estrada and Patrick Mariano’s senior project, we can

replace the existing laptop computer with the Digilent Spartan 3E FPGA

Development Board to reduce the power consumption of the SuPER system itself [3].

The Spartan 3E, shown in Figure 2.2, will also replace the USB-to-Serial Converter,

the PIC microcontroller, and the two National Instrument 6009 DAQ’s.

The Spartan 3E runs on a 50 MHz clock with 50 usable pins to interface the

system. The 4MB of flash memory will be used for the UCLinux operating system

[3]. The on-board ADC and DAC will handle all the existing sensor readings. For

data acquisition and storage, external memory has been suggested in Tony Wonsyld’s

proof of concept [4]. Integrating all these components while using the Xilinx

Embedded Development Kit (EDK), we can design and develop the necessary

components for the next phase of the SuPER.

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Figure 2.1: Phase 1 Block Diagram of the SuPER

Figure 2.2: Digilent Spartan 3E FPGA Development Board

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III. Requirements

As suggested from prior research to this senior project, we are improving and

redeveloping the system to utilize the Digilent Spartan 3E Development Board. This

senior project continues hardware development of the Spartan 3E as well as some

new software development. The hardware consists of tools developed in the Xilinx

EDK environment, and the software development consists of processing and

analyzing data to show useful trends.

The hardware I will develop in the Xilinx EDK environment for the Spartan

3E will be the following intellectual property (IP) cores:

1. Universal Asynchronous Receive/Transmit (UART)

2. PS/2 Keyboard Port

3. RS-232 Serial Port

Two UARTs are used for both the PS/2 port and serial port. The PS/2 port will allow

an external keyboard to connect to the Spartan 3E for user input. The serial port will

allow the acquired data to be output to a hyper terminal console.

I will develop software to process an output data file in the form of a .txt file

from the SuPER and display the information into useful graphs. This software will be

external from the SuPER system. Displaying these graphs will allow anyone to easily

interpret the trends of the working system. I will be coding the software in the C#

language within the Microsoft Visual Studio environment. The software will do the

following:

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1. Provide a user-friendly interface allowing ease of use

2. Processing the sample output file by parsing the data

3. Display the following data into graphs:

a. PV Voltage, Current, and Temperature Averages

b. Battery Voltage, Current, and Temperature Averages

c. DC-to-DC Voltage, Current, and Temperature Averages

d. Various Load Voltage and Current Averages

4. The software must be able to expand for future implementations

Below is a flow diagram of how my development tools can be used. Figure

3.1 shows how the keyboard is used for input on the Spartan 3E via the PS/2 port and

then becomes serial output to the screen on an external computer. When the Spartan

3E board is fully implemented into the SuPER, it should store the output files on an

external storage device. Using these output files, the Data Analyzer is used for

displaying graphs on the external computer.

Figure 3.1: Development Tools Flow Diagram

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IV. Hardware Design and Configuration

All the hardware I have developed for this project has been under the Xilinx

EDK environment. Within this environment, the system developed contains a

Microblaze soft-core processor connected to local memory bus (LMB) lines to Block

RAM (BRAM) for the system’s memory. The processor takes inputs and sends

outputs to the general purpose input/output (GPIO) devices via the on-chip peripheral

bus (OPB) line. The general process of setting up the system can be followed by

Tom Hickok’s EDK Tutorial [5].

First I created the new project by selecting a Blank XPS project and clicking

OK. After determining the target location of the project files, I configured the target

device fields as shown in Figure 4.1. For those attempting to reproduce any Xilinx

EDK Project, be sure that the target location of the project files does not contain any

spaces, as your project will not compile later.

Figure 4.1: Xilinx EDK Target Device Settings

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Next, I added the non-bus intellectual property (IP) cores. Within the IP

Catalog tab of the Project Information Area of the Xilinx EDK, I added one

Microblaze soft-core processor, two LMB BRAM controllers, and one BRAM block.

This is similar to the Tom’s EDK Tutorial [5], and as the tutorial suggests, these IP

cores’ names were reconfigured. Following that, I added two LMB buses and one

OPB bus to connect the processor to the local memory (LMB) and the processor to

the on-board peripherals (OPB). I established the appropriate connections with the

internal bus ports in the System Assembly View as shown in Figure 4.2.

This is the general Microblaze soft-core processor set-up for the system.

Beyond this is adding the necessary components for the UART, PS/2 keyboard port,

and the RS-232 serial port.

Figure 4.2: System Assembly View of Xilinx EDK System

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A. Universal Asynchronous Receive/Transmit

For this project, two universal asynchronous receive/transmit (UART) devices

were used. As the name suggests, UARTs are used for sending data to other devices

that do not have to use the same clock timing. For hardware purposes, both UARTs

are configured similarly within the Xilinx EDK.

Under the IP Catalog tab in the EDK environment, two OPB UART (Lite)

devices from the Communication Low-Speed section are added. Within the System

Assembly View, both UARTs should be connected to the OPB as shown in Figure

4.3. Both UARTs need to be configured to fit the system, so we can access the

properties by double-clicking the UARTs.

The UART for the PS/2 port has to be configured for the specific keyboard I

am using, so I needed to change the OPB Clock Frequency. This is determined by

powering the keyboard with 5V and using an oscilloscope. I needed to capture the

data line and clock line; by pressing a key down, I measured the frequency of the scan

code which shows up (see Figure 4.4). Referencing the oscilloscope capture, I used

the space bar for my scan code of 29, as described in the Spartan 3E User Guide [6].

The keyboard clock is active low, and the scan code begins with a 0 for a start bit and

ends with a parity bit and a 1 for a stop bit. After measuring the width of the scan

code with the cursors, I took the period, multiplied it by 11 bits and used the

following equation for the OPB Clock Frequency:

FrequencyClockOPB

RateBaud

ClockMhz

HzWidthCodeScan )(9600

50

)(

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I determined this frequency to be 36,923,077 Hz and set it as shown in Figure 4.5.

Figure 4.3: UART Connections within the Xilinx EDK Environment

Figure 4.4: Oscilloscope Capture of Keyboard’s Data Line

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Figure 4.5: UART OPB Clock Frequency

After the two UARTs are added and configured, I continued setting-up the

hardware. I needed to assign the IP bus addresses for all the IP Cores which can be

done by clicking on the Addresses button in the Filters area of the System Assembly

View. The DBRAM controller and IBRAM controller’s size are set to 8K and the

GPIOs will be set to 512. After clicking on Generate Addresses, the configuration is

as shown in Figure 4.6.

Figure 4.6: IP Bus Address Assignment

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Once the IP bus addressing is done, I connected the internal and external nets

by loosely following the EDK tutorial. All GPIOs’ OPB_Clk will be set to the added

external port sys_clk with the GPIO_IO made external. The two UARTs will have

their OPB_Clk and OPB_Rst set to sys_clk and added external port sys_rst

respectively. The UART settings and external ports are shown in Figure 4.7.

Afterwards, any bus width for GPIOs can be determined by the tutorial [5].

Figure 4.7: External Ports, GPIO, and UART IP Connections

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Next, I generated the netlist and add the software application project by

following the EDK tutorial. By selecting Generate Netlist from the Hardware menu,

the Xilinx EDK will begin to compile the hardware and make sure everything is

connected correctly. Once the hardware assembles with zero errors, I selected

Generate Libraries and BSPs from the Software menu. Then, I added software to the

project by clicking Add Software Application Project in the Applications tab of the

Project Information Area. The Xilinx EDK environment allowed me to write our

code within the C Language and compile it to the Microblaze soft-core processor.

The code I have written for this project is contained within Appendix: C. Now the

RS-232 Serial Port and PS/2 Keyboard Port can be configured. This can be done by

simply connecting the IP cores from the system to the according pins of the Spartan

3E board. These two devices are described in the next two sections below.

B. PS/2 Keyboard Port

The Digilent Spartan 3E FPGA board has a standard 6-pin mini-DIN built-in

PS/2 port. This port allows a keyboard or mouse to be connected to the Spartan 3E.

For the purposes of the hardware in this project, I have used the PS/2 port strictly for

the keyboard. The system.ucf constraints file in Appendix: B shows the receive line

connected to pin G13 as described in the Spartan 3E Manual [6]. I did not need to

connect the transfer side of the UART to any part of the PS/2 port because the

keyboard is only used for input purposes.

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C. RS-232 Serial Port

The Spartan 3E has two RS-232 serial ports – a female DB9 DCE connector

and a male DTE connector. For the context of this project, the DCE-style port is used

to connect a serial cable to an external computer. Along with the code in Appendix:

C, we can forward the data processed by the Spartan 3E and display it within a hyper

terminal console. To configure the serial port, I connected pins R7 and M14

respectively to the receive pin and transmit pin of the UART used for the RS-232 as

described in the Spartan 3E Manual [6].

D. Testing and Verification

Once the hardware configuration has been set and the bitstream is updated

within the Xilinx EDK environment, I can download the bitstream to the Spartan 3E

and test the C language code using Xilinx iMPACT which comes with Xilinx ISE

v9.1. After connecting the USB-based download/debug port to the external

computer, I opened Xilinx iMPACT. Selecting create a new project (.ipf), I selected

Configure Devices Using Boundary-Scan (JTAG). I opened the download.bit file

from the Xilinx EDK project to program the XC3S500E and bypass the other two

components. Finally, I programmed the Spartan 3E board.

Testing the hardware system is simple. I connected my external keyboard to

the PS/2 port and my computer to the RS-232 port with a serial cable. After I

programmed the Spartan 3E as described above, I opened up a hyper terminal. I

configured the hyper terminal’s baud rate to 9600; this is the same as the baud rate of

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the RS-232’s UART I configured in Xilinx EDK. To know whether or not the system

is working, I typed a few characters onto the keyboard. The program in Appendix: C

will print the input scan code as the ASCII value onto the LCD and forward the data

to the serial port. This way, I can debug the data from the hyper terminal to match

that of the LCD. If the characters are not correctly displaying within the hyper

terminal, this means that the baud rate was not configured correctly.

E. Software Integration Recommendations

The use of the keyboard and serial port can be useful for future

implementations of the SuPER project. Once the next phase of the SuPER project is

complete, the Spartan 3E will run stand-alone using UCLinux as suggested by Brian

Estrada and Patrick Mariano [3]. The existing implementations of Phase 1 of the

SuPER use a laptop to run code for data acquisition. We can use the keyboard to run

the data acquisition code in UCLinux and use the serial port to display the data via a

hyper terminal.

There are a few improvements to my keyboard implementation. With my

implementation, the code will constantly poll to see if a key is pressed. I suggest

using the interrupt line from the UART and an interrupt service routine to handle

keystrokes. By using interrupts, the C language code will also have to be altered. As

of now, the code works so that when a key is pressed, two scan codes are sent to the

Spartan 3E. From here, only one scan code is processed, and printed. The problem

that arises is if there is someone who can type fast, then some scan codes are lost and

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some are repeated. As well, the C language code that I have provided only allows the

user to type the mapped keys. This only pertains to the lower case letters and because

only one shift code is processed at a time, capital letters are not included within this

set. Using shift and then a letter involves two separate scan codes; this issue should

be resolved before fully using the keyboard implementation.

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V. Graphic User Interface Overview

The graphic user interface portion of my senior project is a completely new

concept for the SuPER project. The idea arose from the idea of processing the output

information from the data acquisition into graphs for easy interpretation. I decided to

construct the graphic user interface (GUI) using C# within the Microsoft Visual

Studio environment. Visual Studio offers an easy solution to build my solution.

Within the next several sections, I will describe the process of building the GUI, how

I tested my program, and future recommendations to improve it.

A. Design and Construction

As stated above, I used the Microsoft Visual Studio environment to build what

I called the SuPER: Data Analyzer. Before any initial programming of the GUI was

written, I had to design a simple layout of the program. Using some sample output

from the SuPER (see Appendix: E), I noticed that data values were acquired for the

PV solar panel, the battery, the DC-to-DC converter, and five various loads. For the

PV panel, battery, and DC-to-DC converter, three different values are written to the

output file: voltage, current, and temperature. For the loads, voltage and current are

obtained from the SuPER system. With eight different sets of data, I decided to use a

tab control in C# to conserve some space. This also allows me to separate the data by

component, only displaying relevant data together.

Each tab contains two or three graphs, depending on the component. The

graphs are designed to be 300 by 300 pixels as picture boxes. Each picture box has a

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background picture of a grid which I created. This grid has a gray background with

15 by 15 pixel grid boxes. Each graph was labeled based on the sample output file. I

determined that the voltage for the PV panel ranges from 0 to 60V, the battery voltage

ranges from 0 to 16V, and DC-to-DC component ranges from 0 to 40V. The current

for these three range from -4.0 to 4.0 A, -12.0 to 12.0 A, and -2.0 to 2.0 A

respectively. The temperature ranges from 0 to 40°C. Using a television for the

loads, the voltage ranges from 0 to 12V and -2.0 to 2.0 A for voltage and current

respectively. All the voltage, current, and temperature ranges were determined in

Tyler Sheffield’s thesis [2] and sample output files. These increments can be changed

within the C# code by multiplying the parsed data by the proportion of pixels for one

unit. For example, if the PV Panel’s voltage was from 0 to 40V, then we obtain the

factor by taking 300 pixels and diving by 40 V, giving 7.5 pixels per one volt. The

GUI is shown in Figure 5.1 (a) and (b).

Figure 5.1 (a): PV Panel Tab of the Data Analyzer

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Figure 5.1 (b): Load 1 Tab of the Data Analyzer

Because the graphs take a lot of space, I decided to add a menu bar for

opening and closing the data file. Selecting Open Data File from the File menu

allows the user to select the file from the user’s hard drive. Close Data File will close

the file and Exit quits the Data Analyzer. The file menu is shown in Figure 5.2. The

Info displays information about the program.

Figure 5.2: Data Analyzer File Menu

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Once an output file is opened, the filename including its path is displayed at

the bottom left corner. The file is then parsed by the program and stored within

arrays. To simplify the programming, I decided to parse lines of data values and store

the values accordingly within the arrays. A sample of this output file is shown in

Appendix: F. The program uses the Drawing and Graphics libraries to instantiate a

pen object and draws upon these picture box graphs. The values from the output file

are computed to correlate to coordinates on the graphs and then drawn by the pen

object. All the code for the design layout and program implementation can be found

in Appendix: D.

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B. Testing and Verification

There were three different phases of testing and verification to the Data

Analyzer. The first step was viewing the layout of the compiled program. Each

graph and each label needed to be given specific coordinates to assure the alignment

within the program.

The second step was to assure that I could read the data file. To test if my

program was reading in the data correctly, I first made the stream reader output to the

console within the Microsoft Visual Studio environment. Then, I placed these values

within the arrays of data to make sure I was parsing the data correctly. After that, I

had to figure out how to draw lines.

Using the Visual C# Developer Center [7], I coded the Pen object and made

sure the lines were being drawn onto the graphs. Once this was completed, I had to

compute the coordinates for displaying the lines on the graphs. This was merely an

easy conversion of the parsed data and multiplying it by a factor to correlate to the

units in the graph. The finished product shows the graphs correctly (see Figure 5.3).

Figure 5.3: The Data Analyzer Program Displaying Graphs

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C. Future Recommendations

The Data Analyzer was designed to work the sample file that I originally

obtained from the SuPER project. There are several recommendations that I would

suggest to improve this GUI.

The first thing I would recommend is some error checking with file opening.

Currently, the program does not check to see whether it is a SuPER output file; it only

needs a .txt file. It would be easy to implement some code to display an error box

saying that the text file is not a SuPER output file based on the first line read in. I

would also recommend either implementing the parsing to the Data Analyzer to deal

with actual SuPER data. This is because an actual output file has labels. Although

this is the case, it would probably be easier to change the output code from the

SuPER to follow this format.

Dealing with data parsing, the graphs will only display the first twenty data

points. I would suggest improving the code to dynamically display the data graphs.

There could possibly be a scroll bar that will allow the window to slide around a time

frame. Also, a zoom on the graphs could be implemented. It could be possible to

also parse data in real-time and serially read in data via the serial port.

The last recommendation would be to improve the drawn lines within the

code. For some reason, the lines drawn will erase from the graphs if the window is

dragged outside the computer screen or if another window is dragged on top of the

Data Analyzer. I temporarily fixed this by adding a Refresh Graphs button in the

bottom right that will redraw the graphs when needed.

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VI. Conclusion

This project involved designing and implementing development tools for the

Digilent Spartan 3E FPGA Development Board. This board will be used for the next

phase of the SuPER Project which will replace the existing laptop and reduce the

power consumption of the system. The Spartan 3E will also reduce the number of

parts within the system and reducing the number of components is directly correlated

to reducing failure.

I hope the tools I have developed will allow the SuPER Project to progress.

The PS/2 port can be used to connect a keyboard to the Spartan 3E for debugging

purposes. The RS-232 serial port can be used for outputting the data to the screen for

debugging purposes as well. The Data Analyzer can be used to display the SuPER

output into easily interpretable graphs for analysis.

All the implementations in this project are fully functional, but I have also

recommended quite a few improvements in each section. If any of these components

are used in the future implementations of the SuPER Project, I would recommend

some or all of the improvements of my development tools.

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Appendix A: Bibliography

[1] J. G. Harris. (2005, Jul.). “White Paper for Sustainable Power for Electrical

Resources – SuPER,” [Online] Available: http://courseware.ee.calpoly.edu/

~jharris/research/super_project/white_paper_susper.pdf. (10 Jan. 2009).

[2] T. Sheffield. (2007, Apr.). “Cal Poly SuPER System Simulink Model and Status

and Control System,” [Online] Available: http://courseware.ee.calpoly.edu/

~jharris/research/super_project/ts_thesis.pdf. (31 May 2009).

[3] B. Estrada & P. Mariano. (2008, Jun.). “Development of UCLinux Platform for

Cal Poly SuPER Project,” [Online] Available: http://courseware.ee.calpoly.

edu/~jharris/research/super_project/be_pm_sp.pdf. (27 Jan. 2009).

[4] T. Wonsyld. (2008, Dec.). “Proof of Concept Implementation with the Spartan 3E

Evaluation Board for the Cal Poly SuPER Project,” [Online] Available: http://

courseware.ee.calpoly.edu/~jharris/research/tw_sp.pdf. (1 Jun. 2009).

[5] T. Hickok. (2008, Sep.). “Embedded Developers Kit EDK 9.1i Tutorial,” [Online]

Available: http://courseware.ee.calpoly.edu/cpe329/EDK_Resources/

EDK_Tutorial.pdf. (12 Feb. 2009).

[6] Xilinx, Inc. (2006, Mar.). “Spartan-3E Starter Kit Board User Guide,” [Online]

Available: http://www.digilentinc.com/Data/Products/S3EBOARD/

S3EStarter_ug230.pdf. (24 Mar. 2009).

[7] Microsoft Developer Network. (2009). Visual C# Developer Center. Microsoft

Corporation. [Online] Available: http://msdn.microsoft.com/en-

us/vcsharp/default.aspx. (8 Apr. 2009).

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Appendix B: UCF Constraints File

# system.ucf file for Spartan 3E Board Project

# System clock source from Spartan 3E Board

NET "sys_clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;

# Reset for system assigned to BTN South

NET "sys_rst" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;

# LED outputs for GPIO to Spartan 3E LEDs: 8 downto 1

NET "led_pin<7>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "led_pin<6>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "led_pin<5>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "led_pin<4>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "led_pin<3>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "led_pin<2>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "led_pin<1>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "led_pin<0>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

#lcd control signal I/O pin assignments

NET "lcd_pin<6>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "lcd_pin<5>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "lcd_pin<4>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "lcd_pin<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "lcd_pin<2>" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "lcd_pin<1>" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "lcd_pin<0>" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

#UART_PS2 pins for data input

NET "uart_ps2_RX" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

#UART_RS232 pins for data output

NET "uart_rs232_RX" LOC = "R7" | IOSTANDARD = LVTTL ;

NET "uart_rs232_TX" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;

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Appendix C: C Language Source Code

#include <xio.h>

#include <xparameters.h>

#include "keyboard.h"

#include "lcd.h"

/* Message Constants */

#define MSG_LEN 13

#define MSG_LEN2 13

void getKeyboard();

main()

{

/* Initialize the LCD */

initLcd(); // Setup LCD for 4-bit communication

XIo_Out32(XPAR_LED_BASEADDR + 4, 0);

/* Getting Keyboard Info */

getKeyboard();

}

void getKeyboard()

{

char letter;

int rStatus = 0, bs = 0, j = 0, dataValid = 0, data;

int idx = 0;

for ( ;; )

{

rStatus = XIo_In32(XPAR_UART_PS2_BASEADDR + 8);

if (rStatus & 0x01)

{

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if(dataValid == 0)

{

data = XIo_In32(XPAR_UART_PS2_BASEADDR);

dataValid++;

XIo_Out32(XPAR_UART_PS2_BASEADDR + 12, 0x03);

}

}

switch (data)

{

case 0x15: data = 'q'; break;

case 0x1D: data = 'w'; break;

case 0x24: data = 'e'; break;

case 0x2D: data = 'r'; break;

case 0x2C: data = 't'; break;

case 0x35: data = 'y'; break;

case 0x3C: data = 'u'; break;

case 0x43: data = 'i'; break;

case 0x44: data = 'o'; break;

case 0x4D: data = 'p'; break;

case 0x1C: data = 'a'; break;

case 0x1B: data = 's'; break;

case 0x23: data = 'd'; break;

case 0x2B: data = 'f'; break;

case 0x34: data = 'g'; break;

case 0x33: data = 'h'; break;

case 0x3B: data = 'j'; break;

case 0x42: data = 'k'; break;

case 0x4B: data = 'l'; break;

case 0x1A: data = 'z'; break;

case 0x22: data = 'x'; break;

case 0x21: data = 'c'; break;

case 0x2A: data = 'v'; break;

case 0x32: data = 'b'; break;

31

case 0x31: data = 'n'; break;

case 0x3A: data = 'm'; break;

case 0x29: data = ' '; break; /* Space */

default: data = 0x00; dataValid = 0;

}

if (dataValid)

{

letter = data;

XIo_Out32(XPAR_LED_BASEADDR, letter);

if (idx == 0)

{

printLcd(&letter);

XIo_Out32(XPAR_UART_RS232_BASEADDR + 4, letter);

}

idx = (idx + 1) % 2;

}

}

}

32

Appendix D: C# Language Source Code

(Please reference my senior project CD for the C# language source code. These

source code files include SuPER.Designer.cs and SuPER.cs. To view the complete

solution on the CD, please use the Microsoft Visual Studio environment.)

33

Appendix E: SuPER Sample Output File

(Edited for Relevant Data)

----------PV Averages------------

voltage = 14.026299

current = -0.020687

temperature = 24.543805

----------Batt Averages------------

voltage = 12.498643

current = 0.027688

temperature = 23.674121

----------DC-DC Averages------------

voltage = 12.556636

current = -0.187664

temperature = 24.153205

----------LOAD1 Averages------------

voltage = 0.053950

current = 0.045019

----------LOAD2 Averages------------

voltage = 0.054662

current = -0.020821

----------LOAD3 Averages------------

voltage = 0.055176

current = -0.033356

----------PV Averages------------

voltage = 14.048359

current = -0.069973

temperature = 24.627621

----------Batt Averages------------

voltage = 12.492516

current = 0.116528

temperature = 23.674121

----------DC-DC Averages------------

voltage = 12.549505

current = -0.220730

temperature = 24.183861

----------LOAD1 Averages------------

voltage = 0.055989

current = 0.022977

----------LOAD2 Averages------------

voltage = 0.060784

current = -0.097987

----------LOAD3 Averages------------

voltage = 0.062276

current = -0.149017

----------PV Averages------------

voltage = 14.030310

current = -0.026163

temperature = 24.543805

----------Batt Averages------------

voltage = 12.490473

current = 0.018804

temperature = 23.684331

----------DC-DC Averages------------

voltage = 12.531170

current = -0.171131

temperature = 24.051021

----------LOAD1 Averages------------

voltage = 0.049872

current = -0.004576

----------LOAD2 Averages------------

voltage = 0.051602

current = 0.045322

----------LOAD3 Averages------------

voltage = 0.050104

current = 0.010706

----------PV Averages------------

voltage = 14.058387

current = -0.053544

temperature = 24.585713

----------Batt Averages------------

voltage = 12.488431

current = 0.152064

temperature = 23.694540

----------DC-DC Averages------------

voltage = 12.536263

current = -0.160109

temperature = 24.265608

----------LOAD1 Averages------------

voltage = 0.055989

current = 0.022977

----------LOAD2 Averages------------

voltage = 0.059763

current = -0.048380

----------LOAD3 Averages------------

voltage = 0.058219

current = -0.149017

34

Appendix F: SuPER Simulated Output File

15.23948

1.23984

30.23948

13.83458

0.83489

38.67849

5.76548

-1.87842

18.4888

0.04578

1.83848

0.01892

-1.02389

0.05489

1.58388

13.34888

1.83848

35.77433

11.83849

0.98943

32.88883

3.38289

-0.53999

15.28839

0.01292

-1.59932

0.05900

0.03848

0.06889

1.20399

12.83489

0.98388

12.84588

15.38384

0.57368

32.88828

10.83878

0.58738

11.38488

0.03843

-0.10093

0.03888

1.38488

0.06888

0.850998

8.48888

0.00000

32.00388

17.37489

0.45889

18.48800

5.23849

0.93847

25.3848

0.01283

-1.28489

0.05899

0.48389

0.03890

-0.93848

13.83458

0.83489

38.67849

8.48888

0.00000

32.00388

11.83849

0.98943

32.88883

0.06889

1.20399

0.01292

-1.59932

0.05900

0.03848

17.37489

0.45889

18.48800

5.23849

0.93847

25.3848

8.48888

0.00000

32.00388

0.03890

-0.93848

0.05899

0.48389

0.05899

0.48389

11.83849

0.98943

32.88883

17.37489

0.45889

18.48800

13.83458

0.83489

38.67849

0.06889

1.20399

0.01292

-1.59932

0.05900

0.03848

7.23948

0.23984

24.23948

10.83458

0.83489

32.67849

9.76548

-0.87842

12.4888

0.01578

1.13848

0.00892

-0.92389

0.02489

1.18388

17.34888

1.13848

25.77433

15.83849

0.58943

35.88883

3.58289

-0.53999

15.58839

0.05292

-1.09932

0.03900

0.01848

0.06889

1.80399

19.83489

0.98388

19.84588

19.38384

0.57368

39.88828

19.83878

0.98738

19.38488

0.04843

-0.40093

0.04888

1.48488

0.04888

0.450998

13.83458

0.83489

38.67849

8.48888

0.00000

32.00388

11.83849

0.98943

32.88883

0.06889

1.20399

0.01292

-1.59932

0.05900

0.03848

8.48888

0.00000

32.00388

17.37489

0.45889

18.48800

5.23849

0.93847

25.3848

0.01283

-1.28489

0.05899

0.48389

0.03890

-0.93848

17.37489

0.45889

18.48800

5.23849

0.93847

25.3848

8.48888

0.00000

32.00388

0.03890

-0.93848

0.05899

0.48389

0.05899

0.48389

11.83849

0.98943

32.88883

17.37489

0.45889

18.48800

13.83458

0.83489

38.67849

0.06889

1.20399

0.01292

-1.59932

0.05900

0.03848

12.58899

-1.39949

24.00399

12.58899

-1.39949

24.00399

12.58899

-1.39949

24.00399

0.05000

-1.39942

0.05000

-1.39942

0.05000

-1.39942

(This file is represented in columns to conserve space)

35

Appendix G: Senior Project Analysis

Summary of Function Requirements

As described within my requirements section, I described three different

development tools for my project. These tools consist of the PS/2 port, the RS-232

serial port, and a data analyzer. The PS/2 port allows keystrokes to be pressed and

processes the scan codes to ASCII values correctly. The RS-232 serial port, which is

fully functional, can simply be used to output data to an external computer. The data

analyzer parses data correctly and display them in graphs on the program.

Primary Constraints

There were not too many limiting factors within this project. Most of the

development tools were independent to the others working on the SuPER Project.

The only limitation I feel is that my implementations could have progressed more if

the others’ implementations were complete. One example of this is my data analyzer

could have been able to deal with serial data processing if the SuPER was already

running on the Spartan 3E FPGA board.

Economic and Manufacturing Issues

There were no economic issues in developing my project. Pertaining to the

SuPER Project in general, the Spartan 3E board costs $149.00. Once the Spartan 3E

board replaces the existing laptop in the system, the cost to produce the SuPER will

drastically decrease, especially since some other components will be replaced by the

36

development board. The total development time for this project took two full

quarters, averaging around ten hours per week.

Environmental, Manufacturability, and Sustainability

The SuPER is the epitome of these three issues. The central idea of the

SuPER Project is to build a self-sustaining power system that converts solar energy

to electrical energy. Building such a self-sustaining system allows us to give a power

supply to those less fortunate in the world without going through government aid

programs. The main idea for manufacturing is that although some of the components

are expensive, as technology improves in the future, these items will become easily

affordable. Lastly, the SuPER Project does not affect the environment on a large

scale. In fact, it probably improves the environment since it utilizes solar power as an

alternate source of energy. The only environmental effect is the battery used in the

SuPER. Disposal of car batteries would be difficult, and battery acid from faulty

batteries would be a bad environmental effect.

Ethical Issues

There are no ethical issues pertaining to this project. The Xilinx EDK

software and Microsoft Visual Studio is supplied from Cal Poly. Any persons

attempting to reproduce this project needs to ethically purchase these software

programs to reproduce these development tools.

37

Health and Safety Issues

There are no particular health and safety issues within this project. Overall,

the SuPER involves converting solar energy to electric power. One safety issue is

dealing with high voltage, and this should be considered when maintaining the

SuPER. Another safety issue is faulty batteries and dealing with leaking battery acid.

Battery acid can be harmful to people and the environment, as described above.

Social and Political Issues

Pertaining to political issues, we must consider the effects of supplying the

self-sustaining SuPER to third-world countries. The SuPER is a powerful tool which

can help underdeveloped countries and provide them the tools to become more

developed societies.

Development Issues

During the course of my project, I learned to use the Microsoft Visual Studio

environment. This project also allowed me to learn a new object-oriented

programming language, C#. As well, I have become more accustomed to reading

data sheets.