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DFTTetraMAX Astro
20141230
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--TetraMAX--Astro*111*
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TetraMAX
Synopsys
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source /opt/demo/synopsys.envtmax &*111*
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TetraMax GUImenu barcommand tool barquick access buttonsStatus
barcommand line windowtranscript window*111*
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--help*111*
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CTRL-C OR CTRL-Break. stop*111*
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ATPG 1.2.3.ATPG4.DRC5.ATPG6.ATPG7.8.*111*
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1.Read Netlist(1/2)TetraMAXVerilogVHDLEDIF (Flat)(Hierarchical)
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1.Read Netlist(2/2)NETLISTread_netlist BUILD-T > read_netlist
mydesign.v*? BUILD > read_netlist design/*/??design*.v *111*
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2.Read Library ModelsVerilogNETLISTread_netlistBUILD-T >
read_netlist smic/smic_40.v *111*
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3.Build ModelATPG BUILD-T> run_build_model top_module_name
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4.Perform Test DRCDRC 1. 2.set/reset
3.clock/set/resetoff4.netsTetraMAXDRCSTIL test protocol file.SPFSPF
DFT Compiler BUILD-T> run_drc filename.spf *111*
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5. Prepare to Run ATPGTEST-T> add_faults all set_patterns
ATPGATPG *111*
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6.Run ATPG TEST-T> run_atpg -auto*111*
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7.Review Results(1/3)report_summariesreport_faults
summary*111*
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7.Review Results(2/3)Fault Collapsing(BUFFER
{A SA0,Z SA0},{A SA1,Z SA1}Z SA0,Z SA1A SA0,A SA1
(collapsed)(uncollapsed)()*111*
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7.Review Results(3/3)(Fault Coverage)vs(Test Coverage)*111*
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8.Saving PatternsSaving patterns presents many choices:STIL,
Verilog, WGL,VHDL, or proprietary Binary outputsCompression
choices: none, GZIP, or proprietaryall or a selected range of
patternsATPG patterns, Chain Test Patterns, Setup, or combos
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TetraMax -- 1.Read Netlistread_netlist
../syn/netlist/top_pad.sv*111*
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TetraMax -- 2.Read Library Modelread_netlist -library
/home/smic/smic_40/SCC40NLL_HS_RVT_V0p1a/verilog/SCC40NLL_HS_RVT_NEG_V0p1.vread_netlist
-library
/home/smic/smic_40/SP40NLLD2RN_3P3V_V0p2/verilog/SP40NLLD2RP_TEMP_V0p0.v
report_modules -summaryreport_modules -error*111*
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TetraMax -- 3.Build Modelrun_build_model top_padreport_summaries
primitivesreport_rules -fail*111*
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TetraMax --4.Perform DRC Checkrun_drc
../syn/netlist/top_pad.spfreport_rules -failreport_nonscan cells
-summaryreport_bus -summaryreport_feedback paths
summaryreport_scan_chains
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TetraMax -- 5.Prepare ATPGset_faults -fault_coverage -model
stuck -summary verboseadd_faults -all
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TetraMax -- 6. ATPGrun_atpg -auto
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TetraMax -- 7.Review Resultsreport_summaries*111*
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TetraMax --8.Saving Patternswrite_faults
./tmax/pattern/top_pad.au -class au -replacewrite_patterns
./tmax/pattern/top_pad_comp.stil -format stil -noexpand_vector
-replace
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ICMatlabModelsimQuestasimMaxplus IIDesign Compiler AstroIC
Compiler Encounter
VLSI MatlabSpectreVirtuoso,LakerCalibreIC *111*
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GDSGraphic Data System, +=*111*
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AstroSynopsysAvanti2002SynopsysApollo2007IC Compiler(ICC) SOC
Encounter Cadence*111*
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AstrodbEncounterASCII.lefAstrocellTerminalEncounter
cellTerminalAstroGDSCEL viewEncounterGDSAstroCalibreCalibre
DRCEncounterCalibre*111*
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Astro AstroIO*111*
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A Standard Cell is a predesigned layout of one specific basic
logic gate Each cell usually has the same standard heightA Standard
Cell Library contains a varied collection of standard
cellsLibraries are usually supplied by an ASIC vendor or library
group Layout View2-Input NAND Gate*111*
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Astro*111*
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--FoundryIPIOSRAMIP----DC(SDCDC)TDF--*111*
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IO IOIOIOIOCorner*111*
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Core AreaPad Area*111*
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PAD Area1Input/Output/InOut pads Reset2Power pads and conner
pads CornerURcorner pads Conner pads Pads() VDD VSSPower pads Power
pads core pads IO pads pads PadPad cell3Pads fillers pads()4P/G
rings pads/padsfillerscornerspad areaP/G rings,padspadsP/G
ring*111*
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IO connerIO pad bottomtopleftrightbottomrighttopleft*111*
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;1.1V digital core power/groundinsertPad "VDD" "PVDD1RN" "VDD"
"VDD"insertPad "VSS" "PVSS1RN" "VSS" "VSS";3.3V digital IO
power/ground dbCreateCellInst (geGetEditCell) "" "PVDD2RN" "VDD_IO"
"0" "No" '(0 0) fsk_0323"dbCreateCellInst (geGetEditCell) ""
"PVSS2RN" "VSS_IO" "0" "No" '(0 0) fsk_0323";Corner
celldbCreateCellInst (geGetEditCell) "" "PCORNERRN" "CORNER1" "0"
"No" '(0 0) " fsk_0323 "dbCreateCellInst (geGetEditCell) ""
"PCORNERRN" "CORNER2" "0" "No" '(0 0) " fsk_0323 "dbCreateCellInst
(geGetEditCell) "" "PCORNERRN" "CORNER3" "0" "No" '(0 0) " fsk_0323
"dbCreateCellInst (geGetEditCell) "" "PCORNERRN" "CORNER4" "0" "No"
'(0 0) " fsk_0323 "tdfPurgePadConstrpad "CORNER1" "Bottom"pad
"CORNER2" "Right"pad "CORNER3" "Top"pad "CORNER4" "Left" pad
"VDD_IO" "left" 1pad "VSS_IO" "left" 2pad "data_in_block" "top"
1pad "fsk_out_block" "top" 2pad "VDD" "right" 1pad "VSS" "right"
2pad "clk_block" "bottom" 2pad "en_block" "bottom" 1IO--tdf
insertPad insertPad netName padCellName padName
connectPindbCreateCellInst dbCreateCellInst cellId childLibName
chlidCellName chilidInstName rotationStr mirrorStr Points
topCellName
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mkdir astro cd astrosource /opt/demo/synopsys.envastro_shell
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help insertPad insertPad *111*
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Technology File:
/home/smic/smic_40/SCC40NLL_HS_RVT_V0p1a/astro/tf/scc40nll_hs_7lm_1tm.tf*111*
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1/3*111*
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VDDVSS2/3*111*
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IO3/3/home/smic/smic_40/SCC40NLL_HS_RVT_V0p1a/astro/SCC40NLL_HS_RVT_V0p1/home/smic/smic_40/SP40NLLD2RN_3P3V_V0p2/apollo/SP40NLLD2RN_3P3V_V0p1_7MT_1TM/
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Cell
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Astro*111*
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IO*111*
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-- /Pad Filler 1.IO2. 3. 1.IO2.(Core)IO/(ring)3.Strap4.ring/IO
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IO *111*
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pad (Pad Limited Design) IOcore(Core Limited Design)SRAMIPPad
LimitedCore LimitedStagger*111*
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Design Setup->setup floorplan *111*
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Core UtilizationRow/Core Ratio1Core Aspect
Ratio(H/W)11Horizontal RowDouble BackStart First RowFlip First
RowRowRowCore To LeftCore To RightCore To TopCore To
BottomCoreIO
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IO*111*
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/ / lR Drop EMElectromigration*111*
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/Pre Route->Connect Ports to P/G*111*
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VDD net type PowerVSS net type Ground/*111*
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/ CoreIO/ring//IO/PreRoute->Rectangular *111*
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/ pad *111*
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Pad Filler Pad FillerIOIOIOPostPlace->Add Pad Fillers
FillerFiller40nm pad filler PFILL20RN PFILL10RN PFILL5RN PFILL2RN
PFILL1RN PFILL01RN PFILL001RN
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(.tf)TLU*111*
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(Placement)*111*
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top_pad.sdcDC:+*111*
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Timing-> Timing Setup 0.1*111*
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InPlace->Placement Common OptionsOptimiaztion
ModeCongestionTiming*111*
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1.InPlace->Auto Place2.StagePre-placeDetail
Options3.Pre-Place optimizationCell Down Size *111*
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SourceSink *111*
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buffer /*111*
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: () ()Clock->Clock Common Options *111*
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Clock->Skew analysis*111*
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0Clock Skewtcl set_propagated_clock [all_clock]*111*
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::Global RouteTrack AssignmentDetail RouteSearch &
Refine*111*
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Astro(grid)Placement gridUnitTileunitTilerowstandard
cellrowunitTilestandard cell
Routing grid Pitch
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(Global Route)*111*
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(Track Assignment)Track assignment trackDRCjogJog*111*
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(Detail route)tracktrackDRCsboxsboxDRC(Search and
repair)DRCsboxDRC*111*
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1. /2. 3456 78*111*
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/*111*
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-- AstroFoundry(.clf) load ()
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CPURoute Setup->Distributed Routing SetupConnect*111*
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DRCCPU CPURoute Setup->Route Common Options *111*
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Route Setup->HPO Signal Route OptionsCharge-Collecting
AntennaadvancedHonor Top-Layer Probe Constraints*111*
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Route->Net Route GroupAll clock netsTrim antenna of user's
wire*111*
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Route->Auto RouteSearch & Repair Loop5 *111*
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DRC-SUMMARY:@@@@@@@ TOTAL VIOLATIONS = 0 (0) //@@@@ Total nets
not meeting constraints = 0 //*111*
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1.-- 2.-- 3.*111*
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1.DRC Astro 2.LVS LVSVerify-> LVS *111*
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LVS*111*
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LVS*111*
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LVS*111*
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--.SDF
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--.sv VerilogLVS*111*
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--.gds GDSCalibre DRC*111*
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TetraMAXFSKsmic 40nmAstroFSK.sv(.sdf).gds
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