Digital IC Design Flow - 國立臺灣大學access.ee.ntu.edu.tw/course/dsd_93second/2005ppt/Lec 2... · 2010-07-14 · Graduate Institute of Electronics Engineering, NTU Digital IC

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Graduate Institute of Electronics Engineering, NTU

Digital IC Design FlowDigital IC Design Flow

Lecturer: 吳安宇Date: 2005.03.04

V1.0: 3/3/2005


pp. 2Huai-Yi HsuDigital IC Design Flow 2005.03.03

OutlineOutlinevMOS TransistorvIntegrated CircuitsvMOS ProcessvMoore’s LawvDesign ChallengevIC Design flow



The MOS TransistorThe MOS TransistorPolysilicon Aluminum/Cu

Channel/Gate length: The distance between Source and Drain

0.18um/0.13um: this year’s main stream90nm: next year



Discrete TransistorsDiscrete Transistors



The First Integrated Circuits The First Integrated Circuits

Bipolar logic1960’s

ECL 3-input GateMotorola 1966

Invented/patented by - Jack Kilby (Texas Instrument, Nobel Laureate)- Bob Noyce (Fairchild)



Intel 4004 MicroIntel 4004 Micro--ProcessorProcessor

19711000 transistors1 MHz operation



Intel Pentium (IV) microprocessor:Intel Pentium (IV) microprocessor:millions of transistorsmillions of transistors



88--inch Waferinch Wafer

An 8-inch (200-mm) diameter wafer containing Intel Pentium 4 processors



Die CostDie Cost

Single die

Wafer

From http://www.amd.com

Going up to 12” (30cm)

http://www.amd.com



The MOS TransistorThe MOS TransistorPolysilicon Aluminum/Cu

Channel/Gate length: The distance between Source and Drain

0.18um/0.13um: this year’s main stream90nm: next year



Patterning of SiO2Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-lightPatternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch



The chip manufacturing processThe chip manufacturing process



oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

PhotoPhoto--Lithographic ProcessLithographic Process



Process v.s. Pizza MakingProcess v.s. Pizza Making



MooreMoore’’s Law:s Law: Driving Technology AdvancesDriving Technology Advances

v Logic capacity doubles per IC at regular intervals (1965).v Logic capacity doubles per IC every 18 months (1975).



Process Technology EvolutionProcess Technology Evolution



Chips SizesChips Sizes

Source: IBM and Dataquest



Shrinking Product CyclesShrinking Product Cycles

v Shrinking product cyclesv Shrinking development turnaround timesv Need for productivity increase (remember the “design gap”)v Note: PCS: 個人通訊服務 (Personal Communication Service)

PCS: Personal Communication Services



Productivity TrendsProductivity Trends

Source: Sematech

Complexity outpaces design productivity

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000Logic Tr./ChipTr./Staff Month.

xxxx

xx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Logi

c Tr

ansi

stor

per

Chi

p(M

)

0.01

0.1

1

10

100

1,000

10,000

100,000

Prod

uctiv

ity(K

) Tra

ns./S

taff

-Mo.

Com

plex

ity

Courtesy, ITRS Roadmap



Design Productivity CrisisDesign Productivity Crisis

v Human factors may limit design more than technology.v Keys to solve the productivity crisis:

v Design techniques: Hierarchical design, SoC design (IP reuse, platform-based design), etc.

v CAD: algorithms & methodology



Increasing Processing PowerIncreasing Processing Powerv Very high-performance circuits in today’s

technologies:v Gate delays: ~27ps for a 2-input Nand in CU11v Operating frequencies: up to 500MHz for SoC/Asic, over

1GHz for custom designs

v The increase in speed/performance of circuits allowed blocks to be reused without having to be redesigned and tuned for each application

v Enhanced Design Tools and Techniques (EDA tools)v Although not enough to close the “design gap”, tools are

essential for the design of today’s high-performance chips



IPIP--Based Based SoCsSoCsv An Evolutionary Pathv Early daysØ IP/Cores not really designed for reuse (no standard

deliverables)ØMultiple Interfaces, difficult to integrate

v IPs evolved: parameterization, deliverables, verification, synthesizable, reusable

v On-Chip bus (OCB) standards began to appear (e.g, IBM, ARM)

v Reusable IP + On-chip bus architecturesv 1998: max number of cores > 30 cores

core content between 50% and 95%



IP / CoresIP / Coresv Soft IP/Corev Delivered as RTL Verilog or VHDL source code with

synthesis script (i.e: clock generation logic)v Customers are responsible for synthesis, timing closure, and

all front-end processingv Firm IP/Corev Delivered as a netlist to be included in customer’s netlist

(with don't touch attribute)v Possibly with placement information

v Hard IP/Corev Due to their complexity, they are provided as a blackbox

(GL1/GDSII). Ex. Processor cores, Analog cores, PLLsv Usually very tight timing constraints. Internal views not be

alterable or visible to the customer



Chasing the Design GapChasing the Design Gap



Changes in the Nature of IC DesignChanges in the Nature of IC Design

(IEEE Spectrum Nov,1996)



Evolution of Silicon DesignEvolution of Silicon Design

Source: “Surviving the SoC revolution – A Guide to Platform-based Design,”Henry Chang et al, Kluwer Academic Publishers, 1999



Methodology Methodology –– Analysis and Verification Analysis and Verification



IC Design and ImplementationIC Design and ImplementationIdea

Design



Types of Types of ASICsASICs



Types of Types of ASICsASICsvFull-custom ASICsvSemi-custom ASICsvCell-based ASICsvGate Array-based ASICs

vProgrammable ASICsvProgrammable logic devicesvField Programmable Gate Array



CMOS ProcessCMOS Process



A Modern CMOS ProcessA Modern CMOS Process

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

DualDual--Well TrenchWell Trench--Isolated CMOS ProcessIsolated CMOS Process



Circuit Design and LayoutCircuit Design and Layout

VDD VDD

Vin Vout

M1

M2

M3

M4

Vout2

Its Layout ViewIts Layout ViewSchematic ViewSchematic View

0 1 0



CMOS Inverter LayoutCMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’





Full-custom Designv Performance at transistor levelv Utilize layout editing toolsv Virtuoso (Cadence, USA)v Laker (SpringSoft, Taiwan)

v Very expensive in design cost and design timev 10-20 gates per week

(low design productivity)

v Used for:v Analogv Leaf cells - libraries, memory cellsv Datapath unit in high performance

designs (ALU in high-end CPU)



Standard Cell Standard Cell -- ExampleExample

3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time



Automatic Cell GenerationAutomatic Cell Generation

Courtesy Acadabra

Initial transistorgeometries

Placedtransistors

Routedcell

Compactedcell

Finishedcell



CellCell--based Design (or standard cells)based Design (or standard cells)

Routing channel requirements arereduced by presenceof more interconnectlayers

Functionalmodule(RAM,multiplier, …)

Routingchannel

Logic cellFeedthrough cellR

ows

of c

ells





Cell-based IC (CBIC) Design



Standard Cell Standard Cell —— ExampleExample

[Brodersen92]



Transition to Automation and Regular StructuresTransition to Automation and Regular Structures

Intel 4004 (Intel 4004 (‘‘71)71)Intel 8080Intel 8080 Intel 8085Intel 8085

Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel



Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

LateLate--Binding ImplementationBinding Implementation



Gate Array Gate Array —— SeaSea--ofof--gatesgates

rows of

cells

routing channel

uncommitted

VD D

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

UncommitedCell

CommittedCell(4-input NOR)



SeaSea--ofof--gate Primitive Cellsgate Primitive Cells

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation



SeaSea--ofof--gatesgates

Random Logic

MemorySubsystem

LSI Logic LEA300K(0.6 µm CMOS)

Courtesy LSI Logic





The return of gate arrays?The return of gate arrays?

metal-5 metal-6

Via-programmable cross-point

programmable via

Via programmable gate array(VPGA)

Exploits regularity of interconnect: Structured ASIC



System SpecificationSystem Specification

From CIC



Algorithm MappingAlgorithm Mapping

RTL Level

System Level

From CIC



Gate and Circuit Level DesignGate and Circuit Level Design

From CIC



Physical Level DesignPhysical Level Design

From CIC



Design Abstraction LevelsDesign Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM



SemicustomSemicustom Design FlowDesign Flow

HDLHDL

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout Simulation

Pre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

StructuralStructural

PhysicalPhysical

BehavioralBehavioralDesign Capture

Des

ign

Itera

tion

Des

ign

Itera

tion



Pre-layout simulation

Post-layout simulation

Logic Design

Physical Design

Circuit extraction



Design FlowDesign Flow

Design Specification

Design Partition

Design Entry-VerilogBehavioral Modeling

Simulation/FunctionalVerification

Design Integration &Verification

Pre-SynthesisSign-Off

Synthesize and MapGate-Level Netlist

Post-Synthesis Design Validation

Post-SynthesisTiming Verification

Test Generation &Fault Simulation

Cell Placement, ScanChain & Clock Tree

Insertion, Cell Routing

Verify Physical &Electrical Design Rules

Extract Parasitics

Post-LayoutTiming Verification

Production-ReadyMasks

Production-ReadyMasks

Front End

Design Sign-Off

Back End



Concept of SynthesisConcept of SynthesisvSynthesis is Constraint DrivenvTechnology Independent



The The ““Design ClosureDesign Closure”” ProblemProblem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)



Behavioral ModelBehavioral Model

Transistor Level

Gate Level

Register Transfer Level

Architecture

Algorithm

Systemconcept

Increasingbehavioralabstraction

Increasingdetailed

realization &complexity



Design Domain (Verification and Design Domain (Verification and Closure)Closure)

Behaviorallevel of

abstraction

Design Model Domain

Abstract PhysicalStructural

System

Algorithm

RTL

Gate

Switch

ArchitectureDesign

StructuralDesign

LogicDesign

LayoutDesign

Verification

Verification

Verification

ArchitectureSynthesis

RTL levelSynthesis

Logic levelSynthesis

Documents

Digital IC Design Flow - 國立臺灣大學access.ee.ntu.edu.tw/course/dsd_93second/2005ppt/Lec 2... · 2010-07-14 · Graduate Institute of Electronics Engineering, NTU Digital IC