Digital System Design IC Contest Cellll--based Designaccess.ee.ntu.edu.tw/course/dsd_97second/lecture/W15_IC_Contest_090527.pdfIC設計競賽簡介 v自86學年度開始舉辦，由教育

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Digital System DesignDigital System DesignIC ContestIC Contest –– CellCell--based Designbased Design

Lecturer: Chih-Hao ChaoAdvisor: Prof. An-Yeu Wu

Date: 2009.5.27 Wednesday

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P2

ICIC設計競賽簡介設計競賽簡介

v 自86學年度開始舉辦，由教育部指導，SoC總聯盟主辦，CIC協辦，各大學電機電子工程學系承辦。

v 競賽項目:v Full custom designv Cell-based design v Analog designv FPGA design

v 依報名隊數決定一階段或兩階段比賽。

v 競爭激烈v 研究所/大學部分組競賽


P3

規則說明規則說明

v 連續12小時之競賽

v 初賽採線上比賽,透過開放式網路下載測資與說明,上傳設計檔案v 初賽須完成Gate-level designv 需要預先安裝好競賽指定之環境 (CAD或是各IC設計實驗室有)v 通常在各校實驗室進行設計

v 決賽採現場比賽,透過封閉式網路下載測資與說明,上傳設計檔案v 決賽須完成Physical design (但不須包含DFT部分)v 環境由CIC準備好，無法更動；各組使用一台工作站，連線到大型主機進行設計。

v 在國家晶片系統設計中心(新竹CIC)進行設計。


P4

評審方式評審方式v初賽：v 將依報名該組之隊伍數及初賽整體表現，由評審委員與主辦單位共同決定最後入選決賽之隊伍數量(N)。若符合設計規格之隊伍數小於N隊，則全數錄取，不足額部份再依設計規格完成度遞錄取。(不論參賽者是否完成電路設計，敬請務必於競賽時間截止前繳交上傳)若符合規格之隊伍數大於N隊，則將依各隊繳交時間順序，先行繳交者優先錄取。

v決賽：v 分組分類個別評選優勝隊伍。

v 主辦單位將對參賽設計進行相關驗證，是否通過驗證將以主辦單位之執行結果為準，而執行結果取得之數據將做為評分依據。

v 進入決賽錄取方式：以完成設計規格為要件，將依傳送時間之先後順序擇優錄取至額滿為止。若錄取不足額，則依設計完整度，擇優錄取未完成隊伍遞補。因此未完成設計者，亦可傳送檔案。（其他規定請參閱題目說明）

v 決賽評分標準：各組之設計結果將分開評比，評分項目含效能、面積、功率、完成度等，評比的標準實際項目將詳列於試題中。


P5

獎勵方式獎勵方式

獎項學生指導老師

特優（一隊）

教育部獎牌一面／每人獎狀(中英文對照)一紙／每人六萬元獎金／每隊

教育部獎牌一面

優等（兩隊）

教育部獎牌一面／每人獎狀(中英文對照)一紙／每人四萬元獎金／每隊


佳作（數隊）

教育部獎狀(中英文對照)一紙／每人兩萬元獎金／每隊


設計完整獎 SoC總聯盟中文獎狀一紙／每人SoC總聯盟中文獎狀一紙


P6

How to Prepare IC Contest?How to Prepare IC Contest?v Form a team: find your partner.v Find a instructor (Professor)v Systematically improve your skill by problems in the

past. http://140.125.35.209/ic_contest_2009/problem.html

vMake a self-examination on each step after each practice.

v Typically, there will be several stepsv Understand the problem and define your strategyv Partition the problem and co-work with your partnerv RTL Coding and Debuggingv Synthesis and gate-level simulationv Layout and post-layout simulation

http://140.125.35.209/ic_contest_2009/problem.html


P7

Understanding the Problem and Understanding the Problem and Define your StrategyDefine your Strategy

v Usually the document has many pages (>15).v In preliminary, you can print 2 copies for each team

and read them in parallel.v In final, you have only 1 hardcopy.

v One of you can prepare the working environment first.v The other can keep about 1 or 2-page ahead, and

pipelined.


P8

Understanding the Problem and Understanding the Problem and Define your Define your Strategy (2)Strategy (2)

v Reading procedures1. Overview/problem description and System block diagram2. Grading method

3. Pin-out table (which describes properties of I/O signals)4. Timing diagram (and note the timing parameters)

5. System function description (takes most time to read!)6. Test data (refine your understanding of the problem)


P9

Understanding the Problem and Understanding the Problem and Define your Define your Strategy (3)Strategy (3)

v Define your strategyv Identify which type of problem it is ØDepends on system function descriptionØ Especially note to grading method

v Typically, the grading method will be:ØArea * Clock period: basic method.ØArea * Total simulation cycle: you don’t need to reduce critical path;

focus on FSM state reduction.ØArea * Total simulation time : may use many design tricks to reduce

the score. Usually there will be several “bonus parts”.ØArea * Total simulation time * Adjustment: may have some trap.ØCompleteness: usually it’s a hard problem. Use more FSM state for

flexibility and then add functionality. Optimize later.ØHybrid


P10

Define Control SchemeDefine Control Schemev Identify by observing I/O signalsv Check the system block diagram, pin-out table, and the I/O

Timing diagrams.

v non-FSM: output timing is determined with very small flexibility. (usually it’s just delayed by several cycles, can be viewed as pure datapath)Ø data output without control signal (valid_out, oen, done, …)Ø testbench assumes data output has regular pattern (w/ or w/o

some indication signal )

v FSM: output timing can be fully controlled in your designØ data output with control control signal (valid_out, oen, done, …)


P11

Example: NonExample: Non--FSMFSM


P12

Example: FSMExample: FSM


P13

More on FSMMore on FSM--based Control Schemebased Control Scheme

v FSM + counter is preferred control structure for most problemsv FSM only depends on primary inputs, counter values, and

important (few) control registers.v Counter is used for regular data access and phase control.v Reduce state number hugely.

when counter==2’d2

set counter=2’d0 staten = state


P14

Partition the Partition the Problem Problem and and CoCo--Work Work with with Your PartnerYour Partner

vFor Non-FSM design:vDraw complete architecture: combinational circuits

could be drawn in a box.vFIFO is often used to delay and store datavInsert register to control its timing.vPlace register on equal-spaced points of datapath,

which may help timing reduction. (Don’t spend too much time on it.)


P15

Partition the Partition the Problem Problem and and CoCo--Work Work with with Your Partner (2)Your Partner (2)

v For FSM design:v Draw a complete FSM diagram and define counters.ØDon’t optimize at first. State-register is small, flexibility is

important. Write down all the values on the paper.v Coding purely on FSM state variables, counters, and control

signals controlled by FSM and counters.Ø state, staten; counter, countern… etc

v Trace state transition and control signals before you go to next step (datapath design).

v Use 3-always block coding style for FSMØRegister, next-state logic, output control logic

v Use easy-debugging coding style


P16

EasyEasy--Debugging Coding Style (1/2)Debugging Coding Style (1/2)v Signal naming with prefix & suffixv Utilize the prefix & suffix to show the attributes of signalsv signal_n: low-activev signal_w: wirev signal_r: register/flip-flopv next_signal: next-state signal of FSMv cur_signal: current-state signal of FSM

v Alphabetically naming for waveform debugging


P17

EasyEasy--Debugging Coding Style (2/2)Debugging Coding Style (2/2)vPure sequential block

always@(posedge clk) beginif(state==2’d0) begin

state <= 2’d1;endelse if(state==2’d1) begin

state <= 2’d2;endelse if(state==2’d2) begin

if(flag) state <= 2’d3;else state <= state;

endelse begin

state <= 2’d0;end

end

always@(*) beginif(state==2’d0) begin

next_state = 2’d1;endelse if(state==2’d1) begin

next_state = 2’d2;else if(state==2’d2) begin

if(flag) next_state = 2’d3;else next_state = state;

endelse begin

next_state = 2’d0;end

endalways@(posedge clk) begin

state <= next_state;end


P18

Partition the Partition the Problem Problem and and CoCo--Work Work with with Your Partner (3)Your Partner (3)

v It’s teamwork!v If both of you’re very experienced, working on 2 computer may

be more efficient.v But in most cases, 2 people on 1 computer is much better!

v Partition coding parts by different always blocks and continuous assignments of related signals.

v Time-saving technique: You should watch carefully when your partner is coding, and so does your partner.v Online debugging in different one’s head is much more

efficient than wave-form tracing.


P19

RTLRTL Coding and DebuggingCoding and Debuggingv Separate registers and transfer parts clearly.v Simple is best: v Do not use both edges of clock in logic circuit!! It is only used

for the inverse clock of memory.v Do not use clock as data!!!!v Result in serious synthesis problem and makes physical

design fail.

v Trace timing diagram and test data carefully. v Use +notimingchecks to eliminate unnecessary

timing check system tasks ($setup, $hold, $width…)v ncverilog testbench.v rtl.v +access+r +notimingchecks

v Read warning message generated by ncverilog.


P20

SynthesisSynthesis and and GateGate--Level SimulationLevel Simulationv Use nLint to help you refine your code.v Check environment setting is correct.v FileàSetup, check .synopsys_dc.setup successfully guides

design vision to load libraries.

v Check all constraints are successfully set (return 1 in console/dv log).v copy/paste from .sdc file, group-by-group.

v Use relaxed initial timing constraint. (e.g. 100ns)v Faster compile time! v Reduce timing constraint by a value slightly larger than slack.


P21

GateGate--Level Debugging (1/2)Level Debugging (1/2)vSDF annotationvMake sure SDF file existsvMake sure SDF file is parsed correctly when running

simulationvInput delay and output delayvSynthesis tool does not know when your inputs

come and when the outputs are capturedvNo input delay & output delay is default setting

Switch Logic

(0.9 cycle)

Computation(1 Cycle)

Switch Logic

(0.7 Cycle)

din

Error occurs!Also setup-time violation!


P22

GateGate--Level Debugging (2/2)Level Debugging (2/2)vSetup-time violationvInput of flip-flop not stable when clock triggersvCheck if there is …ØUnexpected long combinational delayØCombinational loopØImproper input delay

vHold-time violationvOutput of flip-flop is asked stable too earlyvIf caused by shift registers, it will be fixed at place &

route stage (backend stage)vOtherwise it should not happen at frontend stage


P23

TimeTime--Saving TricksSaving Tricksv Add extra $finish task to testbench for shorter

simulation time.v initial #(`CYCLE * `MAX_SIM_CYCLE ) $finish;v sometimes the testbench never finish if your output is incorrect!

v Prepare reusable coding constructsv always@() begin end …v for other combinational block, copy the used constructs from

the always block of FSM transition logic.always@(*) begin

case()…endcase

end


P24

TimeTime--Saving Saving Tricks (2)Tricks (2)v Define 1-bit longer state register than the required bit

number of your first FSM diagram.v Use parameter to define state name (capitals letters).

vWhen interfacing memories, do not use clock to generate a new clock.v If the memory requires a clock signal from your design, use

FSM + phase counter to generate waveform. It’s much more reliable and easy to control, and almost has no effects on synthesis and place-and-route.


P25

Case Study: 97Case Study: 97--PreliminaryPreliminaryv NAND Flash Memory Controller

Testbench


P26

ReadRead


P27

WriteWrite


P28

Write (2)Write (2)


P29

I/O Timing I/O Timing ((HostHostààFlashFlash Controller)Controller)


P30

Brief SummaryBrief SummaryvIt’s a FSM based design.vHalf handshake between host and controllerv Fully: controller response ready, host give control signalv Half: host send command right after controller being ready. No

host control signal.

vWrite(2) may takes a lot of time (both simulation time and design effort) to handle.


P31

Grading MethodGrading Method

v Grade by completenessv Easy parts and difficult partsv RTL is much more important (obstacle at level B~D)


P32

PinPin--Out Table &Out Table & Detailed Detailed TimingTiming


P33

Detailed Timing (2)Detailed Timing (2)

Multi-cycle controller is preferred to generate control signals


P34

System FunctionSystem Function


P35

Given Flow ChartGiven Flow Chart

FSM design idea:1. separate sequence for

(a), (b), and (c)2. detect for erasing case,

overlap on (a) and (b)

PreviousStates

3. add redundant states between computation for flexibility


P36

FSM DesignFSM Design


P37

FSM + Counter for Signal ControlFSM + Counter for Signal Control

Extra Tips: For tracing large design, create groups of signal to observeStore selected signals in resource file by nWaveà File à Save SignalRestore selected signals in resource file by nWaveà File à Restore Signal


P38

Test DataTest Data

Identify state transition sequence of command 1:0 à 25 à 1 à 2 à 3 à 12 à 13 à 14 à15 à 16 à 17 à 26 à 18 à19 à 1

Identify state transition sequence of command 2:1 à 2 à 4 à 5 à 6 à 7 à 8 à 9 à10 à 11 à 1

Non-overlapped pages


P39

Test Data (2)Test Data (2)

Identify state transition sequence of command 1:0 à 25 à 1 à 2 à 3 à 12 à 13 à 14 à15à 16 à….



P40


Identify state transition sequence of command 2:0 à 25 à 1 à 2 à 3 à 12 à 13 à 14 à15 à 16 à 17 à 26 à 18 à15 à 16 à 17 à 26 à 18à 19 à 1



P41


page: 0f3 à 0f4page: 0f0 à 0f1

page: 0f1à 0f2page: 018 à 018

Previous state

Read Flash (4pages)

Write Flash (4pages)

Read System memory & Update buffer

Done


P42

ResultResult

RTL ready takes around 10~11 hours (1 person)


P43

Bonus IC Contest of 972Bonus IC Contest of 972 DSDDSDvWe’ll choose a simpler problem for participants.v If there’re more than six teams, there will be awards.v 3K, 2K, 1K, 500-dollor coupon of book

Gravity Center Calculator (non-FSM) Triangle Rendering Engine (FSM)


P44

Final ProjectFinal Projectv Announce on 5/27v Present on 6/17, 6/22 (Mon.), 6/24 afternoon

Documents

Digital System Design IC Contest Cellll--based Designaccess.ee.ntu.edu.tw/course/dsd_97second/lecture/W15_IC_Contest_090527.pdfIC設計競賽簡介 v自86學年度開始舉辦，由教育