Dimtri_ESD_LNA2005

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1434 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005

A 5-GHz Fully Integrated ESD-Protected Low-NoiseAmplifier in 90-nm RF CMOS

Dimitri Linten , Student Member, IEEE , Steven Thijs, Mahadeva Iyer Natarajan , Senior Member, IEEE ,Piet Wambacq , Member, IEEE , Wutthinan Jeamsaksiri , Member, IEEE , Javier Ramos,

Abdelkarim Mercha , Member, IEEE , Snezana Jenei , Member, IEEE , Stéphane Donnay , Member, IEEE , andStefaan Decoutere

Abstract—A fully integrated 5-GHz low-power ESD-protectedlow-noise amplifier (LNA), designed and fabricated in a 90-nmRF CMOS technology, is presented. This 9.7-mW LNA features a13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, whilemaintaining an input return loss of 14 dB. An on-chip inductor,added as “plug-and-play,” i.e., without altering the original LNAdesign, is used as ESD protection for the RF pins to achieve suffi-cient ESD protection. The LNA has an ESD protection level up to1.4 A transmission line pulse (TLP) current, corresponding to 2-kV

Human Body Model (HBM) stress. Experimental results show thatonly minor RF performance degradation is observed by adding theinductor as a bi-directional ESD protection device to the referenceLNA.

Index Terms—CMOS, electrostatic discharges (ESD), low noiseamplifier, radio frequency.

I. INTRODUCTION

AVAILABILITY of high data rate wireless local area net-

works fuelled the rapid deployment of several emerging

applications for portable electronic devices. CMOS technology,

which has not been considered for commercial RF applications

until recently, is becoming a commercially viable manufac-

turing option. For example, with the 90-nm CMOS technology

node, transit frequencies well over 100 GHz are achieved [1].

This offers a comfortable frequency margin for RF designers.

Recently, the design of a 5-GHz low-noise amplifier (LNA) and

voltage-controlled oscillator (VCO) [3], [4] have validated this

technology node for low-voltage low-power high-performance

RF front-ends. However, downscaling places severe restrictions

on analog design, such as low supply voltage resulting in

reduced voltage headroom.

With the decrease of gate oxide thickness, CMOS circuits

become more sensitive to stress from electrostatic discharge

Manuscript received November 12, 2004; revised January 27, 2005. Thiswork was supported in part by the European Union in the framework of theIST-2000-30016 IMPACT Project and the Flemish IWT.

D. Linten is with the DESICS/WL, IMEC, 3001 Leuven, Belgium. He is alsowith the Vrije Universiteit Brussel (VUB), Department ELEC-ETRO, Brussels,Belgium, and the IWT (e-mail: [email protected]).

S. Thijs was with IMEC, 3001 Leuven, Belgium. He is now with Sarnoff Europe, 9880 Aalter, Belgium.

M. I. Natarajan, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Donnay, and S.Decoutere are with IMEC, 3001 Leuven, Belgium.

P. Wambacq is with IMEC, 3001 Leuven, Belgium. He is also with the VrijeUniversiteit Brussel (VUB), Brussels, Belgium.

S. Jenei was with IMEC, 3001 Leuven, Belgium. She is now with AmericanSemiconductors, Vilvoorde, Belgium.

Digital Object Identifier 10.1109/JSSC.2005.847490

(ESD). For example, in RF systems, the LNA, one of the most

critical building blocks in any RF front-end, is usually con-

nected to the outside world through the antenna or an off-chip

antenna filter and can therefore be exposed to ESD stress

events. Incorporating sufficient level of on-chip ESD protection

on a given circuit requires that the added ESD protection

does not degrade the performance parameters of the circuit.

Consequently, simultaneously achieving the RF performanceand ESD robustness in state-of-the-art CMOS technologies is

highly challenging.

In digital circuits, ESD protection circuits commonly consist

of large clamping devices, e.g., diodes or grounded gate nMOS

structures, often with a current limiting series resistor, and are

added as “plug-and-play” devices. However, in RF LNA design,

such devices, sized to achieve the desired ESD protection level,

present a big parasitic input capacitance (e.g., 500 fF for a 2-kV

HBM stress). These devices cannot be “plugged” into the LNA

design without seriously affecting the amplifier performance:

the extra capacitance at the RF input pin will degrade the input

matching constraint, and the limiting resistor, if used, will dras-

tically increase the LNA’s noise figure.ESD-RF co-design techniques take the ESD protection struc-

tures into the LNA design space [5], [8]. Recently, a number of

articles [6]–[9] highlighted the use of inductors to shunt the ESD

current from the core circuit, without disturbing the RF signal

propagation, realized in 0.35, 0.25, and 0.18 m CMOS tech-

nologies.

In the work presented in this paper, an inductor is added as

a “plug-and-play” ESD protection structure, i.e., without al-

tering anything to the original LNA design as preferred by any

RF designer. The fully integrated 5-GHz CMOS LNA fabri-

cated in IMEC 90-nm RF CMOS technology, drawing 8.1 mA

from a 1.2-V supply, achieves a power gain of 13.3 dB and anoise figure of 2.9 dB, while maintaining an input return loss

of 14 dB. The input 1-dB compression point is 11.5 dBm,

the third-order input referred intercept point (IIP3) is 2.7 dBm,

both at 5.5 GHz. This LNA is protected against ESD up to 1.4 A

transmission line pulse (TLP) current [10], which corresponds

to 2-kV HBM stress.

This paper is structured as follows. The 90-nm RF CMOS

technology used is briefly described in Section II. The LNA ar-

chitecture, circuit design aspects, and ESD protection are dis-

cussed in section in Section III. Section IV describes the mea-

surement results of the LNA with and without ESD protec-

tion. Finally, Section V compares the measurement results with

0018-9200/$20.00 © 2005 IEEE



LINTEN et al.: A 5-GHz FULLY INTEGRATED ESD-PROTECTED LOW-NOISE AMPLIFIER IN 90-nm RF CMOS 1435

Fig. 1. Common source LNA with inductive source degeneration, with added

ESD protection within dotted boxes.

state-of-the-art fully integrated LNA designs in the open litera-

ture.

II. 90-nm RF CMOS TECHNOLOGY

The LNAs have been fabricated in IMEC’s 90-nm RF CMOS

process on p-type 20 cm Si substrate with a five-level standard

copper interconnect structure. Passive components including

high-quality MIM capacitors and inductors are available in this

process. The minimum physical gate length of the MOSFETs

can be as low as 70 nm with an effective oxide thickness of

1.5 nm, a polysilicon gate electrode and a threshold voltage

( ) of 0.3 V for the nMOS transistor ( 0.3-V PMOS). The

maximum supply voltage is 1.2 V. The nMOS transistor can

achieve a value for , , and , of 1250 mS/mm,

200 GHz, and 150 GHz, respectively [3]. To design the LNA

in this technology, MOS Model 11 parameters [11] have been

used.

III. “PLUG-AND-PLAY” INDUCTOR ESD PROTECTION

IN RF CMOS LNA DESIGN

The LNA circuit (see Fig. 1) employs a common source

topology (transistor ) with a cascode transistor , it ismatched to 50 at both input and output. The power-con-

strained noise optimization technique by Shaeffer et al. [12],

including the impact of the non-quasi-static input resistance

[13], has been used to get an initial estimation of the aspect

ratio and overdrive voltage of .

A 50- input impedance matching is achieved using source

degeneration inductor, [12]. Inductor is used to tune out

the remaining capacitive impedance at the gate of . The MIM

capacitor isused to ac-couple the RFsignal ontothe LNA. A

capacitive impedance divider consisting of MIM capacitors

and achieves the output matching. It adds the exact amount

of capacitance to resonate with the load inductor at the

center frequency and to transform the impedance level at thedrain of to 50 .

A measure for the level of ESD protection is the Human Body

Model (HBM) [14] test pass voltage. The HBM test consists

of a charged capacitance of 100 pF that is discharged through

a 1.5- resistor, connected to the device under test (DUT),

resulting in a 150-ns double-exponential pulse. The standard

level of ESD protection is 2 kV and refers to the ability of the

on-chip ESD protection to conduct 1.34 A during an ESD event( 150 ns for HBM pulse) away from the sensitive core circuit,

and to limit the voltage of the protected node to a safe level.

The HBM component level test method is used for qualifica-

tion of parts, meaning that the results show only a “pass” or a

“fail” and do not provide any detailed information on the ESD

protection network behavior. TLP testing is traditionally used to

characterize the on-chip ESD protection structures and evolved

as one of the most useful tools to reduce the ESD protection de-

sign cycle time. A TLP tester employs a rectangular pulse with

energy ranges similar to those used in HBM ESD qualification

testing. This allows for correlation between TLP (with rectan-

gular pulse widths of 75–200 ns) and HBM [14]. In this paper,

TLP tests are performed and the results are correlated to equiv-alent HBM test qualification level.

The HBM ESD pulse frequency spectrum is limited to

GHz. Therefore, it can be split from the RF signal

GHz at the RF pins by providing a low-impedance

pad toward the ground at frequencies less than 1 GHz. This

can be achieved by inserting suitable inductors at both

input and output of the LNA to sink the stress current at the RF

pins away from the LNA core to the power lines; see Fig. 1.

Tradeoffs in inductor selection from an RF and ESD point of

view are discussed in the next sections.

A. RF OperationConsider the input stage of the LNA in Fig. 2. The inductor

tunes out all parasitic capacitances (pad capacitance

, line parasitics , and bottom plate capacitance of )

at the operating frequency of the LNA. At resonance, the

only remaining parasitic is the equivalent parallel resistance,

of the inductor

(1)

where is its parasitic series resistance. comes in

parallel with the 50- input impedance of the LNAin Fig. 2. If

(2)

does not disturb the input matching condition of the

original LNA design. Condition (2), independent of the core

LNA design, is usually fulfilled since is in the order

of in state-of-the-art RF CMOS technologies, where high-

quality inductors at 5 GHz with large inductance values can be

realized. If (2) is fulfilled, then the input matching is not affected

by the presence of the added ESD inductor and consequently, the

power gain as well as linearity remains practically unaffected.

The introduction of the parallel resonance at the input of theLNA, equivalent to a first-order LC bandpass filter, can reduce




Fig. 2. Top: input matching network of the LNA withL

as added ESDprotection device; bottom: equivalent scheme at the RF operating frequency

!

.

the input bandwidth of the LNA when its quality factor is higher

than the input quality factor of the LNA.

The presence of increases the noise factor ofthe LNA

with a term :

(3)

Since condition (2) is valid, this increase is negligibly small.Similar approaches have been published in 0.18 m CMOS

[8]. However in this reference, off-chip components and an

on-chip ESD inductor are integrated in the matching network.

The ESD inductor together with the decoupling capacitor is

placed at the gate of (after the bond wire inductor ). As

a result the noise figure increases with a term :

(4)

Expression (4) reveals that the protection strategy of [8]

cannot be used as a plug-and-play solution since the increase

of noise depends on the LNA design itself through the value of

.

B. ESD Operation

The gate oxide of transistor is the weakest spot of the cir-

cuit during ESD stress at the input. Consider an ESD event oc-

curring between the RF input pin ( in Fig. 1) and ground.

The simulated HBM current is seen in Fig. 3. Its fast rising

edge causes a voltage overshoot across the inductor,

in Fig. 3, as the current through it cannot be changed instanta-

neously. The ESD robustness of the inductor is characterized by

measuring it in standalone configuration using a 50- TLP mea-

surement system. The inductor, e.g., 3-nH inductor, can with-stand a current of 4.7 A prior to failure with 33 V across it. After

Fig. 3. 2-kV HBM simulations of the inductor protected LNA, stressed fromthe RF input pin

( R F )

to the ground. The HBM current trough the inductorcauses a voltage overshoot on the RF input node ( R F ) . The capacitor C

couples this overshoot on the gate of M ( V ( M ) )

, which can damage thegate oxide of

M

.

Fig. 4. Measured absolute value of leakage currents of the gate oxide of theRF transistor for positive and negative voltage stress conditions.

the overshoot, the voltage across the inductor is determined by

its on-resistance. Therefore, an inductor with a small on-resis-

tance is preferable to reduce the voltage drop across its terminals

as much as possible since this voltage could possibly damage the

thin gate oxide (1.5 nm) of transistor . The MIM capacitor

(Fig. 2, top) couples the transient voltage onto the gate of

transistor , as a capacitive divider, in Fig. 3.

Ergo, one must determine the maximum allowed voltage atthe gate of during a positive and a negative ESD event. TLP

measurements are performed on a standalone RF transistor that

is identical to of the LNA. Its gate is stressed with source,

bulk, and drain grounded. The breakdown voltage is defined as

the TLP voltage level at which the gate leakage current increases

(because of oxide failure). The measured positive and negative

breakdown voltage of the 1.5-nm oxide during a 100-ns pulse

are 4.1 V and 5.1 V, respectively (seen in Fig. 4). This asym-

metry can be explained as follows: during negative ESD events,

will be driven in its accumulation regime, where the nega-

tive voltage spreads over both the oxide and the accumulation

region. The latter does not take part during the positive stress,

and therefore the transistor can take a larger negative voltagebefore damaging the gate oxide.




C. Selecting

From the ESD standpoint, the voltage overshoot at the gate of

needs to be minimized up to a value below the breakdown

voltage of the gate oxide. HBM simulations are needed to select

the proper ESD inductor . On the other hand, from the RF

standpoint, should be kept as low as possible in order not

to degrade the noise figure of the LNA, thereby fulfilling theinput matching condition.

Based on this RF and ESD analysis, a proper can be se-

lected from the available inductor library (Fig. 5). The minimum

is determined from the requirement of 10 dB input re-

flection of the LNA [Fig. 5(a)]. The 2-kV HBM simulation for

a 3-nH inductor, input stressed with respect to ground, yields

almost 4 V across the gate of which is close to the oxide

breakdown voltage. Since this is only a simulation result, the

real voltage at the gate could differ and be even a bit higher,

e.g., due to an additional parasitic resistance to connect .

Moreover, taking statistics into account, and to make sure that

99.9% of all oxides are not degraded, the maximum allowed

voltage should be lowered to 3.8 V according to Weibull sta-

tistics. This voltage has been calculated based on [15] with a

Weibull slope of 1.5 and a voltage acceleration factor of

6 decades/V. Finally, the 3-nH inductor has been chosen as the

ESD protection inductor at both input and output because of its

lower dB [Fig. 5(c)]. The maximum voltage over the

gate of [Fig. 5(b)] is close to the above-determined voltage

of 4.1 V, which is a little bit higher than the voltage determined

by Weibull statistics (3.8 V).

To protect the supply pin from both positive and negative

ESD pulses versus the supply pin, a grounded gate nMOS device

(ggNMOS), in Fig. 1, is used as a power clamp. The

ggNMOS can be sized as big as desired because no RF signalis present at this pin, and hence its parasitic capacitance is of no

importance.

IV. EXPERIMENTAL RESULTS

In order to validate the plug-and-play inductive ESD-protec-

tion approach discussed above, the LNA has been fabricated

with and without the ESD protection. In the next sections, the

layout, as well as RF and ESD experimental results, are dis-

cussed.

A. Layout

Fig. 6 shows the micrograph of both LNAs. The circuit area of

the reference LNA (without ESD protection) is m ,

compared to m with the ESD protection, both

including the bondpads. Both the input nMOS and cascode

nMOS have an aspect ratio of m nm. The multifin-

gered transistors have their gates contactedon both sides in order

to reduce the noise contribution from the gate resistance. All in-

ductors are implemented on-chip with a grounded patternedpoly

shield. The windings of the inductor are made in the two highest

metal layers with via shunts. In this way, a metal thickness of

approximately 1.3 m is obtained. The inductors used are 0.4 nH

for , 4.3 nHfor , and 1.1nH asloadinductor;the measured

quality factors at 5 GHz are 8.8, 7, and 7.8, respectively. TheESD inductors at input and output nodes have an inductance

Fig. 5. RF–ESD tradeoff on the selection of L

; under the condition of

(a) j S 1 1 j < 0 1 0 dB), (b) maximum voltage on the gate of M before oxidefailure determines the ESD limit and (c) the maximum noise figure of the LNAdetermines the RF limit.

valueof 3 nH, witha of6.5at 5 GHz.On-chipMIMcapacitors

serve as supply decoupling.

B. RF Measurement Results

On-wafer measurements have been performed on the LNAs.Both circuits draw 8.1 mA from a 1.2-V supply voltage. The




Fig. 6. Micrographs of the fully integrated LNA without ESD protection (left), and with “plug-and-play” inductive ESD protection (right).

TABLE ISTATE-OF-THE-ART OF FULLY INTEGRATED LNAS AND PERFORMANCE SUMMARY

measurements, summarized in Table I, clearly shows that adding

the inductor as a plug-and-play bi-directional ESD protecting

device does not disturb the RF performance.

The bandwidth of the LNA is practically unaffected by the

ESD protection, since the Q of inductor is lower than the

of (Fig. 7). Further, the measured input reflection

at 5.5 GHz of the ESD-protected LNA and the reference LNA

are 14.2 dB and 10.3 dB, respectively (Fig. 8). A slight in-

crease in frequency is observed in both curves. This is dueto an inaccurate initial model of the source degeneration in-

ductor, which was proven with updated model of the inductor

. However, still a good input matching is obtained over the

entire operation 3-dB bandwidth of the ESD LNA. The better

input matching behavior (S11) of the ESD-protected LNA re-

sults in a slightly higher power gain (S21), as stated above. An

output reflection below 4 dB is obtained over the entire 3-dB

bandwidth of both LNAs (Fig. 8).

The noise figure of the ESD-protected LNA at 5.5 GHz is

2.95 dB, as shown in Fig. 9. The minimum noise figureof 2.9 dB

occurs at 5.2 GHz. The major contributor to this noise figure is

the series loss of the integrated inductor (the LNA’s simu-

lated noise figure drops with 1 dB when the noise contribution of is removed). The noise figure increases with about 0.25 dB

Fig. 7. Measured power gain( S )

of the ESD-protected LNA and the

reference LNA.

when adding the ESD inductor at the input, as expected from

the simulation data in Fig. 5(c).

C. ESD Measurement Results

The input pin was protected using , a 3-nH inductor,which alone could withstand a current of 4.7 A with 33 V across




Fig. 8. Measured inputand output reflection (S

andS

, respectively) of the

ESD-protected LNA and the reference LNA.

Fig. 9. Measured 50-

noise figure of the ESD-protected LNA and thereference LNA.

it (50- TLP measurement). For comparison, TLP measure-

ments were performed on the full circuit, where ESD stress was

applied positive on the input pad with respect to ground. The

full circuit could withstand at its input 1.46-A TLP stress be-

fore failure. During this stress, 11 V develops across the ESD

inductor, as can be seen in Fig. 10. This figure shows the mea-

sured voltage waveform using a 50- TDR TLP system, where

part of the incident and reflected waveforms of the TLP pulse

overlap in the measurement setup, these overshoots do not stress

the ESD-protected LNA. At the input node a voltage of

11 V during the TLP pulse is measured, as predicted by simula-

tion data in Fig. 3.

During ESD testing, a quick method is needed to detect

failure. Since the inductor only has a few ohms of resistance to

ground, leakage at the input node cannot be used as criterion.

Therefore, another criterion is needed. If during monitoring

of the leakage at the node (in case this node is present

in the design) the bias resistor R is measured, most likely the

gate oxide of has failed. Without failure, an open circuit

should be seen here. Another possible criterion is to use the

leakage at the node. During positive bias at this node,

transistor goes into strong inversion, such that any damageat transistor can be monitored. This is much more sensitive

Fig. 10. Measured voltage during a 100-ns TLP stress of 1.46 A between theRF input pin

( R F )

and ground.

than monitoring at , because now there is not a large

resistor in series with the leakage path.

The power pin is protected by a grounded gate nMOS(ggNMOS in Fig. 1). The ggNMOS has a width of 100 m and a

gate length of 0.25 m. These power clamps can withstand up to

1.6-A TLP, corresponding to 2.5-kV HBM. The voltage devel-

oped at this current is about 7 V. When stressing the ggNMOS

with a negative polarity, the current is conducted mainly by the

P substrate/N+ drain diode and more than 4–A TLP could be

reached.

V. STATE-OF-THE-ART COMPARISON

To compare the performance of our LNA to other designs, dif-

ferent figures of merit (FOM) that are common in literature, are

used. The performance summary of the LNA, and a comparison

with other fully integrated CMOS LNAs operating in the 5-GHz

band, is shown in Table I. The FOMs do not include the ESD

performance. However, to the authors’ knowledge, this work is

the first published fully integrated 5-GHz LNA with ESD pro-

tection.

A first figure of merit (FOM1) for low-power RF amplifiers

is the ratio of the gain in dB to the dc power consumption in

milliwatts. The LNA described in this paper has a value of 1.38

for this FOM. This high value is achieved due to the use of

90-nm CMOS technology. Further, this FOM can be extended

to include the noise figure of the LNA as follows:

(5)

Brederlow et al. [17] proposed a FOM that also includes IIP3

and operating frequency as follows:

(6)

From Table I, it is clear that the FOMs of the CMOS LNA de-

sign described in this paper are among the best reported values

of fully integrated 5-GHz band LNAs. Only Chiu et al. [18] re-ported a higher FOM2 value. Their remarkably low noise figure




of 2.17 dB was reached by applying a nonstandard wafer thin-

ning technique. The LNA reported by Linten et al. [4] was opti-

mized for low-power low-voltage operation, resulting in a high

FOM1 and FOM2.

VI. CONCLUSION

A functional fully integrated 5.5-GHz low-power LNA with

ESD protection has been designed and fabricated in 90-nm

RF CMOS technology. This state-of-the-art LNA features a

power consumption of 9.7 mW and a 13.3-dB power gain with

a noise figure of 2.9 dB, while maintaining an input return loss

of 14 dB. The 3-dB bandwidth is 1.35 GHz (641-MHz 1-dB

bandwidth). The input 1-dB compression point at 5.5 GHz is

11.5 dBm, and the IIP3 is 3 dBm.

An integrated inductor has been used as a “plug-and-play”

bi-directional ESD protecting device, i.e., without altering any-

thing to the original core LNA design, as preferred by any RF

designer. No significant degradation of the core LNA RF per-formance is observed. This LNA is protected against ESD up to

1.4-A TLP current, corresponding to 2-kV HBM stress.

The use of 90-nm CMOS has been found suitable for

low-power high-performance RF design around 5 GHz. The

measurement results demonstrate that low noise figures and

low power consumption can be achieved simultaneously with

on-chip input and output matching networks and ESD protec-

tion.

ACKNOWLEDGMENT

The authors wish to thank the EU IMPACT IST-2000-30016

Project and the Institute for the Promotion of Innovation

through Science and Technology in Flanders (IWT-Vlaan-

deren) for their support, the IMEC PLINE for processing of the

wafers, A. Scholten from Philips Eindhoven for MOS Model 11

parameter extraction, L. Pauwels for measurement assistance,

J. Mees for all the design environment support, B. Kaczer,

V. Vassilev, T. Daenen, R. Degraeve, and G. Groeseneken for

their input on ESD reliability issues, and G. Van der Plas for

proofreading the manuscript.

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[16] S. Thijs, M. I. Natarajan, D. Linten, V. Vassilev, T. Daenen, A. Scholten,R. Degraeve, P. Wambacq, and G. Groeseneken, “ESD protection for

a 5.5 GHz LNA in 90 nm RF CMOS—implementation concepts, con-straints and solutions,” in Proc. EOS/ESD Symp., Sep. 2004, pp. 40–49.

[17] R. Brederlow, W. Weber, J. Sauerer, S. Donnay, P. Wambacq, and M.Vertregt, “A mixed signal design roadmap,” IEEE Design Test Comput.,vol. 18, no. 6, pp. 34–46, Nov.–Dec. 2001.

[18] H. W. Chiu and S. S. Lu, “A 2.17 dB NF, 5 GHz band monolithic CMOSLNA with 10 mW DC power consumption,” in IEEE Symp. VLSI Cir-

cuits Dig. Tech. Papers, Jun. 2002, pp. 226–229.[19] E. H. Westerwick, “A 5 GHz band low noise amplifier with a 2.5 dB

noise figure,” in Proc. IEEE Int. Symp. VLSI Technology, Systems, and

Application, Apr. 2001, pp. 224–227.[20] D. Mukherjee, J. Bhattacharjee, S. Chakaraborty, and J. Laskar, “A 5–6

GHz fully integrated CMOS LNA for a dual-band WLAN receiver,” inProc. IEEE RAWCON , Sep. 2002, pp. 213–215.

[21] T. K. K. Tsang and M. El-Gamal, “Gain and frequency controllablesub-1 V 5.8 GHz CMOS LNA,” in Proc. ISCAS, vol. 4, May 2002, pp.795–798.

[22] D. Linten, X. Sun, G. Carchon, W. Jeamsaksiri, A. Mercha, J. Ramos,S. Jenei, L. Aspemyr, A. J. Scholten, P. Wambacq, S. Decoutere, S.Donnay, and W. De Raedt, “A 328 W 5 GHz voltage-controlled os-cillator in 90 nm CMOS with high-quality thin-film post-processed in-ductor,” in Proc. IEEE Custom Integrated Circuits Conf., Oct. 2004, pp.

701–704.

Dimitri Linten (S’01) was born in Vilvoorde, Bel-gium, in 1978. He received the Masters degree as anElectrical Engineer in Electronics and InformationProcessing in 2001 at the Vrije Universiteit Brussel(VUB), Brussels, Belgium. In August 2001, he

joined the Department ELEC as a Research Assis-tant working toward the Ph.D. degree. His residenceis at the Wireless Research group of IMEC, Leuven,Belgium.

His research interests are CMOS, BiCMOS, andnew emerging technologies for low-power RF designand electrostatic discharge (ESD) reliability.




Steven Thijs received the M.Sc. degree in elec-trotechnical engineering option electronics, autom-atization and computer systems in 2001 from theKatholieke Universiteit Leuven (KUL), Belgium.

He joined the Silicon Processing and DeviceTechnology group of IMEC, Leuven, Belgium, in2001, where he was involved in ESD protectiondesign, layout, simulation and characterization

on CMOS and BiCMOS technologies and in RFcircuit design with ESD protection. In March 2005,he joined Sarnoff Europe, Gistel, Belgium, as a

Member of the Technical Staff.

Mahadeva Iyer Natarajan (M’94–SM’00) received

the B.Sc degree in physics in 1985, and the M.Sc.and Ph.D. degrees in solid state physics from KeralaUniversity, India, in 1987 and 1994, respectively.

From 1994 to 2000, he worked as a Member of Technical Staff at Institute of Microelectronics, Sin-gapore, and has been involved in the ESD/latch-upresearch, IC failure analysis, and various failureanalysis techniques. Since March 2000, he has been

working in the High Voltage and Reliability groupof IMEC, Leuven, Belgium, as the Section Head for

the ESD research activities. His research interests are ESD engineering, device

failure physics and analysis. He has published more than 45 papers in ICFA,ESD and analytical techniques, and conducted a number of workshops/trainingsessions on ESD, device reliability and analytical techniques.

Dr. Natarajan is serving as a member of the technical program committees of the EOS/ESD Symposium ’01–’05, IEEE IRPS ’02–’05, IEEE IPFAS ’00–’05and MRS-ICMAT’03 and ’05.

Piet Wambacq (S’89–M’91) was born in Asse, Bel-gium, in 1963. He received the M.Sc. degree in elec-

trical and mechanical engineering and the Ph.D. de-

gree from the Katholieke Universiteit Leuven, Bel-gium, in 1986 and 1996, respectively.

From 1986 to 1996, he was a Research Assistantat the ESAT-MICAS Laboratory, Katholieke Univer-siteit Leuven. Since 1996, he has been with IMEC,Heverlee, Belgium, working as a Principal Scientiston design methodologiesfor mixed-signal and RF in-tegrated circuits. He is a Lecturer at the University of

Brussels (Vrije Universiteit Brussel). He has authored or coauthored two booksand more than 100 papers in edited books, international journals, and confer-ence proceedings. He is the co-inventor of two patents. His research interestsare design and CAD of mixed-signal and RF integrated circuits.

Dr. Wambacq is an associate editor of the IEEE TRANSACTIONS ON CIRCUITS

AND SYSTEMS, PART I. He is the co-recipient of the Best Paper Award at theDesign, Automation and Test Conference (DATE) in 2002 and 2005. He regu-

larly is a member of the Program Committees of international conferences (e.g.,DATE).

Wutthinan Jeamsaksiri was born in Thailand. Hereceivedthe M.Eng.and Ph.D. degrees fromthe Elec-trical and Electronic Engineering Department, Impe-rial College, London,U.K.,in 1996and 2002, respec-tively.

From 1996 to 1997, he was with AndersenConsulting, Thailand (now Accenture) as an In-formation Technology Analyst. Since 2001, he hasbeen working with the Silicon Process and Device

Technology Division of IMEC, Leuven, Belgium,as an R&D Engineer. His research interests include

digital, high frequency test structure design and characterization, Si process

and device architecture research and development, and RF CMOS. He isactively involved in device and process integration of 90-nm node CMOS forRF applications, in the framework of the European project (IMPACT).

Javier Ramos was born in Irun, Spain. He receivedthe B.S. degree in electronics engineering from theUniversity of the Basque Country, Spain, in 1999 andthe M.S. degree in control and systems engineeringfrom the University of Navarra, Spain, in 2002.

In September 2002, he joined the Silicon Processand Device Technology Division of IMEC as anR&D Engineer within the CMOS Device Research

department where he has been mainly involved inthe process integration and device characterizationof advanced CMOS technologies operating well

into the RF range in the frame of the European funded project (IMPACT).His research interests are CMOS device physics as well as high frequencycharacterization and modeling on RFCMOS devices and circuits.

Abdelkarim Mercha (M’03) was born in MaaderTiznit, Morocco. He received the M.Sc. degree incondensed matter physics from University of LeMans, France, in 1994, the M.Sc. degree in electricalengineering from the Ecole Nationale Supérieured’Ingénieurs de Caen (ENSI de Caen), France, in1997, the Certificate of business Management fromthe Institut d’administration des enterprises (IAE)in 1997 and the Ph.D. degree in microelectronics

from the University of Caen in December 2000. Hisdissertation was on the transport and low-frequency

fluctuations mechanisms in polycrystalline silicon thin-film transistors (poly-SiTFTs).

In 2001, he joined IMEC, Belgium. He was initially involved in a Europeanproject for the European Spatial Agency (ESA) on radiation effects study of

components operated at cryogenic temperature and future generations semi-conductor devices. He is currently leading the Analog/RF CMOS activities inthe Mixed Signal Technology Integration group. His interests cover the fieldof device physics and analog/RF characterization with particular emphasis onthe study of low-frequency noise in advanced devices. In these fields, he has

authored or co-authored over 80 journal and conference papers and one book chapter.

Snezana Jenei was born in Novi Sad, Vojvodina,Serbia, Yugoslavia. She received the M.S. degree inelectrical engineering from the University of NoviSad, Novi Sad, Yugoslavia, in 1991 with the Masterthesis in digital data transmission systems.

From 1991 to 1997, she was with the Departmentof Electrical Engineering, University of Novi Sad,where she was involved in research on inductivecomponents in thick film hybrid technologies andpublished a number of papers on the subject. From

1998 to 2003, she was with IMEC, Belgium, whereshe received the Ph.D. degree in electrical engineering and worked in the MixedSignal Technology Integration group on analysis, characterization, modeling

and optimization of RF passive integrated components. Currently she is withAMIS (American Semiconductors), Vilvoorde, Belgium, working on new CADmethodologies.




Stéphane Donnay (M’00) received the M.S. andPh.D. degrees in electrical engineering from theKatholieke Universiteit Leuven (K.U.Leuven),Belgium, in 1990 and 1998, respectively.

He was a Research Assistant in the ESAT-MICASLaboratory of the K.U.Leuven from 1990 to 1996,where he worked in the field of analog and RFmodeling and design automation. In 1997, he joined

IMEC, Belgium, where he is now Program Director.His current research interests include: circuit andsystem design in very deep-submicron technologies,

ultra-low-power radios for sensor networks, system-in-a-package integrationof RF front-ends and the modeling and simulation of substrate noise coupling

in mixed-signal ICs. He has authored or co-authored more than 100 papers inbooks, journals and conference proceedings. He is co-editor of Substrate Noise

Coupling in Mixed-Signal ASICs (Boston, MA: Kluwer Academic Publishers,2003).

Dr. Donnay has been a member of the Technical Program Committee of the European Solid-State Circuits Conference (ESSCIRC) since 2001. Hewas co-recipient of the Best Paper Award at the Design, Automation and Test(DATE) Conference in 2002.

Stefaan Decoutere was born in Kortrijk, Belgium,in 1963. He received the electronic engineeringdegree in 1986 and the Ph.D. degree in 1992 fromthe Katholieke Universiteit Leuven (K.U. Leuven),Belgium. His dissertation concerned two-dimen-sional effects in advanced bipolar transistors.

He joined the Interuniversity Micro-ElectronicsCenter (IMEC), Belgium, in 1987, where he was ac-

tive in high-voltage BCD technology development.From 1992 to 1997, he was in charge of the develop-ment of high-speed BiCMOS technologies and SiGe

HBT technologies. Since 1998, he has been the Head of the Mixed-Signal/RFtechnology group at IMEC. His main interests are in analog and RF CMOS andSiGeC HBT technology, and integrated passives for wireless applications. Inthis field he has authored or co-authored more than 100 international conferenceand journal publications.

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