Ee105 Fet Lect

7/29/2019 Ee105 Fet Lect

1/61

Chapter 7Field Effect Transistors

7/29/2019 Ee105 Fet Lect

2/61

Field Effect Transistors (FETs)OBJECTIVES:

describe the construction and basic operation of FETs

identify FET schematic symbols.

understand JFET parameters.

explain the information carried in FET data sheets.

identify the different FET DC bias circuits. determine the DC operating point of FET DC bias circuits.

identify the characteristics that FET amplifiers have in common withBJT amplifiers.

Explain the operation and characteristics of metal oxide

semiconductor field effect transistors (MOSFET) identify the different MOSFET DC bias circuits.

explain the advantages and disadvantages of FET amplifierscompared to BJT amplifiers.

apply troubleshooting principles to FET amplifiers.

7/29/2019 Ee105 Fet Lect

3/61

Introduction

1. Field effect transistors control current byvoltage applied to the gate.

2. The FETs major advantage over the BJT ishigh input resistance.

3. Overall, the purpose of the FET is the same asthat of the BJT.

7/29/2019 Ee105 Fet Lect

4/61

BJT vs JFET

BipolarJunctionTransistor

Current-based device

IBase controls ICollectorEmitter

JunctionFieldEffectTransistor

Voltage controlled device

VGate controls ISourceDrain

7/29/2019 Ee105 Fet Lect

5/61

The JFET Primary Characteristics

Junction field effect transistor controls current flow.

The JFET uses voltage to control the current flow.

You will recall, the transistor uses current flow through thebase-emitter junction to control current.

JFETs can be used as an amplifier just like the BJT.

VGGvoltage level controls current flow in the VDD, RDcircuit.

7/29/2019 Ee105 Fet Lect

6/61

The JFET - Labels

The terminals of a JFET are the source, gate, and drain.

A JFET can be either p channel or n channel.

7/29/2019 Ee105 Fet Lect

7/61

The JFET - Biasing

The source-drain current iscontrolled by a voltage field at thegate.

That field is developed by thereverse biased gate-source junction

(gate is connected to both sides). With more VGG(reverse bias) the

field grows larger.

This field or resistance limits the

amount of current flow through RD. With low or no VGG current flow

is at maximum.

7/29/2019 Ee105 Fet Lect

8/61

The JFET Current Control

(a) Mid-Bias for moderatecurrent flow

(b) Max-Bias for Pinch-off (nocurrent flow)

(c) Low-Bias for maximumcurrent flow

7/29/2019 Ee105 Fet Lect

9/61

JFET Characteristics and Parameters Ohmic

Lets first take a look at the effects with a VGSof 0V. ID increasesproportionally with increases ofVDD(VDSincreases as VDDisincreased). This is called the ohmic region (point A to B).

7/29/2019 Ee105 Fet Lect

10/61

JFET Characteristics and Parameters Pinch-Off

The point when ID ceases to increase regardless ofVDD increases

(constant current source) is called the pinch-off voltage (point B)

(Note: VGS = 0).

This current is called maximum drain current (IDSS).Breakdown(point C) is reached when too much voltage is applied. This isundesirable, so JFETs operation is always well below this value.

7/29/2019 Ee105 Fet Lect

11/61

JFET Characteristics and Parameters Drain CurvesFrom this set of curves you can see increased negative voltageapplied to the gate (-VGS) produces no change in ID. IDis limited

and the pinch-offvoltage (VP) is reduced. Note: VGS controls IDSSThis is the normal work zone for a JFET

7/29/2019 Ee105 Fet Lect

12/61

JFET Characteristics and Parameters Cutoff

We know that as VGS is increased IDwill decrease. The point that ID

ceases to increase is called cutoff. The amount ofVGS

required to do

this is called the cutoff voltage (VP). The field (in white) grows such

that it allows practically no current to flow through.

It is interesting to note that pinch-off voltage (VGS(off)) and cutoff

voltage (VP

) are the same value but opposite polarity.

7/29/2019 Ee105 Fet Lect

13/61

Pinch-OffVpvs CutoffVGS(off)

VGS(off) and VP are always = and opposite is sign

VP(inch off) - the value of VDS where ID becomes constantwith VGS = 0.

VP(inch off)alsooccurs for VDS

7/29/2019 Ee105 Fet Lect

14/61

Example

Vp = 4 V

VDS = 4 VID = I DSS =12 mA

VDD = V RD + VDS = (ID*RD) + VDS = 6.72 + 4 = 10.72 V

For the JFET below, VGSS (off) = - 4 V & IDSS =

12 mA. Determine the minimum value of VDD

required to put the device in the constant area

of operation. Given RD = 560

7/29/2019 Ee105 Fet Lect

15/61

JFET Characteristics and Parameters

The transfer characteristic curveillustrates the control VGShas on

IDfrom cutoff (VGS(off)) to pinch-off (VP). Note the parabolic shape. Theformula below can be used to determine drain current.

ID= IDSS(1 - VGS/VGS(off))2 Note:(VGS= 0 to VGS(off)controlsID)

Square-law device: Parabolic curve of the JFET Transfer Characteristic Curve.See Datasheet, for FET, in text pg.339

VGS(OFF)

Vp

7/29/2019 Ee105 Fet Lect

16/61

Example

The partial datasheet for a 2N5459 JFET indicates that typically IDSS = 9 mA& VGS(off) = - 8 V maximum. Using these value, determine the drain current

for VGS = 0 V ,-1 V and -4 V.

ID= IDSS(1 - VGS/VGS(off))2 Note:(VGS= 0 to VGS(off)controlsID)

VGS = 0 ; Id = Idss = 9 mA

VGS = -1 V; Id= 6.89 mA

VGS = -4 ; Id = 2.25 mA

7/29/2019 Ee105 Fet Lect

17/61

Example

The following information is included on the datasheet for a2N5457 JFET : typically IDSS = 3 mA, VGS(off) = -6V (maximum) &gfs(max) = 5000 S. Using these values, determine the forwardtransconductance for VGS = -4 V & find ID.

gfs(max) = gm0gm = 1.66 mSId = 0.33 mA

7/29/2019 Ee105 Fet Lect

18/61

JFET Characteristics and Parameters

Input resistance for a JFET is high since the gate-source junction is

reverse-biased.RIN = lVGS/IGSSl

where: IGSSis the gate reverse current@ a certain gate-to-source voltage.

Drain-to-source resistance is the ratio of changes ofVDS to ID.Large changes in VDSproduce very small changes in ID.

rds = VDS/ID

However, the capacitive effectscan offset this advantage,particularly at high frequencies. (remember varactors !!)

7/29/2019 Ee105 Fet Lect

19/61

JFET Biasing

Just as we learned that the bipolar junctiontransistor must be biased for proper operation,the JFET must also be biased for operation.

Lets look at some of the methods for biasing

JFETs.

In most cases the ideal Q-point will be the middle

of the transfer characteristic curve, which is about

half of the IDSS.

7/29/2019 Ee105 Fet Lect

20/61

JFET Biasing Self Bias

Self-bias is the most common type of

biasing method for JFETs. No voltage isapplied to the gate. The voltage to

ground from here will always be 0V.

However, the voltage from gate to source

(VGS) will be positive for n channel and

negative for p channel keeping the

junction reverse-biased. This voltage can

be determined by the formulas below.

ID= ISfor all JFET circuits.

(n channel) VGS= +IDRS

(p channel) VGS= -IDRS

VGS

VGS

See Ex.7-6 for derivation of VGS.

7/29/2019 Ee105 Fet Lect

21/61

JFET Biasing - Q-Point

Setting the Q-point requires us todetermine a value ofRS that will

give us the desired ID and VGS.The formula below shows therelationship.

RS=| VGS/ID|

To be able to do that we must firstdetermine the VGSandIDfrom the

either the transfer characteristic

curve or more practically from the

formula below. The data sheet

provides the IDSSand VGS(off).

VGSis the desired voltage to setthe bias.

ID= IDSS(1 - VGS/VGS(off))2

Transfer characteristic curveSee Ex.7-7 & 7- 8

V

7/29/2019 Ee105 Fet Lect

22/61

Example

Find VDS & VGS for the figurebelow. For this particular JFET, the

internal values such as gm,VGS(off) & IDSS are such that thedrain current, ID of approximately5mA is produced.

VDD = 15 VRD = 1kRs = 220 ID = 5 mARG = 10 M

VDD = VDS + VRS +VRDVDS = VDDVRS VRD = 8.9 VVGS = VG VS =-1.1V

See Ex.7-7 & 7- 8

7/29/2019 Ee105 Fet Lect

23/61

JFET Biasing - Q-Point

Determine the value of Rs required to self

bias p channel JFET with :

VGS (off) = 15 V

VGS = 5 V

IDSS =25 mA

Ans : Rs = 450

7/29/2019 Ee105 Fet Lect

24/61

JFET Biasing Midpoint Biasing

Since midpoint biasing is mostcommon, lets determine how this isdone.

Step 1. The values ofRSand RDdetermine the approximate midpoint

bias. Half ofIDSSwould be IDmidpoint. The VGS to establish this

can be determined by the formula

below.

Step 2. VGSVGS(off)/3.4IDmidV

*See Appendix B:

2ID = IDSS when VGS = VGS(OFF)/3.4

7/29/2019 Ee105 Fet Lect

25/61

JFET Biasing

The value ofRS needed to

establish the computed VGS can

be determined by the previously

discussed relationship below.

Step 3. RS=|VGS/ID|

The value ofRDneeded can be

determined by taking half ofVDD

and dividing it by ID.

Step 4. RD= (VDD/2)/IDV

See Ex. 7-9

7/29/2019 Ee105 Fet Lect

26/61

Example

Select resistor values for RD and Rs below to

set up an approximate midpoint bias. For this

particular JFET, the parameter are IDSS = 12

mA & VGS (off) = -3V, VD= 6 V. Given VDD= 12

V and RG = 10 M

ID = 6 mA

VGs= -882 mV

RS = 147

RD = 1 K

7/29/2019 Ee105 Fet Lect

27/61

JFET Biasing - Summary

Remember the purpose of biasing isto set a point of operation (Q-point).In a self-biasing type JFET circuit theQ-point is determined by the givenparameters of the JFET itself andvalues ofRSand RD. Setting it at

midpoint on the drain curve is mostcommon.

One thing not mentioned in thediscussion was RG. Its value isarbitrary but it should be largeenough to keep the input resistancehigh.

7/29/2019 Ee105 Fet Lect

28/61

JFET Biasing Graphical Analysis

The transfer characteristic curve

along with other parameters can beused to determine the midpoint biasQ-point of a self-biased JFET circuit.

First determine the VGSat IDSS from

the formula below.VGS= -IDRS

#1VGS = -IDRs = (0)(470) = 0V

#2VGS = -IDRS=(10mA)(470)= -4.7V

Where the two lines intersect givesus the IDand VGS (Q-point) neededfor midpoint bias. Note that load lineextends from VGS(off)(ID= 0A) to VP(ID= IDSS)

#1

#2

Load Line

(ID = IDSS/2)Intersect

See Ex. 7-10

7/29/2019 Ee105 Fet Lect

29/61

JFET Biasing Voltage-Divider

Voltage-divider bias can also be used tobias a JFET. R1and R2are used to keep the

gate-source junction in reverse bias.

Operation is no different from self-bias.

Determining ID&VGS for a JFET voltage-

divider circuit with VDgiven can be

calculated with the formulas below.

VS=IDRS

VG

= (R2

/R1

+R2

)VDD

VGS=VG-VS

ID= (VDDVD)/RD

See Ex. 7-11

7/29/2019 Ee105 Fet Lect

30/61

Example

Determine ID

& VGS

for the JFET with voltagedivider bias below, given that for this particular

JFET the internal parameter values are such

that VD = 7 V.

VDD = 12 VRD = 3.3 k

Rs = 2.2 k

R1 = 6.8 M

R2 = 1 M

VS=IDRS

VG= (R2/R1+R2)VDD

VGS=VG-VS

ID= (VDDVD)/RD

ID=1.5 mA

Vs= 3.3 V

VG= 1.54 V

VGS = -1.76 V

7/29/2019 Ee105 Fet Lect

31/61

JFET Biasing Graphical Analysis

In using the transfer characteristiccurve to determine the approx. Q-point, we must establish the twopoints for the load line.

The 1st point is for ID= 0.

(Note: VGS = VG when ID = 0).

VGS =VG = (R2/R1+R2)VDD

The 2nd point is IDwhen VGS

is 0.ID=VG/RS

2nd pt.

1st pt.

Intersect

See Ex. 7-12

7/29/2019 Ee105 Fet Lect

32/61

JFET Biasing gm variable

Transfer characteristics can vary for JFETs ofthe same type (just like the of a transistor).

This will adversely affect the Q-point. The

voltage-divider bias is less affected by thisthan self-bias.

This is an undesirable problem that inextreme cases would require trying several of

the same type until you find one that workswithin the desired range of operation.

7/29/2019 Ee105 Fet Lect

33/61

Q-Point Instability

Shaded area between Q1 andQ2 illustrates the variability ofQ-point with changes in thetransfer characteristics (gm) ofa selection of replacement

JFETs.

Self-bias exerts no control overgm variability.

Voltage-divider bias offers someimprovement.

7/29/2019 Ee105 Fet Lect

34/61

The MOSFET

The metal oxide semiconductor field effect transistor (MOSFET) isthe second category of FETs. The chief difference is that there is no

actual pn junction as the p and n materials are insulated from eachother. MOSFETs are static sensitive devices and must be handled byappropriate means.

These are depletion MOSFETs (D-MOSFET). Note thedifferences in construction with the E-MOSFETs on next slide)

7/29/2019 Ee105 Fet Lect

35/61

THE MOSFET

MOSFETs have characteristics similar to JFETs and

additional characteristics that make then very useful

There are 2 types of MOSFETs:

Depletion mode MOSFET (D-MOSFET) Operates in Depletion mode the same way as a

JFET when VGS 0

Operates in Enhancement mode like E-MOSFET

when VGS > 0

Enhancement Mode MOSFET (E-MOSFET) Operates in Enhancement mode

IDSS = 0 until VGS > VT (threshold voltage)

7/29/2019 Ee105 Fet Lect

36/61

D-MOSFET

These are depletion MOSFETs (D-MOSFET). Interestingly, they

can also be biased to operate as enhancement mode D-MOSFETS

Note the differences in construction with the E-MOSFETs on next slide)

7/29/2019 Ee105 Fet Lect

37/61

The D-MOSFET Basic OperationA D-MOSFET may be biased to operate in two modes:

the Depletion mode or the Enhancement mode

7/29/2019 Ee105 Fet Lect

38/61

The D-MOSFET Depletion Mode

The D-MOSFET can beoperated in depletionor enhancementmodes. To be operated

in depletion mode, thegate is made morenegative effectivelynarrowing the channelor depleting the

channel of electrons.

Note the solid lines

indicating D_MOSFET.

7/29/2019 Ee105 Fet Lect

39/61

The D-MOSFET Depletion Mode Operation

The transfer characteristics are similar to the JFET

In Depletion Mode operation:

When VGS = 0V, ID = IDSS

When ID = 0 ; VGS = VGS(off)

When VGS(off) = -Vp

The formula used to plot the Transfer Curve, is:

2

GS

D DSS

P

VI = I 1 -

V

7/29/2019 Ee105 Fet Lect

40/61

The D-MOSFET Enhancement Mode

To be operated in theenhancement mode thegate is made morepositive, attracting moreelectrons into the channel

for better current flow.Remember we are using nchannel MOSFETs fordiscussion purposes. For pchannel MOSFETs,polarities would change.

7/29/2019 Ee105 Fet Lect

41/61

The D-MOSFET Enhancement Mode

2

GS

D DSS

P

VI = I 1 -

V

7/29/2019 Ee105 Fet Lect

42/61

E-MOSFET has no physical channel

The enhancement MOSFET (E-MOSFET) has no structural channel. Thechannel is induced thru biasing. For an n-channel device, a +VG inducesa channel to form (must exceed a threshold voltage).

NoChannel

7/29/2019 Ee105 Fet Lect

43/61

The E-MOSFET

The E-MOSFET orenhancementMOSFET canoperate in only the

enhancementmode. With apositive voltage onthe gate the psubstrate is made

more conductive.

Note: Broken line indicates E_MOSFET

7/29/2019 Ee105 Fet Lect

44/61

Power MOSFETs

The lateral double diffused MOSFET (LDMOSFET) and theV-

groove MOSFET (VMOSFET) are specifically designed for highpower applications.

Dual gate MOSFETs have two gates, which helps controlunwanted capacitive effects at high frequencies.

LDDMOSFET

VMOSFET

Dual Gate MOSFET

7/29/2019 Ee105 Fet Lect

45/61

MOSFET Characteristics and Parameters

Since most of the characteristics and parameters

of MOSFETs are the same as JFETs we will coveronly the key differences.

7/29/2019 Ee105 Fet Lect

46/61

D-MOSFET Characteristics and Parameters

For the D-MOSFET we have to also consider its enhancement mode.Calculating IDwith given parameters in the enhancement modeanddepletion mode is the same. Note this equation is no different for IDthan JFETs and the transfer characteristics are similar except for itseffect in the enhancement mode.


Remember n and p channel polarity differences.See Ex. 7-13

7/29/2019 Ee105 Fet Lect

47/61

Example

For a certain D MOSFET, IDSS= 10 mA and VGS(0ff)= -8 V

a) Is this an n channel or p channel ?b) Calculate ID at VGS = -3V ;ans: 3.9mA

c) Calculate ID at VGS= 3 V ;ans:18.9mA


Remember n and p channel polarity differences.See Ex. 7-13

7/29/2019 Ee105 Fet Lect

48/61

E-MOSFET Characteristics and Parameters

The E-MOSFET for all practical purposes does not conduct until VGS

reaches the threshold voltage (VGS(th)). IDwhen it is when conductingcan be determined by the formulas below. The constant Kmust first

be determined. ID(on)is a data sheet given value.

K= ID(on)/(VGS- VGS(th))2

ID=K(VGS-VGS(th))2

See Ex. 7-14

7/29/2019 Ee105 Fet Lect

49/61

Example

The data sheet for a given 2N 7008 E MOSFET gives ID(on) = 500mA

(minimum) at VGS = 10 V & VGS(th) =1V. Determine the drain currentfor VGS = 5 V

K= ID(on)/(VGS- VGS(th))2 ; ans=6.17mA/v 2

ID=K(VGS-VGS(th))2 ; ans= 98.8 mA

See Ex. 7-14

7/29/2019 Ee105 Fet Lect

50/61

MOSFET Biasing

The three ways to bias a MOSFET are zero-bias, voltage-dividerbias, and drain-feedback bias.

For D-MOSFET, zero biasing as the name implies has no appliedbias voltage to the gate. The input voltage swings it intodepletionand enhancement mode.VGS = 0, ID = IDSS therefore, no amplification, input isolation only.

7/29/2019 Ee105 Fet Lect

51/61

Example

Determine the drain to source voltage for the circuit shown belowwhere VGS(off) = -8 V and IDSS = 12mA ,RD = 620 & VDD= 18 V

VDS = VDD - IDSS RD; ans= 10.6V

7/29/2019 Ee105 Fet Lect

52/61

E- MOSFET Biasing

For E-MOSFETs, no zero biasing. Voltage-

divider bias used to set the VGSgreaterthan the threshold voltage (VGS(th)). ID

can be determined as follows. To

determine VGS, normal voltage divider

methods can be used. The following

formula can now be applied.

K= ID(on)/(VGS -VGS(th))2

ID = K(VGS-VGS(th))2

VDScan be determined by application ofOhms law and Kirchhoffs voltage law tothe drain circuit.

7/29/2019 Ee105 Fet Lect

53/61

E-MOSFET Biasing

With drain-feedback biasthere is no voltage dropacross RGmaking VGS= VDS.With V

GSgiven determining

ID can be accomplished bythe formula below.

ID= VDD- VDS/RD

l

7/29/2019 Ee105 Fet Lect

54/61

Example

Determine VGS & VDS for the E MOSFET

circuit below. Assume ID(on) = 200mA at

VGS = 4V & VGS(th) = 2 V. VDD = 24V ,

R1= 100 k , R2 =15 k & RD = 200.

VGS = [R2/ (R1+R2) ] VDD

VDS = VDDID * RD

K= ID(on)/(VGS -VGS(th))2

ID = K(VGS-VGS(th))2

Summary Table

7/29/2019 Ee105 Fet Lect

55/61

January 2004 ELEC 121 55

Summary Table

JFET D-MOSFET E-MOSFET

7/29/2019 Ee105 Fet Lect

56/61

Troubleshooting

As always, having a thorough knowledge of the devicesmakes it easier to utilize them for troubleshooting circuits.We will discuss some of the common faults associatedwith FET circuits.

Experience in troubleshooting is the best teacher, andhaving basic theoretical knowledge is extremely helpful.

7/29/2019 Ee105 Fet Lect

57/61

Troubleshooting

IfVD= VDDin a self-biased

JFET circuit, it could be one ofseveral opens. It is a clearindication ofno drain current.Use of senses to check forobvious failures is the first andeasiest step. Replace the FETonly if associated componentsare known to be good.

IfVDis less than normal in aself-biased JFET circuit, an

open in the gate circuit ismore than likely the problem.The low drain voltage wouldbe indicative ofmore draincurrent flowing than normal.

less

T o bleshooting

7/29/2019 Ee105 Fet Lect

58/61

Troubleshooting

In a zero-biased D-MOSFETor drain-feedback biasedE-MOSFET, an open in thegate circuit is more difficult to

detect. It may seem to bebiased properly with dcvoltages but will fail to workproperly when an ac signal isapplied.

This is a classic FET fault!!

7/29/2019 Ee105 Fet Lect

59/61

Troubleshooting

With a voltage-divider biasedE-MOSFET, circuitfaults are moreeasily detected.

With an open R1there is no draincurrent, so theVD= VDD. Withan open R2full

VDD is applied tothe gate turningit on fully. VD= 0

7/29/2019 Ee105 Fet Lect

60/61

Summary

JFETs are unipolar devices.

JFETs have three terminals: source, gate, and drain.

JFETs have a high input resistance since the gate-source junction is reverse-biased.

IDSS for all FETs is the maximum amount ofcurrentflow in the drain circuit when VGSis 0V.

All FETs must be biased for proper operation.Midpoint is most common for use in amplifiers.

Unwanted capacitance associated with FETs can bedealt with by using dual gate-type FETs.

7/29/2019 Ee105 Fet Lect

61/61

Summary

E-MOSFETs have no physical channel. A channel isinduced with VGSgreater than VGS(th).

There are special MOSFET designs forhighpower applications.

E-MOSFETs have no IDSSparameter.

MOSFETs differ in construction in that the gate isinsulated from the channel.

D-MOSFETs can operate in both depletion andenhancement modes. E-MOSFETs can only operate in

the enhancement mode.

Documents

Ee105 Fet Lect