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EE141
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EE1411© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 1
IFSINIFSIN
IMPLEMENTACIIMPLEMENTACIÓÓ FFÍÍSICA DE SISTEMES INTEGRATS NANOMSICA DE SISTEMES INTEGRATS NANOMÈÈTRICSTRICSIMPLEMENTACIIMPLEMENTACIÓÓN FN FÍÍSICA DE SISTEMAS INTEGRADOS NANOMSICA DE SISTEMAS INTEGRADOS NANOMÉÉTRICOSTRICOSPHYSICAL IMPLEMENTATION OF NANOMETER INTEGRATED SYSTEMSPHYSICAL IMPLEMENTATION OF NANOMETER INTEGRATED SYSTEMS
Prof. Xavier Aragones ([email protected])Prof. Antonio Rubio ([email protected])Prof. Francesc Moll ([email protected])Prof. Josep Rius ([email protected])
Fall 2008
EE1412© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 2
WEB PAGEWEB PAGEhttphttp://://weble.upc.esweble.upc.es//ifsinifsin//
EE141
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EE1413© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 3
COURSE CONTENTSCOURSE CONTENTS
Objective: to provide the student the necessary knowledgeto achieve a successful implementation of his design.
Contents:• Techniques and implementation alternatives of integrated systems• Classical and advanced packages • Interconnections, effects and models. Power-supply and clock distribution • Parasitic couplings: electrical and thermal. Electromagnetic shielding. Heat dissipation. • Signal integrity. Internal noise coupling: switching, substrate, crosstalk. Techniques to reduce coupling and noise. • Process variations, categories, models, mismatching and layout implementation techniques. • Input/output circuits. Pads, protections.• Specific design methodologies for nanometer-scale systems.
EE1414© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 4
COURSE SCHEDULECOURSE SCHEDULEINTRODUCTION: XAVIER ARAGONES, 22 and 23 September.
Implementation techniques and options for integrated systems
BLOCK 1: XAVIER ARAGONES, 29 and 30 September, 6 and 7 October.Substrate as a progagation means. Substrate couplingModeling of interconnects
BLOCK 2: JOSEP RIUS, 13, 14, 20, 21 and 27 October.Crosstalk between interconnects.Power-supply networks. SSN
BLOCK 3: FRANCESC MOLL, 28 October, 3, 4, 10 and 11 November.Process variationsImpact on digital and analog circuits
BLOCK 4: XAVIER ARAGONES, 17, 18, 24 and 25 NovemberLayout techniques. Design rules
BLOCK 5: ANTONIO RUBIO, 1, 2, 9, 15 and 16 DecemberClock distributionThermal couplingTolerant design methodologies
EE141
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EE1415© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 5
COURSE EVALUATIONCOURSE EVALUATION
75% CONTINOUS ASSESSMENT:• Guided works, presentations, exercises...• Attendance• A mark is obtained from each block
25% FINAL EXAMINATION:• Short questions / exercises• 7th January
EE1416© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 6
INTRODUCTIONINTRODUCTION
• Reminder: IC manufacturing - photolithography
• How are ICs today ?
• Smaller, but less certain
• System-on-a-Chip (SoC)
• Signal Integrity
• Needs for First silicon success in nanometer technologies
EE141
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EE1417© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 7
Integrated Circuits (ICs or chips):manufactured on Silicon wafers
wafer diameter: 150 - 200 - 300 mm6” 8” 12”
waferthickness:~0.5 mm.
IC MANUFACTURINGIC MANUFACTURING
EE1418© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 8
wafer
chip
SiliconPN
doping on the order of10 impurities/cm
(little conductive)
15 3
IC MANUFACTURINGIC MANUFACTURING
Integrated Circuits (ICs or chips):manufactured on Silicon wafers
EE141
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EE1419© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 9
Silicon wafersmanufacturing of ingots of crystalline Silicona purity up to 99.9999999% is required
slicing of the wafers
IC MANUFACTURING: IC MANUFACTURING: thethe waferwafer
EE14110© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 10
Each step of the manufacturing process that implies thedefinition of a geometry needs a mask
• draw the mask with an electronbeam (scale 1:4)
• replicate the mask of the IC to coverthe wafer surface
IC MANUFACTURING: IC MANUFACTURING: thethe masksmasks
EE141
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EE14111© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 11
• How do you transfer the drawing in the mask to the chip surface? Example: definition of the gate of a MOS transistor
(complete example at http://micro.magnet.fsu.edu/electromag/java/transistor/)
IC MANUFACTURING: IC MANUFACTURING: thethe lithographylithography
EE14112© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 12
IC MANUFACTURING: IC MANUFACTURING: thethe lithographylithography
• How do you transfer the drawing in the mask to the chip surface? Example: definition of the gate of a MOS transistor
(complete example at http://micro.magnet.fsu.edu/electromag/java/transistor/)
EE141
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EE14113© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 13
IC MANUFACTURING: IC MANUFACTURING: thethe lithographylithography
• How do you transfer the drawing in the mask to the chip surface? Example: definition of the gate of a MOS transistor
(complete example at http://micro.magnet.fsu.edu/electromag/java/transistor/)
EE14114© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 14
Manufacturing process: successive implants of P or N-type impurities, oxide growths, material depositions(polysilicon, aluminium, etc.), forming the circuit as a stack oflayers.
photolithography
White room
IC MANUFACTURING: IC MANUFACTURING: thethe lithographylithography
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EE14126© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 26
ICsICs ACCORDING TO TEXTBOOKSACCORDING TO TEXTBOOKS
EE14127© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 27
HOW ARE HOW ARE ICsICs TODAY ?TODAY ?
624V, 32V5.5V1.8V0.18 um High Voltage
63.3V1.8V0.18 um CMOS Image Sensor
63.3V1.8V0.18 um Mixed-Mode/RFCMOS
63.3V1.8V0.18 um Logic
8Cu3.3V1.2V0.13 um Copper Mixed-Mode/RFCMOS
8Cu2.5V,
3.3V, 3.3VHG
1.2V0.13 um Copper Logic
9Cu1.8V, 2.5V,3.3V
1.0V, 1.2V90 nm Copper Logic
10Cu1.8V, 2.5V, 3.3V
1.0V, 1.2V65 nm Copper Logic
High VoltageI/OCore
Max. Metal Layers
Voltage OptionsTechnology
0.25 um0.35 um0.5 um0.6 um0.8 um(…)
• Different technology nodes• Different technology “flavours”to
the
past
to th
e fu
ture
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EE14128© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 28
HOW ARE HOW ARE ICsICs TODAY ?TODAY ?
to the past to the future
50 nm length(IEDM 2002)
30 nm prototype (IEDM 2000)
65 nm node
2005
20 nm prototype(VLSI 2001)
45 nm node2007
90 nm node
2003
22 nm node
2011
10 nm prototype(DRC 2003)
25 nm
15nm
15 nm prototype(IEDM 2001)
32 nm node2009
50 nm length(IEDM 2002)
30 nm prototype (IEDM 2000)
65 nm node
2005
30 nm prototype (IEDM 2000)
65 nm node
2005
20 nm prototype(VLSI 2001)
45 nm node2007
20 nm prototype(VLSI 2001)
45 nm node2007
90 nm node
2003
22 nm node
2011
10 nm prototype(DRC 2003)
22 nm node
2011
10 nm prototype(DRC 2003)
25 nm
15nm
15 nm prototype(IEDM 2001)
32 nm node2009
25 nm
15nm
15 nm prototype(IEDM 2001)
32 nm node2009
25 nm
15nm
15 nm prototype(IEDM 2001)
32 nm node2009
from Massimo Conti, BCN 2006
EE14129© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 29
HOW ARE HOW ARE ICsICs TODAY ?TODAY ?
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EE14130© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 30
HOW ARE HOW ARE ICsICs TODAY ?TODAY ?
• 65 nm printed gate length, 35 nm physical gate length• Multiple VT voltages for Vdd = 1 V, Vdd = 1,2 V.• 1.2 nm gate oxide• Ultra-shallow drain-source.
Characteristics of a typical 65 nm process :
• Si3N4 spacer necessary to build drain-source extensions.• Nickel Silicide (NiSi) for low resistance at gate, and source and drain extensions.• Strained silicon at channel
Check how complex is to build your own 65 nm transistor!! :http://www.appliedmaterials.com/products/assets/transistor_challenge/index.html
EE14131© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 31
Ge atoms are injected to the channel, thus the atomic lattice is strained and mobility increases (20% approx.)
HOW ARE HOW ARE ICsICs TODAY ?TODAY ?
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EE14132© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 32
HOW ARE HOW ARE ICsICs TODAY ?TODAY ?
• No more polysilicon gate: Metal gate• No more SiO2 gate oxide: Hafnium-based high-k insulator
Characteristics of a typical 45 nm process :
EE14133© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 33
HOW ARE HOW ARE ICsICs TODAY ?TODAY ?
• 8 – 10 metal layers• Cu interconnects• Low-k dielectrics (carbon doped oxide)• M1 distance ∼ M1 width ∼100 nm• M5 distance ∼ M5 width ∼150 nm• Approx. 600 m/cm2
(excluding global levels)• M1 length at which RC delay = gate delay: 80 µm
Characteristics of a typical 65 nm process :
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EE14134© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 34
HOW ARE HOW ARE ICsICs TODAY ?TODAY ?
• Extra low-resistance top layer (M9) for low-resistance power-supply distribution between package and lower metals
Characteristics of a typical 45 nm process :
C4 package bump
Via 9
Metal 9
Metal 1 - 8}
EE14135© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 35
HOW ARE HOW ARE ICsICs TODAY ?TODAY ?
Devices for Mixed-Mode / RF :
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EE14136© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 36
HOW ARE HOW ARE ICsICs TODAY ?TODAY ?Devices for Mixed-Mode / RF :
p-well
n-well
• Special layers for inductors
• Special layers for capacitors
• Special layers for resistors
• Triple well
• Special layers for NPN
EE14137© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 37
Lithography (manufacturing)
resolution does not increase as
fast as demanded by
technology evolution !
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
10
1
0.1
1980 1990 2000 2008
Silicon feature size
Lithography Wavelength
436nm365nm
193nm0.25µm
0.13µm
0.6µm
3µm
0.05µm
ABOVE WAVELENGTH SUB WAVELENGTH
from Massimo Conti, BCN 2006
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EE14138© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 38
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
90 nm process :
target results (due to lithography diffraction
effects)from Massimo Conti, BCN 2006
EE14139© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 39
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
target results (due to lithography diffraction
effects)from Massimo Conti, BCN 2006
Sub Wavelength Lithography cause strong variations on metal lines width, MOSFET width and length …
EE141
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EE14140© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 40
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
Oxide variations over a 20 Å nominal oxide thickness :
from Massimo Conti, BCN 2006from Chandu Visweswarian, 2004
EE14141© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 41
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
from Massimo Conti, BCN 2006
Dopant concentration variability has strong influence for small area devices
Technology (nm)
Mean Number
of DopantAtoms
EE141
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EE14142© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 42
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
Example: normalized drain current dispersions of 2 MOSFETs for different geometries and distances
W=L= 0.5 µm d= 5µm W=L= 10 µm d= 5µm
W=L= 10µm d= 100µmW=L= 0.5 µm d= 100µm
Performance variability :
from Massimo Conti, BCN 2006
EE14143© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 43
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
from Massimo Conti, BCN 2006
Probability Density
Technology0,25 µm
0,18 µm
0,13 µm
AcceptableRegion
Not AcceptableRegion
Performance
Effect of process variability on performance:
EE141
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EE14144© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 44
From: R. Madge, ITC 2004
Time
Defect Density
180nm
90nm90nm130nm130nm65nm65nm
00 02 0604
45nm
• Defect density decreases in a mature technology• But increases as feature size reduces !!
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
from Massimo Conti, BCN 2006
EE14145© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 45
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
from Massimo Conti, BCN 2006
EE141
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EE14146© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 46
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
from Massimo Conti, BCN 2006from: C. Visweswariah, IBM
Temperature varies in space and time (switching activity)Temperature effect on clock skew, circuit delay, etc.
IBM Power4Dual-core0,13 µm copper, SOI technology1,3 GHz
EE14147© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 47
SMALLER, BUT LESS CERTAINSMALLER, BUT LESS CERTAIN
Isolated interconnects ??? Welcome to reality!: crosstalk, crosstalk, delay, delay, ...
EE141
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EE14148© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 48
Environmental (Vdd, Temperature,
Coupling Noise, Signal Integrity, Electromigration)D
ynam
ic
α Particle …Single Event Upsets
Technological Process Variations - intradie- interdie
ParametricS
tatic Spot Defects
Design Logic Bugs
Catastrophic
DEFECT TYPESDEFECT TYPESDesign rules provided to minimize them
Objective of this course: how to cope
with them
EE14149© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 49
Frank Op’t Eynde, et al., Fully-Integrated Single-Chip SoC for Bluetooth in 0,25 µm
CMOS, IEEE ISSC 2001
SYSTEMS ON A CHIP (SYSTEMS ON A CHIP (SoCSoC))
H. Darabi et al., Single Chip 802.11b in 0,18 um CMOS, including PA, PLL filter,
baseband and MAC, IEEE JSSC, December2005
EE141
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EE14150© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 50
1.8
mm
fo=1,57 GHzSensitivity -130 dBm (19 dB below thermal noise)
SYSTEMS ON A CHIP (SYSTEMS ON A CHIP (SoCSoC))
EE14151© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 51
SIGNAL INTEGRITYSIGNAL INTEGRITY
Paul van Zeijl, et al., “A Bluetooth Radio in 0,18 µm CMOS”, IEEE JSSC December 2002
Bluetooth radio + baseband in a single chip
0,18 µm CMOS technology
• System-on-a-Chip paradigm multiplies the problems of signal integrity (signal interactions)
• A clear example is digital switching noise coupled through the substrate to sensitive RF signals
EE141
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EE14152© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 52
SIGNAL INTEGRITYSIGNAL INTEGRITY• Digital power-supply lines are contaminated with inductive noise. This is the main agent of substrate noise
• Large circuits being switched on and off (for power saving)provoke current peaks and voltage droop
• Wire resistance provokes IR drop and significant voltage differences across the chip
dddIV Ldt
−
dIGND Ldt
+
© A. Khan, Cadence Design Systems Inc., 2003.
EE14153© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 53
SIGNAL INTEGRITYSIGNAL INTEGRITY• Interconnects: Coupling capacitance increases (+ crosstalk, + self-capacitance), Resistance increases (reduced cross-section, surface scattering, grain-size limitations, skin effect…)
• ⇒ RC constant of allinterconnects increases while gate τ decreases
• ⇒ Signal delays, clock skew impose severe design challenges
© Digital Integrated Circuits2nd
Rabaey, Chandrakasan, Nikolic
Clock skew in Alpha processor:
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EE14154© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 54
SIGNAL INTEGRITYSIGNAL INTEGRITY
• Power density (temperature) is one of the major challenges in microelectronics today
• Temperature differences imply performance differences
• Clock skew for example is also affected by temperature differences
EE14155© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 55
SYSTEMS IN A PACKAGE (SYSTEMS IN A PACKAGE (SiPSiP))
Heat Sink
Metal Cap
Flip Chip Flip ChipSMD SMD
B.T.
↑ Integration of non-CMOS technologies↑ Best technology option for each part↑ Solution to signal integrity↑ High-Q passives can be implemented
↓ Cost↓ Packaging Yield↓ Lack of system integration models/tools
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EE14156© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 56
NEED TO INCLUDE THESE NEED TO INCLUDE THESE EFFECTS IN DESIGN PROCESSEFFECTS IN DESIGN PROCESS
• First silicon success concept • Needed today:
© A. Khan, Cadence Design Systems Inc., 2003.
EE14157© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 57
NEED TO INCLUDE THESE NEED TO INCLUDE THESE EFFECTS IN DESIGN PROCESSEFFECTS IN DESIGN PROCESS
• First silicon success only possible if all the “nanometer effects” are accounted for during design process:
Design entry and synthesis
Pre-layout simulations
Layout synthesis / full custom design
Post-Layout simulation and final verifications
Manufacturing
Parasitics extraction
Conventional design flow :
EE141
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EE14158© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 58
NEED TO INCLUDE THESE NEED TO INCLUDE THESE EFFECTS IN DESIGN PROCESSEFFECTS IN DESIGN PROCESS
• Process, Vdd and thermal variations included in all design models Design entry and synthesis
Pre-layout simulations
Layout synthesis / full custom design
Post-Layout simulation and final verifications
Manufacturing
Parasitics extraction
Conventional design flow :
• Budgets for clock skew, thermal variations, Vdd and GND noise and drops
• Chip-package co-design
• Layout techniques for manufacturing, minimization of process variations, matching, signal integrity
• Models for all parasitics
EE14159© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 59
FUTURE CHALLENGE: DESIGN FUTURE CHALLENGE: DESIGN TOLERANT TO TOLERANT TO ““NANOMETER NANOMETER
EFFECTSEFFECTS””
• It must be assumed that “nanometer effects” (noise, couplings, voltage, temperature and process variations) are both unavoidable and unpredictable (in a deterministic way)
• Design must become tolerant to nanometer effects, tolerant to local failures.
• Models will become statistical, statistic design methodologies will be assumed, leading to desired yields.
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EE14160© Digital Integrated Circuits2nd
DOCTORATE PROGRAM “ELECTRONIC ENGINEERING“ UPC - URV - UIB IntroductionIntroduction - 60
PREPRE--REQUISITES:REQUISITES:
• CMOS technology basic concepts (layers, geometry, models)• CMOS technology manufacturing process (basic concepts)• Fundamentals of CMOS digital and analog circuit design• IC design methodology