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EE221 Electronics -II

Lecture 1

EE221 Spring 2012

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EE-221 ELECTRONICS -II

EE221 Spring 20123

TEXT:Microelectronic Circuits Sixth Edition,by Sedra, Smith OxfordUniversity Press

REFERENCEFundamentals of Microelectronics, by Behzad Razavi, John Wiley & Sons Inc

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EE-221 ELECTRONICS -II

EE221 Spring 20124

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OV DS V v

RECALL: NMOS Essential Relationships

Channelno: tnGS V v

)21

( 2'

= DS DSOV n D vvv L

W k i RegionTriodein NMOS

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OV DS V v


Channelno: tnGS V v

RegionSaturationin NMOS( ) 121

2' DSOV n D vv LW

k i +=

tnGD V v

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RECALL: PMOS Essential Relationships

Channel;no: tpSG V v

OV SD V v

)21

( 2'

=SDSDOV p D vvv L

W k i RegionTriodeinPMOS

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21

2'

OV p D v LW

k i

=


SaturationinPMOS

SDSG DG vvv =

Channel;no: tpSG V v

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RECALL: BJT Circuits at DC

Cut-off Mode

EBJ >> ReverseBiased

CBJ >> ReverseBiased

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BJT Circuits at DC

Active Mode

EBJ >> ForwardBiased

CBJ >> ReverseBiased

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BJT Circuits at DC

Saturation Mode

EBJ >> ForwardBiased

CBJ >> ForwardBiased

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Typical CMOS Parameters

Parameters NMOS PMOS NMOS PMOS NMOS PMOS NMOS PMOS NMOS PMOS

15 15 9 9 6 6 4 4 2.7 2.7

2.3 2.3 3.8 3.8 5.8 5.8 8.6 8.6 12.8 12.8

550 250 500 180 460 160 450 100 400 100

127 58 190 68 267 93 387 86 511 1280.7 -0.7 0.7 -0.8 0.5 -0.6 0.5 -0.5 0.4 -0.4

5 5 3.3 3.3 2.5 2.5 1.8 1.8 1.3 1.3

25 20 20 10 5 6 5 6 5 6

0.2 0.2 0.4 0.4 0.3 0.3 0.37 0.33 0.36 0.33

0.8 m 0.5 m 0.25 m 0.18 m 0.13 m

(nm)

(fF/ )

(A / )

(V)

(V)

/m)

(fF/ )

( cm / V.s)

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Typical Parameters for BJT

Parameters NPN Lateral PNP NPN Lateral PNP

500 900 2 2

200 50 100 50

130 50 35 30

50 60 8 18

0.35ns 30ns 10ps 650ps

1pF 0.3pF 5fF 14fF0.3pF 1pF 5fF 15fF

200 300 400 200

Standard HV Process Advanced LV Process

(

(V)

(V)

(A/A)

(A)

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Comparison of MOSFET &BJT

EE221 Spring 2012

Students to thoroughly read and understand all parameterslisted in the table mentioned below:

SEDRA & SMITH 5 Ed Table 6.3

SEDRA & SMITH 6 Ed Table 7.A.3

The student to work to understand Examples 6.1 and 6.2and attempt EXERCISE 6.1 and 6.2

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The Basic MOSFET / BJT Cell

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Active Loaded MOSFET / BJT Cell

EE221 Spring 2012

In IC technology it is difficult to implement resistances with

precise values. A very high load resistance is effectively implemented in the

drain (collector) loop; thus higher gain is achieved.

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Active Loaded MOSFET / BJT Cell

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POINTS TO NOTE

The MOSFET is biased to operate in Saturation Region. The BJT is biased to operate in Active region. Current = and =

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CE Amplifier with Current-Source Load

r Rin =

omvo r g A =oo r R

=Assume IdealCurrent Source soLoad Resistanceis infinite

o

vo

A

A

astoreferredbeWill

GAININTRINSICtoreferredisit

gainpossiblemaximumtheis

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CE Amplifier with Current-Source Load

r Rin =

omvo r g A =

oo r R=

(A) ............T

C m V

I g =

(B) ............C

Ao I

V r =

T

Aom V

V r g A ==0

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Typical Parameters for BJT

Parameters NPN Lateral PNP NPN Lateral PNP

100V-130V 5V-35V

25 25

4000-5200 200-1400

Standard HV Process Advanced LV Process

(V)

(mV)

(V / V)

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CS Amplifier with Current-Source Load

=in R

omvo r g A=

oo r R =

Assume IdealCurrent Source soLoad Resistanceis infinite

o

vo

A

A

astoreferredbeWill

GAININTRINSICtoreferredisit

gainpossiblemaximumtheis

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CS Amplifier with Current-Source Load

2OV

Ao V

V A =

2

OV

Ao

V

LV A

=

(A) ............2 / OV

Dm V

I g =

(B).......I) / (2 D LW C g oxnm =

(C) .........V A

D D

Ao

I

L

I

V r

==

D

oxn Ao

I

LW C V A

) / )((2 =

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Typical CMOS Parameters

0.8 m 0.5 m 0.25 m 0.18 m 0.13 mParameters NMOS NMOS NMOS NMOS NMOS

0.7 0.7 0.5 0.5 0.4

5 3.3 2.5 1.8 1.3

25 20 5 5 520 10 1.25 0.9 0.65

0.96 0.6 0.33 0.1 0.033

21 16.7 3.8 9 19.7

(V)

/m)

(V)

(V)/2 (V)

(V /V)

EE221 Spring 2012

The value of for new technologies is in the range of 0.15Vto 0.3V ( is 0.075V 0.15V)

The numerator quantity is both process dependent and devicedependent and is steadily decreasing ( = )

For a given technology can be increased by using a longerMOSFET and lower ( but this also deceases the amplifierBW )

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Effect of Output Resistance of Current-

Source Load

I V r Ao

22

=

2])[)((21

tpG DDox p V V V LW

C I = I

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Source Load

I V r Ao

22

=

2])[)((21

tpG DDox p V V V LW

C I =

Q2&Q1forsameisAssume21

Aomv V r g A =

)||( 211 oomi

ov r r gv

v A =

ov A A 21

Therefore=

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Source Load (Print Version)

I

V r Ao

22

=

2])[)((2

1tpG DDox p V V V

L

W C I =

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Example 7.2 & 7.3 S&S 6EdSec6.5.2 Ex 6.8 S&S 5Ed

A practical circuit implementation ofthe common-source amplifier isshown in figure on the left. Here the

current-source transistor Q2 is theoutput transistor of a current mirrorformed by Q2 and Q3 and fed with areference current I-ref.

Assume that Q2 and Q3 arematched. Also assume that I-ref is astable, well-predicted current that isgenerated with a special circuit onthe chip.

Determine the Voltage TransferCharacteristic (VTC), that is,versus .

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Example 7.2

The Current Mirror appears as a

Load in the drain of the transistorQ1.

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Example 7.2

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Current Mirror (PMOS)

1 / 12 / 2

shown thatbecanIt 2

= LW LW

I I REF D

EE221 Spring 2012

thenandIf 22121 REF D I I L LW W ===

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Current Mirror (PMOS)

(A) ............)(33

21 2'

3 t SGn D V V LW

k I

=

(B) ............ 3 REF D I I =

(C) ............)(

2

2

2

1 2'2 t SGn D V V

L

W k I

=

(D) ............ 3 / 32 / 2

32

= LW LW

I I D D

(E) ............ 3 / 32 / 2

2

=

LW LW I I REF D

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NMOS CCS (Hidden Slide)

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NMOS Current Mirror (Hidden Slide)

1 / 12 / 2

shown thatbecanIt 2

= LW LW

I I REF D

EE221 Spring 2012

thenandIf 22121 REF D I I L LW W ===

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(A) ............)(11

21 2'

1 t GSn D V V LW

k I

=

(B) ............ 1 RV V V I I GSSS DD REF D +==

(C) ............)(

2

2

2

1 2'2 t GSn D V V

L

W k I

=

(D) ............ 1 / 12 / 2

12

= LW LW

I I D D

(E) ............ 1 / 12 / 2

2

=

LW LW I I REF D

EE221 Spring 2012

NMOS Current Mirror (Hidden Slide)

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Example 7.2

l

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Example 7.2

E l 7 2

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Example 7.2

NOTE that will have drain current equal to only when= =

Q2 operates in saturation as long as = or (Max output voltage)

E l 7 2

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Example 7.2

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Recall: MOSFET Voltage Gain

(Animated Version)

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Recall: MOSFET Voltage Gain (Print Version)

ll OS l G i

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Recall: MOSFET Voltage Gain

(Print Version)

Example 7 2

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Example 7.2

=

Example 7 2 (Hidden Slide)

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Example 7.2 (Hidden Slide)

Example 7 2

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Example 7.2

Do Example 7.3Do Example 7.3

Increasing the Gain of the Basic Cell

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EE221 Lect 1 Ver1