Embedded Linux

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2010. 09

안양대학교 전기전자공학과

서 삼 준

PXA 255 CPU : XScale

Embedded Linux

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Target Block Diagram

J TAG PortJ Flash / Multi ICE SDRAM

32M to 64M Byte

SRAM1M Byte

FLASH16M to 32MByte

Charactor LCDDisplay #1

BUFFER

PCMCIASocket #1

PS2 KeyBoard #1PS2 Mouse #1

LED Display * 8

Compact FlashSocket #1

7 SegmentHEX Display

PUSH ButtonSwitch * 8

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

TFT Color LCD640*480 (6.4")

BUFFER

BUFFER

Expansion PortSlot #1

Secondary EthernetLAN91C111

Primary EthernetLAN91C111

MMC/SD Socket #1 SPI

IrDA Module #1 IrDA

Full UART Socket#1

Bluetooth UART #1

Full UART

Bluetooth

USB Slave #1 UDC

BUFFER

TouchScreen

6.4"

ADS7846

Real Time ClockRTC4513

I2C EEPROMNM24C16

GPIO

I2C

SDRAM100Mhz

PXA255-400Mhz

XScale Core

I2C BUSConnector #1

I2C

BUFFER

AC’97 CodecCS4202

AC97 Inteface

MMC/SD Socket #1

Embedded Linux

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Platform Specification (1)

items specification

CPU Intel XScale PXA255 400Mhz

Memory SDRAM Samsung 64Mbyte

Flash Intel strata Flash 32Mbyte

주변장치

LCD LG TFT LCD 6.4” (640×480)

Touch Screen ADS7846, 4 wire Touch Interface

Serial FF_UART, BT_UART

USB USB 1.1 Slave

Ethernet LAN91C111 (10/100Base-T)

JTAG 74LCX245

IrDA ST_UART, HDSL3600

Audio AC97 Stereo Codec, CS4202

Embedded Linux

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Platform Specification (2)

items specification

주변장치

PCMCIA 1 slot

CF 1 slot

RTC Real Time Clock Module, RTC4513

TEXT LCD 20×2 TEXT LCD Module

Button Push Button ×8(Bus Control)

LED Discrete LED× 8, 7Segment LED ×4

Interface

Extend connector

120 pin

LCD Connector 30 pin

Inverter connector

5 pin

Touch connector 4 pin

JTAG connector 20 pin

Power connector

4 pin

Embedded Linux

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PXA 255 Processor CPU Overview

• High Performance 32-bit Microprocessor, max 400MHz

• Technology– 0.35um, 3 layer metal CMOS, 2.6 Million transistors– 256 PBGA package (17x17mm)

• XScale core, ARMv5TE 기반• Modified-Harvard Architecture 가 적용된 ARM

프로세서– Separate instruction/data cache : 32Kbytes– 2Kbyte mini data/instruction cache

• Instruction & data Memory Management Units (MMU)

• Debug capability via JTAG port

Embedded Linux

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System Integration Feature

• Memory control• Clock an power control• USB client interface• DMA controller• LCD controller• AC97(audio codec 97)• I2S (Inter-IC Sound Controller)• Multimedia Card Controller• FIR (Fast Infrared) communication port• Synchronous Serial Protocol Port• I2C(Inter-Integrated Circuit) Bus Interface Unit• General Purpose I/O pins (GPIO)• UARTs (Universal Asynchronous Receiver/Transmitter)

– Full/Bluetooth/standard/hardware• Real-Time clocks• OS timers• PWM (Pulse Width Modulation)• Interrupt Control• Network Synchronous Serial Port : other ASIC interface

Embedded Linux

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Palm Size Device : System Example

Intel®XScalePX255

PortableCommunicationsMicroprocessor

UARTCommunications

Tablet/ SerialKeyboard

AC97

InfraredCommunications

USB Synchronization Port

TFT ColorLCD

Display

SDRAM/DRAM

SMROM/ROM

Flash ROM

Glue Logic

SRAM

Variable Latency I/O

PCMCIA Interface(Flash, Modem)

Speaker

Microphone3.686MHz

32.768KHz

Embedded Linux

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PXA 255 CPU Functional Block

ASIC

Color or Grayscale LCD Controller

RTC

OS Timer

PWM(2)

InterruptController

Clock &Power Man.

I2S

I2C

AC97

FF_UART

BT_UART

Slow lrDA

Fast lrDA

SSP

MemoryController

VariableLatency

I/OControl

StaticMemoryControl

Gen

era

l P

urp

ose I

/ O

Peri

ph

era

l B

us

3.6864 MHzOsc

32.768 KHzOsc

System Bus

ROM/FlashSRAM

4 banks

DynamicMemoryControl

SDRAM/SMROM4 banks

DM

A C

on

troller

an

d B

rid

ge

CS #0,1,2

CS #3,4,5

0x4400_0000

XScaleCore

IMMU

DMMU

Icache(32 Kbytes)

Dcache(32 Kbytes)Minicache

Instructions

PC

Addr

WriteBuffer

ReadBuffer

Load/Store Data

MegacellCore

NSSP

USBClient

MMC

PCMCIA& CF

ControlXCVR

Socket 0, 1

Embedded Linux

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Xscale Core Architecture

Embedded Linux

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ARM Core General Register & PC

Embedded Linux

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PXA 255 CPU Registers

• Xscale Core(ARMv5TE ) Registers– ARM state general registers: 6 groups, 90 registers– ARM state program status registers : 6 groups, 11

registers

• System Control Register for Memory Mapped registers Interface– 20 fields about 380 registers

Embedded Linux

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System Control Register

• Example DMA controller

Embedded Linux

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PXA 255 Micro-Architecture

Branch Target Buffer

TraceBuffer

InstructionCache

32KBytes

Data Cache32 KBytes

Mini D-Cache2 KBytes

MMU

MMU WriteBuffer

SystemManagement

DebugJTAG

CP0 Multiplier /

Accumulator

CP 15 Config

Registers

CP 14 PerformanceMonitoring

IRQ FIQ

Interrupt

Request

Coprocessor Interface

Instruction

Execution

Core Data

AddressData

Core Memory Bus

Mini I-Cache2 KBytes

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XScale Core Architecture Features

InstructionCache 32 Kbytes 32 Ways Lockable by line

Micro-Processor7 Stage pipeline

Data Cache Max 32 Kbytes 32 ways WR-Back or WR-Through Hit under miss

Debug Hardware Breakpoints Branch History Table

MAC Single cycle Throughput (16*32) 16-bit SIMD 40-bit accumulator

PowerMgntControl

Write Buffer 8 entries Full coalescing

JTAG

Data RAM Max 28 Kbytes Re-map of data cache

Branch TargetBuffer128 entries

IMMU 32 entry TLB Fully associative Lockable by entry

DMMU 32 entry TLB Fully associative Lockable by entry

Fill Buffer 4~8 entries

PerformanceMonitoring

Mini-DataCache 2 Kbytes 2 ways

Embedded Linux

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Arm Instruction Set Format

Embedded Linux

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PXA 255 Instruction Operation

• XScale Core– 32Bit RISC– 32Bit registers– 32Bit instructions: Longword aligned– 32Bit data paths– 7~8 stage pipeline

ALUExecute

Register FileOperandShifter

InstructionFetch1

WriteBack

StateExecute

PC

PC - 12

PC - 16

InstructionFetch2 PC - 4

InstructionDecode PC - 8

Data CacheAccess

Data CacheAccess

Data CacheWriteback

MultiplierStage1

MultiplierStage X

MultiplierStage2

F1

RF

X1

F2

ID

M1

M2

Mx

X2

XWB

DWB

D2

D1

MAC pipeline

Main executionpipeline

Memory pipeline

Embedded Linux

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Memory Map

Static Memory Interface (ROM, Flash, SRAM) 384 Mbytes

PCMCIA Interface 512 Mbytes

Memory Mapped registers Interface192 Mbytes

Dynamic Memory Interface 256 Mbytes

SDRAM Bank 3 (64 Mbytes)

SDRAM Bank 2 (64 Mbytes)

SDRAM Bank 1 (64 Mbytes)

SDRAM Bank 0 (64 Mbytes)

Memory Mapped registers (LCD)

PCMCIA/CF - Slot 1(256 Mbytes)

PCMCIA/CF - Slot 0(256 Mbytes)

Static Chip Select 3 (64 Mbytes)

Static Chip Select 2 (64 Mbytes)

Static Chip Select 1 (64 Mbytes)

Static Chip Select 0 (64 Mbytes)0h0000 0000

0h1000 0000

0h2000 0000

0h3000 0000

0h4000 0000

0hA000 0000

0h4400 0000

0h4800 0000

0h4C00 0000

0h0400 0000

0h0800 0000

0h0C00 0000

0h1800 0000

0hA800 0000

0hA400 0000

0hAC00 0000

0hB000 0000

Reserved (128 Mbytes)Static Chip Select 5 (64 Mbytes)

Static Chip Select 4 (64 Mbytes)0h1400

0000

Reserved (1280 Mbytes)

Memory Mapped registers (Memory Control)

Memory Mapped registers (Peripherals)

Reserved (1344 Mbytes)

0hFFFF FFFF

Embedded Linux

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PXA 255 Internal Register

• DMA controller• UART: Full function,

Bluetooth• I2C• I2S• AC97• UDC• UART: standard• ICP• RTC• OS timer• PWM0, PWM1• Interrupt Control• GPIO• Power Management & Reset

Control

• SSP• MMC Controller• Clocks Manager• Network SSP• Hardware UART• LCD Controller• Memory Controller

• Total : 21 fields• about 380 registers

Embedded Linux

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PXA 255 Functional diagram

Serial Channel 4(CODEC)

Serial Channel 0 (USB)

Serial Channel 1

Serial Channel 2 (IrDA)

Serial Channel 3 (UART)

Power Management

Clocks, Reset and Test

JTAG

UDC-

UDC+

RXD_1

TXD_1

RXD_2

TXD_2

RXD_3

TXD_3

TXD_C

RXD_C

SCLK_C

SFRM_C

BATT_FAULT

VDD_FAULT

PWR_EN

TCK_BYP

TESTCLK

PEXTAL

PXTAL

TEXTAL

TXTAL

nRESETnRESET_OUT

SMROM_ENROM_SEL

TCKTDI

TDO TMS

nTRST

L_DD(15:0)

L_FCLK

L_LCLK

L_PCLK

L_BIAS

GP(27:0)GPIO Ports

nCAS/ DQM(3:0)

SDCLK<2:0> SDCKE<1:0> nSDCAS

nSDRAS

RDY

nCS(5:0)

nWE

nOE

nRAS/ nSDCS(3:0)

LCD Control

Memory Control

RD/nWR Transceiver Control

nPOE

nPCE<2:1>

nPIOW nPIOR nPWE

VDD

nIOIS16 nPWAIT nPREG PSKTSEL

VSS/VSSX

VDDX

PCMCIA Bus Signals

Supply

A<25:0>

D<31:0> Data Bus

Address Bus

Intelⓡ XScale* PXA 250

[256-pins]

Embedded Linux

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PXA 255: Memory Model

Memory

CoreOn-chipCaches

MMU

Virtual AddressesPhysical Addresses

Buffers

MemoryController

Refer: http://www.intel.com/design/pca/prodbref/252780docs.htm

Embedded Linux

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PXA 255 BUS Read Operation

• Cache line fills read 8 words• Read allocate• Round robin replacement

XScaleCore

SystemMemory

PXA255

32KBI- Cache

MemoryController

32KBD-Cache

PC

Addr

32 bytes

Instruction

Data

Core Clock Half Core Clock

System BusExternal Bus

I-MMU

D-MMU

ReadBuffer

A[0:31]A[0:25]

D[0:31] D[0:31]

D[0:31]

D[0:31]

A[0:31]

A[0:31]

VA[0:31]

VA[0:31]

Instructions&

DataMemory

hit

hit

miss

miss

Embedded Linux

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PXA 255 BUS Writes

• No write to I-Cache• Write Back D-Cache• Software coherency needed between caches• Not write allocate

XScaleCore

PXA255

MemoryController

32KBD-Cache Addr

32 bytes

Data

Core Clock Half Core Clock

System BusExternal Bus

D-MMU

WriteBuffer

(8 entries)

A[0:31]A[0:25]

D[0:31] D[0:31]

D[0:31]

A[0:31] VA[0:31]

Data

Dirty Bits

SystemMemory

Embedded Linux

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PXA 255: Instruction Cache

• 32Kbytes Instruction Cache– 1,024 lines of 32 bytes(8 words)– Uses the virtual address– 32-way 32-set associative– Round-Robin replacement– Mapped via MMU page C-bits

• MMU - enable 경우 : memory management table 의 C-bit 에 의해서 제어

• MMU - disable 경우 : 모든 address 에 대하여 C=1• C=1 or MMU - disable 경우 : miss

– 8word 의 line fetch 가 수행이 되어 round-robin replacement에 의해서 cache bank 가 대치

• MMU - enable, C=0 경우 : virtual address 에 해당하는 외부 메모리에서 single word 를 읽어오고 , cache 에 쓰여지지 않음 .

Data

PC

Address

Instructions

IMMU

DMMU

32 KbyteI-cache

Main D-cache

Mini-D-cache

XScaleCore

Embedded Linux

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PXA 255 Data Cache

• 2 Data Caches: Main Data Cache, Mini Data Cache– Both: write back, read allocate, virtual– Mapped via MMU page B, C-bits

• Main Data Cache: 32KB– 32-way 32-set associative– Round-Robin replacement– B=1 & C=1

• Mini Data Cache: 2KB– 2-way set associative – Least Recently Used (LRU) replacement– B=0 & C=1

Data

PC

Address

Instructions

IMMU

DMMU

32 KbyteI-cache

Main D-cache

Mini-D-cache

XScaleCore

Embedded Linux

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PXA 255 Read Buffer

• PXA 255 Read Buffer• Data prefetcher

– saves processor waiting

– load & calculate in parallel

– for Read-Only data

– supplements the data cache

• Under software control

– Coprocessor 15, register #9

– 4 entries, 32 bytes each

– Loads of 1, 4, 8 words

– Replace or invalidate data

Data

PC

Address

Instructions

I-cache

D-cache&

mini-D-cache

XScaleCore

Write Buffer

128 byteReadBuffer

System Bus

Embedded Linux

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PXA 255 Memory Management

Virtual Addresses SpacePhysical Addresses Space

D-Cache

XScaleCore

SystemMemory

Instructions

Data

Descriptors

I-Cache

PXA255MMU

VAPAAC

VAPAACB

32

ITLB

DTLB

TLB Miss

Translation TableBase Register

Embedded Linux

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PXA 255 Coprocessor15

• CP15 Register transfer instructions

MCR P15, 0, Rd, CRn, CRm, Cop2

cond 1 1 1 0 CRm

31 28 27 2423 21 20 19 1615 12 11 8 7 5 4 3 0

0 0 0 CRn Rd 1 1 1 1 Cop2 1L

load from coprocessor/store to coprocessor

Embedded Linux

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PXA 255 CP15 Register structure

• CP15 Register structureRegister Purpose0 ID Register1 Control2 Translation Table Base3 Domain Access Control5 Fault Status6 Fault Address7 Cache Operations8 TLB Operations9 Read Buffer Operations10 TLB lockdown13 Process ID Mapping14 Debug Support15 Test & Clock Control4,11~12 UNUSED

Embedded Linux

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PXA 255 CP15 register

implementer revision

31 24 23 16 15 4 3 0

part number (BCD)0 0 0 0 0 0 0 AC0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M

31 15 1413 12 1110 9 8 7 6 5 4 3 2 1 0

I Z F R S B L D P W C AVRRC1

0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 14 13 0

translation table base address

D0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

D3 D2 D1D4D7 D6 D5D8D11 D10 D9D12D15 D14 D13

C2

C3

C5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 status

31 9 8 7 4 3 0

domain0

fault address

31 0

C6

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 2524 0

process IDC13

Embedded Linux

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Grouping of PXA 255 System Register

• System Control: clock manager, reset/power manager (CP14)

• System Integration: GPIO, interrupt, RTC, OS timer, PWM

• DMA Controller• Memory Controller• LCD Controller• SSPC• I2C bus unit• UARTs• Fast Infrared communication port• USB device controller• AC’97• I2S• Multimedia controller• NSSP• Hardware UART

Embedded Linux

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System Control Module of PXA 255

• Power management controller – Supporting normal, idle and sleep modes

• General purpose I/O ports: 80 ports– Generate FIQ, IRQ, “wakeup” interrupts

• Interrupt controller– Routes all system (GPIOs, LCD, Serial Channel) interrupts to

either IRQ or FIQ• Multi-channel DMA controller

– Software programmable to any serial port and LCD– Supporting External DMA

• Real time clock and timer – 32 bit counter/comparator– 32.7 kHz crystal: accuracy +/- 5 sec/month

• OS timer with alarm register – 32 bit counter/comparator– 3.68 MHz crystal: fine grain timing interrupts

Embedded Linux

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Running mode of PXA 255

SLEEPIDLE

Hardware Reset

RUN

Power on, nRESET asserted

nRESET assertednRESET asserted

nRESETnegated nRESET

asserted

Wait for interruptinstruction Force sleep bit set, or VDD

or battery fault pins asserted

System orperipheral unitinterrupt

GPIO or RTCalarm interrupt

VDD or battery fault pins assertedCPU clock held low, all otherresources active, wait for interrupt Wait for wake-up event

Embedded Linux

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Power and Battery Faults (1)

• Battery fault– Battery removed or dangerously low

• Power fault– VDD is lost or out of regulation– Caused by shorted PCMCIA card

• Intel® PXA255 sleep mode– During wakeup sequence if Batt_Fault or VDD_Fault

asserts

• Wakeup events ignore– if Batt_Fault asserted when Sleep results from a ‘fault’

state

• All wakeup sources are ignored besides GPIO[0,1]

Embedded Linux

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Power and Battery Faults (2)

• Idle: Low Power Modes– CPU halted but MEMC and peripherals running– Idle mode wakeup ~150uS – Interrupt or timer expiring exit device from Idle– If battery fault/power fault occur during Idle, Intel® PXA255

transitions to Sleep– No processor state lost : Program flow resumes where Idle mode

was entered• Sleep: Low Power Modes

– Power_EN pin negated by Intel® PXA255 to alert system to drive VDD to 0V

– Sleep entered when Batt_fault, Power_fault or Sleep bit asserted– CPU, MEMC, peripherals receive no clocks

• MEMC puts DRAM in self refresh state before fully entering sleep– Power consumed in Sleep < 50uA

• Must disable 3.68MHz oscillator. Wakeup time ~150mS– GPIO, timer expiring, peripheral causing interrupt can start

wakeup sequence

Embedded Linux

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Power and Battery Faults (3)

• Sleep : Low Power Modes

Embedded Linux

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Power Manager Control Register (PMCR)

• IDEA<0> (Imprecise Data Abort Enable) • 0 = nVDD_FAULT 또는 nBATT_FAULT 가 나타났을

때 Sleep mode 에 즉시 들어가는 것을 허용• 1 = nVDD_FAULT 또는 nBATT_FAULT 가 나타났을

때 sleep mode 에 들어가는 것을소프트웨어적으로 CPU 에 부정확한 data 정지 시그널을 강제적으로 인가

• PMCR register

0000 0000 0000 0000 0000 0000 0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

IDAE

Embedded Linux

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Power Manager General Configuration Register

• PCFR (Power Manager General Configuration Register)

– OPDE [0] 3.6864MHz oscillator power-down enable– FP [1] Float PCMCIA controls during Sleep Mode– FS [2] Float Static Chip Selects during Sleep Mode

0000 0000 0000 0000 0000 0000 0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPDE

FPFSReserved

Embedded Linux

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Clock

32.768K

RTC

32.768K

PWR_MGR

3.6864

PWM

3.6864

SSP

3.6864

GPIO

3.6864

OST

CPU

CORE

MEM

Controller

LCD

Controller

USB

47.923

FICP

47.923

12C

31.949

MMC

19.169

UARTs

14.746

AC97

12.288

12S

5.672

32.768

KHz

OSC

3.6864

MHz

OSC

/1 /112

100-400

MHz

PLL*

147.46

MHz

PLL

95.846

MHz

PLL

DMA /

Bridge

/M/2/4

/N

RETAINS POWER IN SLEEP PXbus

L

1 0 1

0

OSCC, OON

CCLKCFGcp14 c6.1 : turbo

CCCR

Embedded Linux

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Core PLL Output Frequencies

196ㅡ

398.1@1.3 V

298.6@1.1 v

398.1@1.3 V

427

165.9ㅡㅡ331.8@1.3 V

245

132.7ㅡㅡ265.4@1.1 V

236

66ㅡ

199.1@1.0 V

227

50298.6@1.1 v

199.1@1.0 V

ㅡ99.5@1.0 V

127

3.002.001.501.00(Run)

SDRAMmax Freq

MEM, LCD

Frequency

(MHz)

PXbusFrequen

cy

Turbo Mode Frequency (MHz) for Values “N” and Core Clock Configuration

Register (CCCR[15:0])Programming for Values of “N”:ML

36 1 132.7@1.0 V

ㅡ

ㅡ

ㅡ

ㅡ

ㅡ

ㅡ

99.5

99.5

165.9

132.7

132.7

99.5

99.5

99.5

83

66

66

99.5

99.5

Embedded Linux

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Core Clock Configuration Register(1)

• CCCR(Core Clock Configuration Register)

– N[9:7] Run Mode Frequency 에서 Turbo Mode Frequency 로 변환하기 위해서 곱하는 수 , Turbo Mode Freq. = Run Mode Frequency * N

000 , 001 , 101 , 111 – Reserved001(Multiplier) = 1011(Multiplier) = 1.5100 (Multiplier) = 2110 (Multiplier) = 3

– Hardware Reset , Watchdog Reset 이 되면 010 값이 default 가 된다 .– Turbo Mode Freq(398.1MHz) = Run Mode Freq(199.1MHz) * N(2)

0000 0000 0000 0000 0000 0001 0010 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LMNReserved

Embedded Linux

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Core Clock Configuration Register(2)

• M [6:5]: Memory Frequency 에서 Run Mode Frequency 로 변환하기 위해서 곱하는 수 Memory Freq = Crystal Frequency * L

00 , 11 – Reserved01(Multiplier) = 1(Multiplier 가 1 이면 Run Mode Freq

와 Memory Frequency 가 같다 .)

10(Multiplier) = 2(Multiplier 가 2 이면 Run Mode Freq가 Memory

Frequency 의 2 배가 된다 .)

• Hardware Reset , Watchdog Reset 이 되면 10 값이 default 가 된다 .

• Memory Freq(99.5MHz) = Crystal Frequency(3.6864MHz) * L(27)0000 0000 0000 0000 0000 0001 0010 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LMNReserved

Embedded Linux

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Core Clock Configuration Register(3)

• L<4:0>: Crystal Frequency 에서 Memory Frequency 로 변환하기위해서 곱하는 수 (3.6864MHz Crystal 을 사용 )00000 , 00110 to 11111 – Reserved00001(Multiplier) = 27 (Memory Freq 는 99.53MHz 가된다 .)00010(Multiplier) = 32 (Memory Freq 는 117.96MHz 가된다 .)00011(Multiplier) = 36 (Memory Freq 는 132.71MHz 가된다 .)00100(Multiplier) = 40 (Memory Freq 는 147.46MHz 가된다 .)00101(Multiplier) = 45 (Memory Freq 는 165.89MHz 가된다 .)

• Hardware Reset , Watchdog Reset 이 되면 00001 값이 default 가 된다 .

0000 0000 0000 0000 0000 0001 0010 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LMNReserved

Embedded Linux

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Clock Enable Register: CKEN

• CKEN0 [PWM0]• CKEN1 [PWM1]• CKEN2 [AC97]• CKEN3 [SSP]• CKEN4 [HWUART]• CKEN5 [STUART]• CKEN6 [FFUART]• CKEN7 [BTUART]• CKEN8 [I2S]• CKEN9 [NSSP]• CKEN11 [USB]• CKEN12 [MMC]• CKEN13 [FICP]• CKEN14 [I2C]• CKEN15 [LCD]

0000 0000 0000 0001 0111 1101 1110 1111

Reserved

CKEN0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CKEN1

CKEN2

CKEN3

r ese r ved

CKEN5

CKEN6

CKEN7

CKEN8

CKEN 11

CKEN 12

CKEN 13

CKEN 14

CKEN 16

r ese r ved

r ese r ved

r ese r ved

* All Unit Clock Enable Bit;

0 – Clock disable1 – Clock enable

Embedded Linux

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Oscillator Configuration Register: OSCC

0000 0000 0000 0000 0000 0000 0000 0000

Reserved

OO

K

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OO

N

• OSCC 는 32.768MHz Oscillator 의 Configuration 을 Control 하는 Register 이다 .• Oscillator 가 동작되었을때 안정화가 되는데는 10 초가 걸린다 . Oscillator 가 안정화 되면

OOK bit 가 1 로 set 된다 .OON [1] Write-once only bit

0 = 32.768MHz Oscillator 사용불가능이때 RTC 와 Power Manager 의 Clock 은 3.6863MHz

Oscillator 의값이 공급된다 .(112 로 나누어진 값 ) ☞ Page 3-3 의 Figure 3-1 Clocks Manager Block Diagram

참고1 = 32.768KHz Oscillator 사용가능이 비트는 Hardware Reset 으로만 Clear 가 된다 .

OOK [0] Read-only bit0 = OON bit 가 0 이거나 Oscillator 가 안정화 되지 않았을 경우1 = OON bit 가 1 로 set 되고 Oscillator 가 안정화 되었을 경우 RTC 와 Power Manager 의 Clock 은 32.768KHz Oscillator 의

Clock 을 사용이 비트는 Hardware Reset 으로만 Clear 가 된다 .

Embedded Linux

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General Purpose I/O

• GPIO[58:73] = dual panel color or 16 bit parallel input on LCD

• GPIO[23:27] = SPI if both synchronous serial protocols are required in a single system

• Modem control signals for UART (CTS, RTS, CD, etc) implemented via GPIO signals

• 4-5 GPIOs required for full PCMCIA support• 3 GPIOs required for Intel® SA-1111

Interface

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General Purpose I/O Block Diagram

Pin Direction Register(GPDR)

Alternate FunctionRegister(GAFR)

Pin Set Registers(GPSR)

Edge DetectStatus Register(GEDR)

Rising Edge DetectEnable Register(GRER)

Falling Edge DetectEnable Register(GFER)

EdgeDetect

Pin-LevelRegister(GPLR)

0

1Alternate Function(Output)

Alternate Function(Input)

Pin Clear Registers(GPCR)2

3

3210

Power ManagerSleep Wake-up

logic

2

0x40E0_000C/10/14

GPDR

1 : 출력0 : 입력

0x40E0_0054/58/5C0x40E0_0060/64/68

0x40E0_0060/64/68

0x40E0_0060/64/68

Base Address0x40E0_0000

0x40E0_0048/4C/50

0x40E0_0030/34/38

0x40E0_003C/40/44

0x40E0_0000/04/08

Embedded Linux

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Interrupt Controller

Interrupt Controller

Level Register(ICLR)

Interrupt Controller

Mask Register (ICMR)

Interrupt Source Bit

Interrupt Controller

Pending Register (ICPR)

Interrupt Controller

IRQ Pending Register (ICIP)

Interrupt ControllerFIQ Pending Register

(ICFP)

All Other Qualified

interrupt Bits

FIQ

IRQ

23 23

XScale CORE

CPSR.6(F)

CPSR.7(I)40D0 0000

40D0 0004

40D0 0008

40D0 000C

40D0 0010

40D0 0014 : Interrupt controller control register (ICCR) ICCR.0 : disable idle mask(DIM)

CCR[DIM]=0 &IDLE mode=‘1’

0 : IRQ

1 : FIQ

Embedded Linux

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Fault Switches

• Sleep Mode Test• External Voltage Regulator Requirements

PXA255

PWR_EN

VDD_FAULT

BATT_FAULT

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Target Board: RESET

• Processor Reset Circuit MAX811T• Voltage Monitor (3V~3.15 )• Manual Reset Input (Push button – “Low”)• Multi-ICE Reset • Reset Output to Flash

PXA255

RESET_IN

RESET_OUT

MR

RESET

MAX811T

31 5 7

J TAG_RST

J TAG PORT J 20

RESET

RESET

Embedded Linux

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Target Board: Flash Memory

• 3Volt Intel Strata Flash - 28F128• 32Bit Data Bus• Size : 32MByte -128Mbit (16Mbyte) * 2 EA• MSC0 : Static Chip Select 0 (Bank 0)• Base Address = 0x0000_0000

PXA255Memory

ControllerInterface

ADDR [10..23]

DATA [0..32]

Flash16Bit Low

Flash16Bit High

D[0..15]

D[16..31]

CS0

RESET

OE

Embedded Linux

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Target Board: Static RAM

• Samsung K6R4016V1C• 3Volt High-Speed CMOS Static RAM• 32Bit Data Bus / 1Mbyte• MSC1: Static Chip Select 3 (Bank 3)• Base Address = 0x0C00_0000

PXA255Memory

ControllerInterface

ADDR [10..23]

DATA [0..32]

SRAM16Bit Low

SRAM16Bit High

D[0..15]

D[16..31]

DQM[0..1]DQM[2..3]

CS3WEOE

Embedded Linux

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Target Board: SDRAM

• Samsung Synchronous DRAM - K4S561632• 32Bit Data Bus• 256Mbit - 4M x 16Bit x 4 Bank• Size : 64MByte -256Mbit (32Mbyte) * 2 EA• SDRAM Bank 0 - Dynamic Memory• Base Address = 0xA000_0000

PXA255Memory

ControllerInterface

ADDR [10..24]

DATA [0..32]

SDRAM16Bit Low

SRAM16Bit High

D[0..15]

D[16..31]

DQM[0..1]DQM[2..3]

nSDCS0

WERAS/CAS

SDCLK1/SDCKE1

Embedded Linux

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Target Board Circuit(1)

MMU

PXA250Core

PXA255

GP[27:0]

D[31:0]A[31:0]

GPIO

GPIO Registers GP[27:0]

Bridge

Interrupt Controller

ICIPICMRICLR

ICCRICFP

FIQ, IRQ

DMA

DMARegisters

LCD Controller

ADS 7843

Dynamic Memory Controller SDCKE[1]

SDCLK[1]SDCS[0]#SDRAS#

WE#SDCAS#

DQM[3:0]

MDCNFGMDCAS00MDREFR

LCD CON

LDD[15:0]L-FCLKL-LCLKL-PCLK

LCDControlRegisters

DCLKCS#DINBUSY

PENIRQ#DOUT

GP4

GP5GP26

X+X-

Y-Y+

Inverter Power

L-BIAS

E-PORT0[7:0] GP25E-PORT

GP23

E-PORT0 7

TFT LCD & Touch screen

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Target Board Circuit(2)

PXA255

D[15:0] D[15:0]

SOCKET 0

SOCKET 1

DIR OE#

DIR OE#

D[15:0]

GPIO(7)

GPIO(12)

CD1#CD2#

CD1#CD2#

RDY/BSY#

RDY/BSY#

GPIO(11)

GPIO(10)

PSKTSEL

nPIOR

nPOE

A(25:0)OE#WE#IOR#IOW#REG#

MA(25:0)nPOEnPWEnPIORnPIOWnPREG

A(25:0)OE#WE#IOR#IOW#REG#nPCE(1:2) CE(1:2)#

CE(1:2)#

nPWAIT

nPIOS16

WAIT# WAIT#

IOIS16#

IOIS16#

PCMCIA / CF

Embedded Linux

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Target Board: PS2 interface

• PS2 Keyboard / Mouse– Holtek HT6542B– 8Bit Data Bus– 8MHz Operating – Support PS/2 compatible mouse

HT6542B

KBCOKBCI

KBDOKBDI

MSCO

MSCI

MSDOMSDI MOUSE

KEYBOARD

DIR OE#

CS#

D(7:0)

PXA255

RD_nWR

nCS1nCS2

nCS3nCS4

DIR OE#

MD(31:0)

HT6542_CS

AddressDecoder

MA(25:0)nOE

nPWE

A0RD#WR#

DQ RESET#

KB_INT

MS_INT

GPIO(19)

GPIO(9)

Embedded Linux

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Target Board: Audio Codec

• Audio Codec– Cirrus Logic CS4202– AC’97 2.2 Compliant– 20-bit Stereo D/A Converters– 18-bit Stereo A/D Converters– MIC Input / Headphone Output

PXA255

AC’97 Controller

Unit(ACUNIT)

nACRESET

CS4202

AC’97 Primary CODEC

SDATA_OUT

SYNC(48 kHz)

SDATA_IN_0

BITCLK(12.288MHz

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Hardware overview

MMU

PXA255 Core

FTUART,BTUART

D[31:0]A[31:0]

PXA255

UTCR0UTCR1UTCR2

DB9

UTCR3

DTDRUTSR0UTSR1

USB

UDCCRUDCARUDCOMP

UDCCS2UDCD0UDCWC

FIQ, IRQ

USBCON

R

R

R

R

RFIQ, IRQ

Interrupt Controller

ICIPICMRICLR

ICCRICFP

FIQ, IRQ

Bridge

TX1RX1

TX3RX3

DMA

DMARegisters

MemoryController

MemoryControlRegisters

D+D-

473K

1.5K27.4

UDCIMPUDCCS0UDCCS1

UDCDRUDCSR

RS-232

Serial / USB Port

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Target Board: Ethernet LAN

• SMSC 10/100 Ethernet Single Chip LAN91C111• Internal 32bit Wide Data Path• 8Kbytes Internal Memory (Receive and Transmit FIFO

Buffers)• External 25MHz-output pin for an external PHY and MAC• MSC0, 1 : Static Chip Select 1,2 (Bank 1,2)• Base Address = 0x04000_0000 (primary)

0x0800_0000(secondary)PXA255

MD(31:0)

T/F

T/F

Primary Ethernet

Secondary Ethernet

ADDR (15:2)

D(31:0) D(31:0)

DIR OE#

Logic

nCS1nCS2nCS3nCS4

RD_nWR

nPWEnOE

MA(25:0)nDQM(3:0)

WE#OE#A(15:2)DQM(3:0)#

WE#OE#A(15:2)DQM(3:0)#

nCS1nCS2

GPIO(0)

GPIO(1)

INTR0INTR0

Embedded Linux

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Target Board: Push Switch

• 8bit Read [D0~D7] • Base Address = 0x1050_0000

PXA255

MemoryController

MD(7:0)

BUFFER

CS4

Address Decoder

MA(22:20)

G

+3.3V

Embedded Linux

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Target Board: Discrete LED

• 8Bit Write [ D0~D7 ]• Base Address = 0x1060_0000

PXA255

MemoryController

MD(7:0)

BUFFER

CS4

Address Decoder

MA(22:20)CK

Embedded Linux

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Target Board: 7 Segment LED

• 16Bit Write [ D0~D7 ] • Base Address = 0x1030_0000 [ Low 2 Segment ]

0x1040_0000 [ High 2 Segment ]

PXA255

MemoryController

MD(15:0) LATCH

CS4

Address Decoder

MA(22:20)

CK

CK

LATCH

DQ(7:0)

DQ(15:8)

DQ(7:0)

DQ(15:8)

Embedded Linux

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Target Board: Text LCD

• 8Bit Data Write [ D0~D7 ]• 3Bit Control Write [ D8~D10]• Base Address = 0x1060_0000• 20 Characters x 2 Lines / Backlight Type

PXA255

MemoryController

MD(15:0) LATCH

CS4

Address Decoder

MA(22:20)

CK

LATCH

Character LCD Module

+5V

VD

D(7:0)DQ(7:0)

RSRW

E

DQ(8)

DQ(9)DQ(10)