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Chapter 11. Operational-Amplifier Circuits

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1. Introduction

2. The Two-Stage CMOS Op Amp

3. The Folded-Cascode CMOS Op Amp

4. The 741 Op-Amp Circuit

5. DC Analysis of the 741

6. Small-Signal Analysis of the 741

7. Gain, Frequency Response, and Slew Rate of the 741

8. Modern Techniques for the Design of BJT Op Amps

Contents

EMLAB

3Introduction

1. CMOS 및 bipolar op-amp 에 대해 알아봄 .

2. CMOS op-amp 는 독립적인 용도 외에 IC 의 구성 block 으로 사용됨 .

3. CMOS op-amp 가 sub-system 인 경우 • chip-terminal 에 연결할 필요가 없어서 output stage 가 필요 없는

경우 많음 .

• 정전기로부터 보호할 필요가 없어서 단자에 clamping diode 붙일 필요가 없음 .

4. 범용 용도로는 bipolar op-amp 가 흔히 쓰임

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41. The Two-Stage CMOS Op Amp

Figure 11.1 The basic two-stage CMOS op-amp configuration.

Frequency com-pensation

5

4

7

6

)/(

)/(2

)/(

)/(

LW

LW

LW

LW

Output DC offset = 0

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Figure 11.2 Small-signal equivalent circuit for the op amp in Fig. 11.1.

11

1211

2

OVOV

Dmmm V

I

V

IggG

2/

||||,

2/

||||,|| 4

4

44

2

2

22421 I

V

I

Vr

I

V

I

VrrrR A

D

Ao

A

D

Aooo

)||( 421111 oomm rrgRGA

6

662

2

OV

Dmm V

IgG

762 || oo rrR

)||( 766222 oomm rrgRGA

1.3 Voltage Gain

)||()||( 766421221121 oomoommm rrgrrgRGRGAAA

Mid band gain

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61.4 Common-Mode Rejection Ratio (CMRR)

]2)][||([ 3421 SSmoom RgrrgCMRR

The CMRR of the two-stage op amp of Fig. 11.1 is determined by the first stage.

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D2 D6

0)( 2211

21 oiCi

iidm VVsCVsC

R

VVGD2 node :

0)( 222

22 ioCoo

im VVsCVsCR

VVGD6 node :

2121212

212122211

2121

)]([)]([1

)(

RRCCCCCsRRRRGCRCRCs

RRsCGG

V

V

CmC

Cmm

id

o

1.5 Frequency Response

644221 gsdbgddbgd CCCCCC

Lgddbdb CCCCC 7762

C

mZ C

G 2

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21

2

121

2

2121

111

111)(PPPPPPPPP

ssss

sssD

212

222211

2121222111

1

)()]1([

1

)(

1

RRGC

CCRRGCCR

RRRRGCRCRC

mC

CmC

mCP

Miller’s effect

2

2

2121

22 )( C

G

CCCCC

CG m

C

CmP

Cmp CRGRf

2211 2

1

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9Simplified equivalent circuit

C

mZ C

G 2

Cmp CRGR 221

1

1

2

22 C

GmP

21

11

)(

PP

m

ss

AsA

C

mPmt C

GA 1

1

안정도를 위해 ft 가 fP2, fZ 보다 작아야 함 .

21

2

212

2

2

22

1 ,,

mmZt

m

C

mPt

C

mZ

mP

C

mt

GG

C

G

C

G

C

G

C

G

C

G

Gain bandwidth product

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101.6 Slew rate (SR)

• 입력 전압이 큰 경우 differential pair 중 트랜지스터 1 개는 완전히 꺼지고 전류는 나머지 한쪽으로만 흐르게 됨 .

• Q4 는 saturation 되어 0 V 에 가깝고 current source 와 등가가 됨 .

• 이 경우 op-amp 는 이상적인 적분기로 모델링 가능

• 안정도를 위해 붙인 CC 로 인해 출력 전압이 증가하는 속도가 제한됨 .

tC

It

Co )(

CC

ISR

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11Relationship Between SR and ft

OVtm

tOVm

C

Vfg

fVg

C

ISR

22

11

OVOVmm V

I

V

I

gG

22

11

C

mt C

Gf

21

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122. The Folded-cascode CMOS Op Amp

• 전압 이득을 더욱 올리고 , 주파수 대역폭을 늘리기 위해 cascode 증폭기 형태로 만듦 .

• 증가된 cascode 증폭기의 출력 임피던스에 병렬로 연결되는 current mir-ror 의 출력 임피던스도 증가시켜야 함 .

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Figure 10.9 A more complete circuit for the folded-cascode CMOS am-plifier of Fig. 10.8.

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142.6 Increasing the Input Common-Mode Range: Rail-to-Rail Input Operation

idomo VRGV 2 omRGA 2

Q1, Q2, Q3, Q4 모두 on 일 때

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153. The 741 Op-Amp Circuit

Short circuit protec-tion circuit

Class AB output stage

DC bias circuit

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164. DC Analysis of the 741

5

1112 )(

R

VVVVI EEBEEBCCREF

][73.0],[15 1112 mAIVVVVV REFBEEBEECC

4.1 Reference bias current

4.2 Input stage bias

][19ln 1041010

4101011 AIRII

IVRIVV CC

C

REFTCBEBE

Widlar current source

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IIIII EECC 2121

PC

II

/21

29

IIC 210

][5.94321 AIIII CCCC

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IIIIIII CCCCCC 654365

3

277

2

R

IRVIII BE

NEC

STBE I

IVV ln6

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194.6 Second-Stage Bias

][618.0ln 1717 V

I

IVV

S

CTBE

9

17817171616 R

VRIIII BEEBEC

AIC 55017

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204.7 Output-Stage Bias

][18025.02323 AIII REFEC

][1651518018 AIE

][8.151919 AII EC

][530ln 1919 mV

I

IVV

S

CTBE

][118.11918 VVVV BEBEBB

14

14

20

20

14

14 ln2lnlnS

CT

S

CT

S

CTBB I

IV

I

IV

I

IVV

][154][103 201414

2014 AIIAII CCSS

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215. Small-Signal Analysis of the 741

5.1 The Input Stage

e

ie ri

4

][1.2)1(4 MrR eNid

eo ii 2

ei

om r

iG

21

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Output resistance

)]||(1[ rRgrR emoo Output resistance formula for Common base amp. :

][7.6|| 641 MRRR ooo

Figure 10.21 Small-signal equivalent circuit for the input stage of the 741 op amp.

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235.2 The Second Stage

]/[5.62 AmVGm

][4)]})(1(||[){1( 81717916162 MRrRrR eei

))(1(

)||(

)||(

8171717

16179

179217

817

1717

RrR

rRR

RR

Rri

ei

ei

iib

e

bc

][81|| 17132 kRRR oBoo

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Figure 10.31 Cascading the small-signal equivalent circuits of the individual stages for the evaluation of the overall voltage gain.

6.1 Small-Signal Gain of 741

outL

Lomiom

o

o

i

o

i

i

i

o

RR

RGRGRRG

o

3))(||( 22211

22

22

][7.107]/[147,24397.0)5.526(1.4760 dBVVAi

o