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Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo de Projeto de Sistemas Eletrônicos e Software Aplicado Laboratório de Microeletrônica – LME Depto. Sistemas Eletrônicos Universidade de São Paulo

Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

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Page 1: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Logic Synthesis in IC Design and Associated Tools

Sequential Synthesis

Wang Jiang Chau

Grupo de Projeto de Sistemas Eletrônicos e Software Aplicado

Laboratório de Microeletrônica – LMEDepto. Sistemas EletrônicosUniversidade de São Paulo

Page 2: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Defined by the quintuple (, , S, , ). A set of primary inputs patterns . A set of primary outputs patterns . A set of states S. A state transition function

: S S. An output function

: S for Mealy models : S for Moore models.

Defined by the quintuple (, , S, , ). A set of primary inputs patterns . A set of primary outputs patterns . A set of states S. A state transition function

: S S. An output function

: S for Mealy models : S for Moore models.

Finite-State Machine Model

Page 3: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Sequential Logic Synthesis

Finite-State Machine F(X,Y,Z, , ) as State Transition Graph (STG):

Circuit composed of : Combinational logic for and Set of registers (flip-flops) D

D

XX YY

State Minimization

State Encoding

Page 4: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

State Minimization

Aims at reducing the number of machine states reduces the size of transition table.

State reduction may reduce the number of storage elements. the combinational logic due to reduction in transitions

Completely specified finite-state machines No don't care conditions. Easy to solve.

Incompletely specified finite-state machines Unspecified transitions and/or outputs. Intractable problem.

Page 5: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

State Minimization for Completely-Specified FSMs

Equivalent states Given any input sequence the corresponding output

sequences match. Theorem: Two states are equivalent iff

they lead to identical outputs and their next-states are equivalent.

Equivalence is transitive Partition states into equivalence classes. Minimum finite-state machine is unique.

Page 6: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Applicable input sequences All transitions are specified. Does not lead to any unspecified transition.

Compatible states Given any applicable input sequence the

corresponding output sequences match. Theorem: Two states are compatible iff

they lead to identical outputs (when both are specified),

their next-states are compatible (when both are specified).

Compatibility is not an equivalency relation (not transitive).

Applicable input sequences All transitions are specified. Does not lead to any unspecified transition.

Compatible states Given any applicable input sequence the

corresponding output sequences match. Theorem: Two states are compatible iff

they lead to identical outputs (when both are specified),

their next-states are compatible (when both are specified).

Compatibility is not an equivalency relation (not transitive).

State Minimization for Incompletely-Specified FSMs

Page 7: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

State Encoding of Finite-State Machines- 1

aka state assignment Given a (minimum) state table of a finite-state machine

Find a consistent encoding of the states with one unique code to each state that preserves the cover minimality with minimum number of bits. with minimum delay (hard- usually neglected)

The state set must be encoded while satisfying simultaneously both input and output constraints.

Given s states, the number of coding bits is log2s b s The minimality depends on the combinational logic

implementation (2-level? Multi-level?)

Page 8: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

State Encoding Aimed to 2-Level Traditional PLA solution, checking dependencies (outputs and

next state signas) w.r.t. inputs and present state signals Maximize number of common cubes betwwen covers. State

Transition Table (STT)

PSNS

x=0 x=1z

x=0 x=1

A A D 0 1

B A C 0 0

C C B 0 0

D C A 0 1

y1y2Y1Y2

x=0 x=1z

x=0 x=1

A00 00 10 0 1

B01 00 11 0 0

C11 11 01 0 0

D10 11 00 0 1

y1y2Y1Y2

x=0 x=1z

x=0 x=1

A00 00 11 0 1

B01 00 10 0 0

C10 10 01 0 0

D11 10 00 0 1

Y1=x´y1+ xy1´

Y2=x´y1+ xy2

z= xy2 ´

Y1=x´y1+ xy1´

Y2= xy2 ´

z= x y1´ y2 ´ + xy1y2

Transition/Output Table (TOT) Transition/Output Table (TOT)

Page 9: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Mustang Algorithm

State encoding for multilvel logic Developed in UC Berkeley upon MIS Motivation: traditional state encoding for

PLAs brings sub-optimal results when applied to multilevel logic

STG ou

STT

Transition/Output Table

Two-Level Format

Multilevel Format

Encoder for PLAs

Mustang

Sub-optimal

Optimal

Optimal

Sub-optimal

Page 10: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Traditional Encoding for PLA

6 cubes

16 gates

13 intermediate literals

Page 11: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Traditional Encoding for Multilevel

7 cubes

15 gates

12 intermediate literals

Page 12: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Mustang State Encoding

Logic network representation. Area: # of literals. Encoding based on cube-extraction heuristics Rationale

When two (or more) states have a transition to the same next-state

Keep the distance of their encoding short. Extract a large common cube.

When two (or more) states have a transition from the same next-state

Keep the distance of their encoding short (wishing common 1´s). Extract a large common cube.

Page 13: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Example- 1

2-input, 5-state FSM (3-bits). s1 s3 with input i1i2’ s2 s3 with input i1’i2.

Encoding s1 000 = a’b’c’. s2 001 = a’b’c s3 110 the common-cube refers to A and B.

Transition A = B = i1i2’ a’b’c’ + i1’i2 a’b’c = a’b’ (i1i2’ c+

i1’i2 c’) 8 literals instead of 10.

For Nb: number of bitsNd: Hamming distance

(Nb-Nd)=3-1=2 is the number of common literals

Page 14: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

2-input, 5-state FSM (3-bits). s3 s1 with input i1i2’. s3 s2 with input i1’i2.

Encoding s1 011 s2 001 s3 110 = abc’

Transition C= i1i2’abc’ + i1’i2abc’ = abc’ (i1i2’ + i1’i2) 7 literals instead of 10.

Example- 2

the common-cube refers to C

For Nb: number of bitsNd: Hamming distance

(Nb-Nd)=3-1=2 is the number of terms with common cubes

Page 15: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Mustang Algorithm Approach

Constructin Graph (V, Em, W(Em)), where V- set of vertices. Each vertex represent a state Em- set of arcs connecting vertices (states). Each

connection represent the relationship between two states and their coding

W(Em) –weigths of arcs. The weigth is the gain associated to each two states, assuming their enconding is close (with low Hamming distance)

The weight carries different meanings depending if the proximity in encoding refers to the present states (example 1) or next states (example 2)

Page 16: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Mustang Algorithm Implementation- 1 • Fanout-oriented algorithm

– Consider state fanout i.e. next states and outputs.– Assign closer codes to pair of states that have same next state

transition or same output.– Maximize the size of the most frequent common cubes.

Weight Em between to states k and l given as MPk,l

Average(divide by 2): we do not know how many 1s ´there exist in the next state

Page 17: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Example- 1

For the only output (i=1) State s=0 to 3 (st0 to st3):

PO0,1 =0; PO

1,1 =2; PO2,1 =3; PO

3,1 =2 For the next states s=0 to 3 (st0 to st3):

Next state s0; present state s=0 to 3 (st0 to st3):Ps

0,s0 =2; Ps1,s0 =1; Ps

2,s0 =0; Ps3,s0 =0

Next state s1; present state s=0 to 3 (st0 to st3):Ps

0,s1 =1; Ps1,s1 =1; Ps

2,s1 =1; Ps3,s1 =0

Next state s2; present state s=0 to 3 (st0 to st3):Ps

0,s2 =0; Ps1,s2 =1; Ps

2,s2 =1; Ps3,s2 =1

Next state s3; present state s=0 to 3 (st0 to st3):Ps

0,s3 =0; Ps1,s3 =0; Ps

2,s3 =1; Ps3,s3 =1

Page 18: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Example- 2

Page 19: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Mustang Algorithm Implementation- 2 • Fanin-oriented algorithm

– Consider state fan-in i.e. present states and inputs.– Assign closer codes to pair of states that have transition from

same present state or same input.– Maximize the frequency of the largest common cubes.

k state ofequation in i state of ocurrences ofnumber :

k state ofequation in iinput of ocurrences ofnumber :

k state ofequation in iinput of ocurrences ofnumber :

)*(*)*()*(

s,

,

,

1

s,

s,,,,1 ,,

ik

OFFik

ONik

ns

i ilikbOFFil

OFFik

ONil

ni

i

ONiklk

P

P

P

PPnPPPPM

Page 20: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Example- 1

For the inputs (i=1 to 2) Input i1; next states=0 to 3 (st0 to st3):

PON0,1 =2; PON

1,1 =0; PON2,1 =3; PON

3,1 =0POFF

0,1 =0; POFF1,1 =3; POFF

2,1 =0; POFF3,1 =2

Input i2; next states=0 to 3 (st0 to st3):PON

0,2 =2; PON1,2 =1; PON

2,2 =1; PON3,2 =1

POFF0,2 =1; POFF

1,2 =1; POFF2,2 =1; POFF

3,2 =0 For the next states s=0 to 3 (st0 to st3):

Present state s0; next state s=0 to 3 (st0 to st3):Ps

0,s0 =2; Ps1,s0 =1; Ps

2,s0 =0; Ps3,s0 =0

Present state s1; next state s=0 to 3 (st0 to st3):Ps

0,s1 =1; Ps1,s1 =1; Ps

2,s1 =1; Ps3,s1 =0

Present state s2; next t state s=0 to 3 (st0 to st3):Ps

0,s2 =0; Ps1,s2 =1; Ps

2,s2 =1; Ps3,s2 =1

Present state s3; next state s=0 to 3 (st0 to st3):Ps

0,s3 =0; Ps1,s3 =0; Ps

2,s3 =1; Ps3,s3 =1

Page 21: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Example- 2

Page 22: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Algorithm- Graph Embedding

• Examine all state pairs– Complete graph with |V| = |S|.

• Add weight on edges– Model desired code proximity.– The higher the weight the lower the distance.

• Embed graph in the Boolean space.– Objective is to minimize the cost function

• Difficulties– The number of occurrences of common factors depends on the next-

state encoding.– The extraction of common cubes interact with each other.

),(*),(1 1

jij

N

i

N

iji vvDistvvWeight

s s

Page 23: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Algorithm- simplified

• Choose one node vi such that

is maximu

where vj are adjacent nodes to vi.

• Code vi and and assign shortest distance codes to vj .

• Repeat until all graph is assigned.

),(1

j

N

ji vvWeight

b

Page 24: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Example

8),(3

10

j

jvvWeight

For 5 states, Nb=3

11),(3

11

j

jvvWeight

11),(3

12

j

jvvWeight

12),(3

13

j

jvvWeight

7),(3

14

j

jvvWeight

Page 25: Escola Politécnica da Universidade de São Paulo GSEIS - LME Logic Synthesis in IC Design and Associated Tools Sequential Synthesis Wang Jiang Chau Grupo

Escola Politécnica da Universidade de São Paulo

GSEIS - LME

Results