ESDESD

충북대학교 전자정보대학 김영석

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ElectroStatic Charge GenerationWhen 2 Surfaces in Contact then Separate

Some Atom Electrons Move Causing Imbalance

One Surface Has Positive Charge & One Surface Has Negative ChargeCharge

d t

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www.esdsystems.com

전자정보대학 김영석

ESD TheoryTriboelectric(마찰전기) charging happens when 2 materials come in contact and then separated

An ESD event occurs when the stored charge is discharged

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ESD ExamplesLightning

Zap from a Door

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ElectroStatic DischargeCharges Seek Balance

Discharge is Rapid

Creating Heat

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Two Types of Materials: ConductorsElectrical Current Flows Easily

So Can be Grounded

Can Discharge

E les: Met ls d Pe leExamples: Metals and People

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Two Types of Materials: InsulatorsElectrical Current Does Not Flow Easily

Cannot be Grounded

Example: Plastics

T i ll hi h h iTypically very high charging

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Static VoltagesWalking across a carpet: 1,500 - 35,000 volts

Walking over untreated vinyl floor: 250 - 12,000 volts

Vinyl envelope used for work instructions: 600 - 7,000 volts

W k t b h 700 6 000 ltWorker at a bench: 700 - 6,000 volts

Unwinding regular tape: 9,000 - 15,000 volts

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Electronic Component ESD SensitivityPeople Discharge Frequently

But To feel a Discharge it must be about 3,000 volts

H B d M d l(HBM)Human Body Model(HBM)

ESD Class 0: Damage you can’t feel: 0 to 199 Volts

ESD Class 1: Damage you can’t feel: 200 to 1,999 VoltsESD Class 1: Damage you can t feel: 2 to 1,999 Volts

ESD Class 2: Damage you might feel: 2,000 to 3,999 Volts

ESD Class 3: Damage you can probably detect as spark with your own body: 4,000 to 15,999 Volts

ESD That A Person Can’t Feel Can Easily Damage ElectronicESD That A Person Can t Feel Can Easily Damage Electronic Components

100 volts or less can damage components

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ESD Test MethodsHuman Body Model (HBM)

Representative of an ESD event between a Human and an Electronic ComponentComponent

Machine Model (MM)

Simulates the ESD event when a Charged Machine discharges through a componentcomponent

Charged Device Model(CDM)

When the component is charged and then discharges through a Pin. The Substrate becomes charged andSubstrate becomes charged and discharges through a Pin

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Human Body Model(HBM)

Human Body Model (HBM)Human Body Model (HBM) Human Body Model (HBM) consists of a Capacitor and a series Resistor: C =100pf, R=1500 Ohm (JEDEC JESD 22-A114 [2])Requirements 2 - 4 kVoltsRequirements 2 - 4 kVoltsPositive or negative discharge between any two pins

VHBM DUTR = 1.5 KΩ

C = 100 pF

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Human Body Model(HBM) Waveform

Human Body Model (HBM) Waveform10ns rise time typically (short)• 2-10ns are allowed

Peak current: • Rule of Thumb: 1kV = 2/3 Ampere

ipeak = VHBM/1500 1kV

i(t)

timet r= 2-10 nsec

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Machine Model(MM)

Machine Model(MM)Machine Model(MM)Machine Model (MM) consists of a Capacitor and no series Resistor: C=200pF (JEDEC JESD 22-A115 [11])[Phili St d d C 2 F R 1 25 Oh L 75 2 5 H ][Philips Standard: C=200 pF, R=10-25 Ohm, L=0.75-2.5µH ]Requirements 200 - 400 VoltsPositive or negative discharge between any two pins

V DUT

L = 0.5 - 0.75 μH

VMM DUT

C 200 F

R < 8.5 Ω

C = 200 pF

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Machine Model(MM) WaveformsMachine Model(MM) Waveform

stress is similar to HBM

Oscillations due to setup parasitics

MM d HBM f il d i iliMM and HBM failure modes are similiar

Less reproducible than HBM

VESD=0.1kV, Ipeak= 1.5 - 2.0AVESD .1kV, Ipeak 1.5 2. A

VESD=0.2kV, Ipeak= 2.8 - 3.8A

VESD=0.3kV, Ipeak= 5.8 - 8.0A

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Charged Device Model(CDM)Charged Device Model(CDM)

Models an ESD event which occurs when a device acquires electrostatic charge and then touches a grounded object

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Charged Device Model(CDM) WaveformCDM Waveform: Highly dependent on die size and package capacitance

500V with 4pF verification module

t <400psec I ~4 5A (Source: AEC Q100 011B)tr<400psec, Ip1~4.5A (Source: AEC-Q100-011B)

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ESD Protection SchemePrimary + Isolation + Secondary Element

Primary Element(PE)

Shunt All of Current during an ESD Event

FOD(Fi ld O id D i ) SCR NMOS PN Di dFOD(Field Oxide Device), SCR, NMOS, PN Diode

Effectiveness of PE is determined by the SE

IsolationIsolation

Resistive Element

Polysilicon, N+ Diffusion, N-well, Zener Diode

Secondary Element(SE)

Limit the Voltage or Current until the PD is Fully Operational

S ll G d d G t MOS Di dSmall Grounded Gate MOS, Diode

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ESD Protection Devices

Non-breakdown BasedDiodesBJT(Bipolar Junction Transistor)BJT(Bipolar Junction Transistor)MOSFET

Breakdown Based

Area Efficient, But Hard to Design/predictTFO(Thick Field Oxide)TFO(Thick Field Oxide)SCR(Silicon Controlled Rectifier)PIPE(Punchthrough Induced Protection Element)LVSCR(Low Voltage SCR)LVSCR(Low Voltage SCR)Gate SCR(Gate Coupled SCR)GCNMOST(Gate Coupled NMOS)Bi d l SCRBimodal SCRSpark Gap

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BJT under ESD Conditions

Two OperationsTwo Operations

1) Self-Triggering OperationB-C Reverse Bias => Breakdown (Bvcbo)=> Avalanche G ti f C iGeneration of CarriersElectrons enter the Collector (Ic) Holes drift to the Base => B-E Forward BiasI-V Curve: Vt1, It1=Snap Trigger Voltage, CurrentVsp=Snap Hold Voltage

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BJT under ESD Conditions

2) External Triggering OperationUsing External Current SourceLow VCB Voltage << BvcboLow VCB Voltage << BvcboVt1(External trigger) < Vt1(Self trigger): Desirable in ESD protection

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MOSFET under ESD ConditionsThin Gate Oxides => Low Clamping Voltage

Triggering by Parasitic Lateral BJT

VD Increase => Avalanche, Electron-Hole Pair Generation

El t t th D i (ID)Electrons go to the Drain (ID)

Holes go to the Substrate (Base) (Isub)

Isub => Forward Bias of B-E Junction of npn BJT (Vt1, It1)Isub > Forward Bias of B E Junction of npn BJT (Vt1, It1)

Electron Injection into the Substrate (Base) => VD Decrease, - Res

Vsp 이후: Conduction Modulation of Substrate

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SCR(Silicon Controlled Rectifier)

SCR(Silicon Controlled Rectifier) =Thyristor = PNP + NPN BJTsSCR(Silicon Controlled Rectifier) =Thyristor = PNP + NPN BJTs

Anode=+ , Cathode=GND => Reverse Bias n-well/p-well Junction

=> Avalanche Breakdown,

=> Electron to n-well (turn on pnp) Bias , Holes to p-well (turn on npn)

Vh ~ 2 5V Vt ~ 20VVh ~ 2-5V, Vt ~ 20V

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SCR

Vtrigger (~20v) Reduction

Desirable in ESD Protection

N+ Diffusion in n-well edge : Vt ~ 15v

Gate Oxide at n-well edge: Vt ~ 6-10V

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Field Oxide Device(FOD)Thick Field Device, or FOD

Feature Sizes from 3um to 1um

Lateral BJT: Breakdown at the Drain Junction

D i S i (DS) Ch l L th(L) C iti l P tDrain Spacing(DS), Channel Length(L): Critical Parameters

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FOD: Vt ReductionTrigger Voltage (Vt) Reduction

(a) FOD without Gate

(b) FOD with Metal Gate Shorted to the Drain

( ) FOD i P l ili G t(c) FOD using Polysilicon Gate

Vt(a) > Vt(b) > Vt(c)

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FOD: Design Parameters

Trigger Voltage(Vt) vs Channel Length(L)

Failure Voltage(HBM) vs Drain Spacing(DS)

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FOD: Layout

DS/ L: Critical

DS’/GR: Not Critical

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NMOS (FPD)NMOS or FPD(Field-Plated Diode) or Gated-Diode

FPD: Thin Oxide Devices (FOD: Thick Oxide Device)

Good for Feature Size < 1um (FOD: 1um<L<3um)

G t Ti d t th G dGate Tied to the Ground

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FPD: PerformanceFeature Size Dependency

L>1um: Thick Oxide Device (FOD) is Better

L<1um: Thin Oxide Device (FPD) is Better

Sili id /N Sili id dSilicide/Non-Silicided

Non-Silicided is Better

DCG(Drain Contact to Gate) DependencyDCG(Drain Contact to Gate) Dependency

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FPD: SummaryGood for Submicron Device

W ~ 200um

L ~ Minimum Channel Length

D i C t t t G t 6Drain Contact to Gate ~ 6um

Finger Length ~ 40 – 80um

Number of Finger ~ 2 -3Number of Finger 2 3

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Gate-Coupled NMOS(GCNMOS)VG>VTH for GCNMOS (VG=0 for FOD/FPD)

Merits

Lower Trigger Voltage (Vt)

U if T f All Fi (VG 0 N if T > ESDUniform Turn-on of All Fingers (VG=0: Nonuniform Turn-on => ESD Failure)

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GCNMOS: VG DependencyGate Coupling : Lower the Avalanche Breakdown Voltage Vbr

Vbr Minimum for VG ~ 1-2V

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GCNMOS with FODGate of GCNMOS is connected to Ground Through the FOD

NPN(GCNMOS) Turn-on, Vpad ~ 8V

NPN Snapback, Vpad ~ 15V, I ~ 2A (R ~ 5Ohm)

T FODTurn-on FOD

Discharge VG=0

Tr ~ 5-10ns: Enough for All the Fingers to Turn-onTr 5 1 ns: Enough for All the Fingers to Turn on

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GCNMOS with FOD: PerformanceTrigger Voltage (Gate Coupled) < Trigger Voltage (VG=0)

Failure Voltage (Gate Coupled) > Failure Voltage (VG=0)

All the Fingers are Turned-on (See Inset of the Fig)

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SCRMost Efficient/unit Area

SCR Action

N-well/P-sub is Highly Reverse Biased =>Avalanche Breakdown

El t C t t N ll > E/B (P+ A d /N ll) F dElectron Current to N-well => E/B (P+ Anode/N-well) Forward Biased. Turn-on PNP in 1ns

Holes from Emitter go to P-sub => Turn-on NPNg

Regenerative PNPN Action

Low Impedance State: Vanode-cathode ~ 1-2V => Low Power Di i ti I d ESD P fDissipation, Improved ESD Performace

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SCR: Trigger VoltageMain Design Parameter for Vt

Spacing bet. Anode and N-well (X)

P-sub Resistance (Rp)

T i ll Vt 40 100VTypically, Vt ~ 40-100V

Vt ~ 60-70V/um in Nonsalicided Process

Vt ~ 40-50V/um in Salicided ProcessVt 4 5 V/um in Salicided Process

Higher Rp => Lower Vt

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SCR: VT Reduction1) MLSCR(Modified Lateral SCR)

Include Highly Doped Region near the Surface

Vt ~ 25V

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SCR: VT Reduction2) LVTSCR(Low Voltage Trigger SCR)

MOS // SCR

Avalanche in Drain Junction of MOS

H l i th S b t t T NPNHoles in the Substrate Turn-on NPN

Electron Current (from N+ source) goes to N-well, Turn-on PNP

Vt ~ 12-15Vt 12 15

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References

Basic ESD and I/O Design, S. Dabral and T. J. Maloney, Wiley, 1998g y y

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