FULLY-DEPLETED SOI CMOS CIRCUITS AND TECHNOLOGY FOR ULTRALOW-POWER APPLICATIONS

Fully-Depleted SOI CMOS Circuitsand Technology for Ultralow-PowerApplications

by

TAKAYASU SAKURAIUniversity of Tokyo, Japan

AKIRA MATSUZAWATokyo Institute of Technology,Tokyo, Japan

and

TAKAKUNI DOUSEKINTT MicroSystem Integration Labs.,Kanagawa, Japan

A C.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN-10 0-387-29217-9 (HB)ISBN-13 978-0-387-29217-5 (HB)ISBN-10 0-387-29218-7 (e-book)ISBN-13 978-0-387-29218-2 (e-book)

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© 2006

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CONTENTS List of Contributors ..............................................................................xi Preface ...............................................................................xiii 1. Introduction .........................................................................................1 1.1 Why SOI? ..................................................................................1 1.2 What is SOI? — Structure — ..................................................2 1.3 Advantages of SOI ......................................................................4 1.4 History of the Development of SOI Technology.........................8 1.5 Partially-Depleted (PD) and Fully-Depleted (FD) SOI MOSFETs, and Future MOSFETs.............................................16 1.6 Summary ...................................................................................19

References .................................................................................20 2. FD-SOI Device and Process Technologies......................................23 2.1 Introduction ...............................................................................23 2.2 FD-SOI Devices ........................................................................24 2.2.1 Basic Features of SOI Devices ......................................24 2.2.2 Operating Modes of SOI MOSFETs .............................28 2.2.3 Basic Characteristics of FD- and PD-SOI MOSFETs ...32

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2.3 Theoretical Basis of FD-SOI Device Operation: DC Operation ............................................................................48 2.3.1 Subthreshold Characteristics .........................................48 2.3.2 Post-threshold Characteristics .......................................53 2.3.3 Short-Channel Effects ...................................................57 2.4 FD-SOI CMOS Process Technology.........................................58 2.4.1 Fabrication Process for FD-SOI CMOS Devices ..........58 2.4.2 Problems and Solutions in FD-SOI Process Technology ....................................................................62 2.5 Summary ...................................................................................76 References .................................................................................77 3. Ultralow-Power Circuit Design with FD-SOI Devices .................83 3.1 Introduction ...............................................................................83 3.2 Ultralow-Power Short-Range Wireless Systems .......................84 3.3 Key Design Factor for Ultralow-Power LSIs............................86 3.4 Ultralow-Voltage Digital-Circuit Design ..................................89 3.4.1 Key Technologies ..........................................................89 3.4.2 Estimation of Energy Reduction ...................................93 3.5 Robustness of Ultralow-Voltage Operation...............................98 3.5.1 Suppression of Floating-Body Effects...........................98 3.5.2 Suppression of Threshold-Voltage Fluctuations due to Operating Temperature .......................................99 3.6 Prospects and Issues in Low-Voltage Analog Circuits ............102 3.6.1 Prospects......................................................................102 3.6.2 Issues ...........................................................................102 3.7 Technology Scaling, Analog Performance, and Performance Trend for Electrical Systems ..............................106 3.7.1 Technology Scaling and Analog Performance.............106 3.7.2 Performance Trend of Electrical Systems ...................107 3.8 Low-Voltage Analog Circuit………………………………… 108 3.8.1 Basic Amplifier............................................................108 3.8.2 Switches ...................................................................... 111 3.8.3 Use of Passive Components ........................................113

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3.9 Fully-Depleted SOI Devices for Ultralow-Power Analog Circuits ....................................................................................114 3.9.1 Transconductance (gm) ................................................114 3.9.2 On-Conductance (Gon) of CMOS Analog Switch........117 3.9.3 RF Characteristics of FD-SOI Devices .......................119 3.10 Future Direction of RF and Mixed Signal Systems.................122 3.11 Summary .................................................................................125 References ...............................................................................126 4. 0.5- V MTCMOS/SOI Digital Circuits ....................................... 131 4.1 Introduction .............................................................................131 4.2 MTCMOS/SOI Circuits ..........................................................132 4.2.1 Combinational Circuits................................................132 4.2.2 Sequential Circuits ......................................................136 4.3 Adder .....................................................................................144 4.3.1 Carry Look-Ahead Adder ............................................145 4.3.2 Carry Select Adder ......................................................151 4.4 Multiplier.................................................................................157 4.4.1 Booth-Encoder and Wallace-Tree Multiplier ..............157 4.4.2 Wave-Pipelined Multiplier ..........................................163 4.5 Memory ...................................................................................170 4.5.1 Design of Ultralow-Voltage Memory Cell ..................171 4.5.2 MTCMOS/SOI SRAM Scheme ..................................174 4.5.3 Multi-Vt h Memory Cell ..............................................175 4.5.4 Multi-Vt h Readout Circuit ..........................................177 4.6 Frequency Divider...................................................................182 4.6.1 CMOS Frequency Divider...........................................182 4.6.2 ED-MOS Frequency Divider.......................................187 4.6.3 ED-CMOS Frequency Divider ....................................192 4.7 CPU .....................................................................................196 4.8 Summary .................................................................................208 References ...............................................................................209

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5. 0.5-1V MTCMOS/SOI Analog/ RF Circuits ............................... 213 5.1 Introduction .............................................................................213 5.2 RF Building Blocks .................................................................214 5.2.1 Piezoelectric Oscillators ..............................................215 5.2.2 Voltage Reference Generator.......................................220 5.2.3 Transmit/Receive Switches .........................................224 5.2.4 Low-Noise Amplifiers (LNAs)....................................226 5.2.5 Power Amplifiers (PAs)...............................................228 5.2.6 Mixers and Image-Rejection Receiver ........................230 5.2.7 Voltage-Controlled Oscillator (VCO)..........................242 5.2.8 Limiting Amplifiers .....................................................248 5.2.9 gm-C Filters.................................................................250 5.3 A/D and D/A Converters .........................................................254 5.3.1 Cyclic A/D Converter ..................................................255 5.3.2 Sigma-Delta A/D Converter ........................................264 5.3.3 Current-Steering D/A Converter..................................270 5.4 DC-DC Converter....................................................................276 5.4.1 Design of DC-DC Converter .......................................276 5.4.2 Switched-Capacitor (SC)-Type Converter...................276 5.4.3 Buck Converter............................................................279 5.4.4 Applicable Zones for SC-Type and Buck Converters ...................................................................283 5.4.5 On-chip Distributed Power Supplies for Ultralow-Power LSIs...................................................285 5.5 I/O and ESD-Protection Circuitry for Ultralow-Power LSIs ..291 5.5.1 Standard Interface Trends............................................291 5.5.2 Problems with I/O Circuits for 0.5-V/3.3-V Conversion...................................................................292 5.5.3 Guidelines for Design of Interface Circuits.................293 5.5.4 Performance of I/O Circuits ........................................297 5.5.5 ESD Protection with FD-SOI Devices ........................298 5.5.6 Design and Layout Requirements for ESD Protection ....................................................................300

5.6 Summary ...............................................................................303

304

..References ...............................................................................

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6. SPICE Model for SOI MOSFETs ............................................... 307 6.1 Introduction .............................................................................307 6.2 SPICE Model for SOI MOSFETs............................................307 6.3 Parameter Extraction ...............................................................309 6.4 Example of SOI MOSFET Simulation....................................325 6.5 Summary .................................................................................333 References ...............................................................................334 7. Applications .............................................................................. 337 7.1 Introduction .............................................................................337 7.2 1-V Bluetooth RF Transceiver and Receiver...........................338 7.2.1 Transceiver ..................................................................338 7.2.2 Receiver.......................................................................345 7.3 Solar-Powered, Radio-Controlled Watch ................................350 7.4 Batteryless Short-Range Wireless System...............................355 7.4.1 Transmitter ..................................................................355 7.4.2 Receiver.......................................................................360 7.5 Summary .................................................................................363 References ...............................................................................364 8. Prospects for FD-SOI Technology..................................................367 8.1 Introduction .............................................................................367 8.2 Evolution of Nanoscale FD-SOI Devices................................368 8.3 Device and Substrate Technologies for Ultrathin-Body SOI MOSFETs ........................................................................372 8.3.1 Ultrathin-Body SOI MOSFETs ...................................372 8.3.2 SOI Wafer Technologies for Future MOSFETs...........386 8.3.3 Design of FD-SOI MOSFETs in Sub-100-nm Regime ........................................................................389 8.4 Power-Aware Electronics and Role of FD-SOI Technology ...398 8.5 Summary .................................................................................39 9

References ...............................................................................40

.....................................................................................40

0

5Index ......................

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List of Contributors Numbers in parentheses indicate the chapter.

Hideaki Matsuhashi (2), Oki Electric Industry Co. Ltd. Toshiaki Tsuchiya (2.2), Interdisciplinary Faculty of Science and Engineering, Shimane University.

Yasuhisa Omura (2.3), Department of Electronics, Kansai University. Akira Matsuzawa (3), Tokyo Institute of Technology. Takakuni Douseki (3.2-3.5), (4), (7), NTT Microsystem Integration Labs., NTT Corporation.

Hiroshi Shimomura (3.9), Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

Masashi Yonemaru (4.3), AV Systems Group, Sharp Corporation. Koji Fujii (4.4), NTT Microsystem Integration Labs., NTT Corporation. Atsushi Kameyama (4.4), (5.4), STI- DC, Toshiba America Electronic Components, Inc.

Hiroshi Kawaguchi (4.7), Institute of Industrial Science, University of Tokyo. Tsuneo Tsukahara (5), (7.2), NTT Microsystem Integration Labs., NTT Corporation.

Minoru Kozaki (5.2.1), Semiconductor Operations Div., Seiko Epson Corporation.

Masayoshi Kinoshita (5.2.2), Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

Akihiro Sawada (5.2.7), Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

Makoto Yoshimi (1), (8.3.2), SOITEC Asia, Inc.

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Yasuyuki Matsuya (5.3), NTT Microsystem Integration Labs., NTT Corporation.

Jun Terada (5.3.1), NTT Microsystem Integration Labs., NTT Corporation. Yoshitsugu Inagaki (5.3.3), Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

Tsuneaki Fuse (5.4), Broadband System LSI Development Center, Semiconductor Company, Toshiba Corporation.

Yusuke Ohtomo (5.5), NTT Microsystem Integration Labs., NTT Corporation. Hiroshi Koizumi (5.5.5), NTT Microsystem Integration Labs., NTT Corporation.

Shunsuke Baba (6), (7.3), Oki Electric Industry Co. Ltd. Kazuyoshi Nishimura (6.4), NTT Microsystem Integration Labs., NTT Corporation.

Yoshifumi Yoshida (7.4), Seiko Instruments Inc. Norio Hama (7.4), Semiconductor Operations Div., Seiko Epson Corporation. Tohru Mogami (8), System Device Research Labs., NEC Corporation. Toshiro Hiramoto (8.2), Institute of Industrial Science, University of Tokyo. Ken Uchida (8.3.1), Advanced LSI Technology Laboratory, Toshiba Corporation.

Shin-ichi Takagi (8.3.1), Graduate School of Frontier Science, University of Tokyo.

Toshinori Numata (8.3.3), Advanced LSI Technology Laboratory, Toshiba Corporation.

Takayasu Sakurai (8.4), Center for Collaborative Research, and Institute of Industrial Science, University of Tokyo.

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PREFACE The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Bulk- Si devices are now running into a number of fundamental physical limits, and SOI technology provides a promising low- power solution to chip implementation. Research and development on SOI technology have been accelerating rapidly since 1998, when IBM announced that they would use partially- depleted (PD) SOI technology to make the PowerPC MPU. Motorola and AMD have also produced a number of MPUs made with SOI devices. Recently, Sony, Toshiba, and IBM announced that they would employ SOI devices for the next- generation broadband engine: the CELL processor. The next generation of SOI technology employs fully- depleted (FD) devices. According to the ITRS roadmap, FD- SOI technology will be necessary to preserve the scaling law. It has the additional advantage of ultralow-power operation, with the power consumption being less than 10 mW. Ultralow- power VLSIs are attracting a great deal of attention because they will be key components of network computing and services in the coming ubiquitous- IT society. The visible manifestation of this trend is the increasing number of mobile phones, electronic dictionaries, game sets, and personal digital assistants, for which it is imperative to reduce the power consumption as much as possible to prolong battery life. Oki Electric began producing a microcontroller and an RF chip made with FD- SOI devices for use in ultralow-power radio-controlled watches. As the demand for smaller, more

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power-efficient devices grows, FD- SOI technology will become increasingly important. Technical books on circuit design methods for PD- SOI devices in applications such as ultrahigh- speed microprocessors have been published; but no books have yet appeared that systematically cover design methods for FD-SOI devices in ultralow- power applications. This book covers topics ranging from the minimum required knowledge of the fabrication of SOI substrates and FD-SOI devices to the latest developments in device and process technologies, ultralow- voltage circuits such as digital circuits, analog/RF circuits, and DC-DC converters. Each technique is fully explained using figures. Furthermore, the book gives three examples of ultralow- power applications based on FD-SOI technology, providing every reader with practical knowledge on the technology and the circuits. We hope that this book will further the understanding of FD- SOI technology and ultralow- voltage circuit techniques for FD- SOI devices.

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In 1978 Katsutoshi Izumi (formerly of NTT, and now a professor at Osaka Prefecture University) invented the SIMOX substrate, a type of SOI substrate; and since that time, NTT has been involved in research and development on SOI technology as it relates to substrates, device fabrication, and circuits. Just 20 years later, Tetsushi Sakai (now a professor at the Tokyo Institute of Technology) and his group demonstrated the effectiveness of high- speed, low- power fully- depleted (FD) SOI devices in a 120K- gate- level CMOS VLSI on a SIMOX wafer. The FD- SOI technology we see today in Japan is due in large part to the inventiveness and persistence of Izumi and Sakai. The authors are grateful to them for their guidance and foresight. This book concerns the application of FD-SOI devices to ultralow- voltage, ultralow- power wireless systems. It is based on the findings and achievements of the Japanese national SOI project, which was supported by the New Energy and Industrial Technology Development Organization. The management efforts of Junzo Yamada and Hakaru Kyuragi (now with NTT Electronics) in the SOI project are greatly appreciated, as is the help with the fabrication of FD-SOI LSIs provided by Katsuzi Iguchi, Akio Kawamura, and Toshio Naka of Sharp Corporation, and Kiyotaka Imai and Shinya Maruyama of NEC Corporation. The authors also thank Professors Kunihiro Asada (Tokyo University) Hiroshi Ishihara (Tokyo Institute of Technology), and Mitsumasa Koyanagi (Tohoku University) for their sustained faith in the technology’s promise and for their valuable comments. The authors are also indebted to the following individuals for their valuable support and for helpful discussions: Yuichi Kado and Mitsuru Harada (NTT Corporation); Eiji Ikuta and Kazuya Fujimoto (Sharp Corporation); Koichi Oguchi, Teruo Takizawa, and Aritsugu Yajima (Seiko Epson Corporation); Jun Osanai and Fumiyasu Utsunomiya (Seiko Instruments Inc.); Mutsumi Mitarashi, Kouichi Morikawa, Kouichi Tani, and Tadashi Chiba (Oki Electric Industry Co. Ltd.); Junji Nakatsuka (Matsushita Electric Industrial Co., Ltd.); Shigeyoshi Watanabe (Toshiba Corporation); Kiyoshi Takeuchi and Toshiaki Koh (NEC Corporation), Takao Yonehara and Kazuhiko Ohmi (Canon Inc.); and Shouji Shiraishi (JEITA). Finally, we would like to express our appreciation to Yoshie Kinebuchi for her editorial support.

Acknowledgements