126 IEEE ELECTRON DEVICE LETIERS, VOL. 14, NO. 3, MARCH 1993

GaAs x Sb 1-x /In Y Al 1-Y Asp-Channel Heterostructure FET’s with High

Transconductance and Low Gate Leakage Current

Marino J. Martinez, Member, IEEE, Fritz L. Schuermeyer, Senior Member, IEEE, and C. Edward Stutz, Member, IEEE

Abstract-We report the first known p-channel GaAs,Sb, - , / In,M, - ,As HFET’s on InP. The devices, Using a strained-layer GaAs,Sb, - , channel, have achieved extrinsic transconduc-

m ~ / m m . addition to high transconductance, the devices exhibit excellent pinchoff and demonstrate a record gate turn-on voltage of -3 V as a result of extremely low gate leakage

lence band-edge discontinuity for either system [3]-[5]. These factors have made it difficult to fabricate high-

A comparison of hole drift mobilities and predicted valence band-edge discontinuities reveals that for a zinc blend lattice close to the InP or GaAs lattice constants

tances of 40 mS/mm and intrinsic transconductances of 100 performance complementa~ circuits in these systems‘

currents, making them exceptional candidates for complemen- tary technologies. These outstanding gate characteristics are

and a bandgap greater than 0.5 e ~ , there is only one

large valence band-edge discontinuity. This combination is attributed to the valence band-edge discontinuity of 0.64 eV. ‘Ombination that gives high as as a

I. INTRODUCTION

PURRED in part by the tremendous proliferation of S CMOS integrated circuits, interest in complementary heterostructure FET (HFET) technology has been grow- ing in recent years. Though n-channel FET’s, particularly those grown on InP, continue to show outstanding perfor- mance and are constantly improving, p-channel devices have lagged far behind. This is due in large part to the much lower mobility of holes in 111-V materials, as com- pared to electrons, but is also due to difficulty in reducing gate leakage currents. Both of these problems may be partially ameliorated by using a material with a higher hole mobility for the channel and using a barrier/ channel material combination with a large valence band-edge dis- continuity to confine holes in the channel.

Previous efforts have focused on the GaAs/ a,- GalPxAs [1] and In,Ga,-,As/ In,Al-,As [21 systems due to their ease of integration with relatively mature n-HFET technologies. Both of these systems suffer from a large mismatch between hole and electron mobilities with the mismatch being worse for In,Ga, -,As/ In,Al, -,As. The situation is made worse by-the relatively small va-

Manuscript received October 8, 1992; revised December 16, 1992. M. J. Martinez is with the Solid State Electronics Directorate, Wright

Laboratory, Wright-Patterson Air Force Base, OH 45433-6543, and the Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721.

F. L. Schuermeyer and C. E. Stutz are with the Solid State Electronics Directorate, Wright Laboratory, Wright-Patterson Air Force Base, OH 45433-6543.

IEEE Log Number 9207501.

a device bearing a channel containing GaSb or GaAs,- Sb,-, and a barrier containing AlAs or In,Al,-,As. This prediction is supported by Monte Carlo simulation of bulk hole transport in GaAso,,,Sbo,,, showing a mobility of 400-540 cm2/V. s (depending on the severity of alloy scattering) as compared to 270 cm2/V. s for GaAs [6], and by measurement of a valence band-edge discontinuity of 0.64 eV (300 K) [7] to 0.78 eV (4 K) [4] between GaAs,,,,Sb,,,, and Ino,52Al,,,8As. Nevertheless, it has re- mained to be proven that this would translate into supe- rior device performance.

To this end, we have fabricated the first GaAs,Sb, -,/ In,Al, _,AS p-channel HFET’s on InP. These devices, intended for integration with InP-based n-HFET’s, demonstrate peak transconductances comparable to any other reported p-channel HFET’s and have the lowest gate leakage currents and highest maximum drain cur- rents known for such devices.

11. DEVICE STRUCTURE AND FABRICATION The structures were grown by molecular beam epitaxy

in a modified Varian Gen I1 chamber on semi-insulating (100) InP substrates. Transmission electron microscopy has verified the ability of the system used to produce smoother and abrupt interfaces between GaAs,Sb, -, and In,Al, _,As [SI. Doping levels were calibrated to Hall effect measurements and layer compositions were cali- brated by X-ray diffraction measurements. The strained- layer channel has a lattice mismatch of 1.2% with the In,l,52Alo,48As and its thickneoss is equal to the approxi- mate critical thickness of 200 A. The sheet hole density in the channel is 8 X 10” cm-*.

U.S. Government work not protected by U.S. copyright

MARTINEZ et a1 GaAF,Sb,~,/In,AI,-,As p-CHANNEL HETEROSTRUCTURE FET'S 127

Source Drain

-75

-60 - E i ln,52A1,48As

200 A p GaAs.35Sb.65 E

1000 A 1 5 ~ 1 0 ' ~

a, 5 -30

E c .- i ln,52A1.48As

SI InP -15 Q

40

32 E 3 E

24 0

m c 16 I) -!2

8 a $

m

Fig. 1. Finished device structure of strained-channel GaAs,Sb, In,AI, - ,As showing recessed gate. The p+ GaAs,,,,Sb,,,, layer is included to improve ohmic contacts, the intrinsic Ino,52 AI,,,,As layer is a semi-insulating barrier between gate and channel, and the n In,, 52Al,, lxAs layer is part of the buffer, but also aids in pinchoff of the device. All layers except the GaAs,,,,Sbo,,, channel are nominally lattice.matched to InP, doping was performed in situ during crystal growth; p-type layers are beryllium doped and the ".type layer is silicon doped.

?.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5 Gate Voltage (V)

Fig. 2. Measured extrinsic transconductance at room temperature for the device structure shown in Fig. 1. The peak transconductance is 40 mS/mm. The characteristics are very broad with respect to gate voltage.

Fabrication used only optical lithography and employed a recessed gate by wet chemical etching. Isolation was achieved by a mesa etch in a H,PO,:H,O,-based solu- tion. Ohmic contacts were evaporated Au/Zn/Au (50 'h/200 k /2500 "A) alloyed in a simple tube furnace in a nitrogen ambient. The alloyed ohmic contacts had a mea- sured contact resistance of 0.97 R . mm. Gate recess was performed with a solution similar to that used for mesa etch. The finished gate length was 1 p m and the width was 200 pm. The completed structure is shown in Fig. 1.

111. RESULTS AND DISCUSSION

The dc characteristics of these HFET's were measured at room temperature and were found to be comparable or superior to published results of In,Ga, -,As/ In,,Al, -,As p-HFET's [2]. Peak extrinsic transconductance was mea- sured to be 40 mS/mm. The corresponding intrinsic transconductance is 100 mS/mm. The plots of transcon- ductance and drain current in Fig. 2 show that the transconductance curve is quite broad, remaining above 30 mS/mm for a gate voltage range of about 1.5 V. This allows some devices to attain maximum drain currents in excess of 100 mA/mm, an important attribute if the transistors are expected to charge and discharge capaci- tive loads quickly. Unlike other p-HFET's, these devices also have excellent pinchoff characteristics, as demon- strated in Fig. 3, with Zd(on)/Zd(off) greater than 90000. This, and the lack of any photoconductivity effects, indi- cates that the channel thickness was not beyond the critical thickness.

Perhaps the most important feature of these p-HFET's is the extremely low gate leakage currents they exhibit. Taking turn-on of the gate to occur when the gate current reaches 5 p A / p m or 1 mA, these gates had a forward gate turn-on voltage V,,,, of approximately -3.0 V, as shown in Fig. 4. This represents an effective barrier height of 0.723 eV with an ideality factor of 5.3 corresponding to

.751, -60 -

-0.5V 1

ov

0.5V -

Drain Voltage (V)

Fig. 3. Measured I-V characteristics at room temperature for the device structure shown in Fig. 1. The device shows very good pinchoff, with the ratio of fd(on)/fd(ufl) in excess of 90000. The device shows no gate leakage effects and negligible output conductance.

Gate Voltage (V)

Fig. 4. Measured gate leakage current at room temperature as a function of forward bias for the device structure shown in Fig. 1. Defining gate turn-on at 5 pA/pm, the gate of this device turns on at approximately -3 V (1 mA). This is the highest known gate turn-on voltage for any heterostructure FET (HFET).

128 IEEE ELECTRON DEVICE LETTERS, VOL. 14, NO. 3, MARCH 1993

the heterojunction as part of the barrier. This is the REFERENCES highest known gate turn’on for any p-HFET tech- [I] D. E. Grider a[,, “A 4 D i t synchronous static random access nology and approximately 50% higher than the previous memory based uuon delta-doued comulementary hetrostructure record. This is an essential feature for enhancement-mode insulated gate fie‘ld effect trahsistor te‘chnology,” in 1991 IEEE _. operation.

While these results are impressive, they are for unopti- mized device structures and processing; it is fully expected

GaAs IC Grnp. Tech. Dig., 91CH3059-3, p. 71. [2] P. P. Ruden, A. I. Akinwade, D. Narum, D. E. Grider, and

J. Nohava, “High performance complementary logic based on GaAs/ InGaAs/ AlGaAs HIGFETs,” in IEDM Tech. Dig., 1989,

that device properties will continue to show improvement. Nonetheless, this unique combination of transconduc- tance, high drain current, and very low gate leakage current shows the promise of GaAs,Sb, -,/ In,Al, -,As p-HFET’s as part of a complementary HFET technology. Future experiments will examine improvements to the device structure to lower the threshold voltage, and broaden the transconductance curve as well as raising the peak transconductance.

ACKNOWLEDGMENT The authors would like to thank E. Taylor for his

dedication to crystal growth, and D. Look, A. K. Rai, and P. Yu for their efforts in material characterization and

p. 217. [31 W. 0. Watanabe, J. Yoshida, M. Mashita, T. Nakanisi, and

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[41 Y. Nakata et al., “Characterization of GaAsSb/InAlAs quantum- well structures lattice-matched to InP grown by molecular beam epitaxy,” J. Ctyst. Growth, vol. 363, 1989. F. Schuermeyer, P. Cook, E. Martinez, and J. Tantillo, “Band-edge alignment in heterostructures,” Appl. Phys. Lett., vol. 55, pp. 1877, 1989.

161 M. J. Martinez, D. C. Look, J. R. Sizelove, and F. L. Schuermeyer, “Monte Carlo simulation of hole transport in AI,Ga, -.As, In,-,Al,As and Ga,AsSb,-.,” submitted to J. Appl. Phys.

[71 M. J. Martinez et al., “Measurement of valence band-edge discon- tinuity for the InAlAs/ GaAsSb heterojunction lattice-matched to InP,” in Proc. 4th Int. Con& InP and Related Mater. (Newport, RI), U. 354.

[5]

calibration. [SI A. K. Rai, unpublished.