NCTU CSDLab

GaN HEMT on Si for High Power Applications

Speaker : Chia Hua ChangPost-doctoral Research Fellow

Advisor : Prof. Edward Yi ChangDepartment of Materials Science and Engineering

National Chiao Tung University, Taiwan

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NCTU CSDLab

Application Advantages

Material Properties of GaN

Outline Introduction

Material Growth of GaN

GaN Device Fabrication

GaN Devices Characteristics & Performance

Summary

Issues of GaN grown on Si substrateMOCVD growth of GaN on Si

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Introduction

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Why GaN ?

Material Properties Device Implications

Large direct band gap High breakdown voltage, high temperature operation, UV

optoelectronic devices

Large Spontaneous and piezoelectric polarization

High sheet charge concentration without

intentional doping, device applications

High electron mobility Microwave devices easily fabricated

High melting point, physically hard material

Easier to process and handle

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Material Band Gap Energy

(eV)

Breakdown field

(MV/cm)

Thermal Conductivity

(W/cm*K)

Mobility(cm2/V*s)

Saturated Velocity

(*107 cm/s)

Si 1.1 1.5 1.5 1300 1.0

GaAs 1.4 0.5 0.5 6000 1.3

SiC 3.2 4.9 4.9 600 2.0

GaN 3.4 1.5 1.5 1500 2.7

Key features of GaN

High breakdown voltage Wide Band gap High current density - High electron velocity - High sheet carrier density

High power applicationHigh power application

Material Property of GaN

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--Source: Compound semiconductor website--Source: Caltech website

Comparison of Different Compound Semiconductor Device Performances

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Main Applications of GaN Devices

Light Emitting Diodes

Laser Diodes

RF electronics

Power electronics

Sanken

Shimei

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GaN Devices in Power Electronics

Data from Yole Development (2007)

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0.1MHz 10MHz 100MHz 1GHz

1kW

10kW

100kW

1MW

Frequency

1MHz

Most devices consist of Si material.

Most devices consist of Si material.

10GHz

Si

DC Transmission

Thyristor

IGBT

Train

SiC

Tran

sdu

ctio

n C

apac

ity

(rat

ed c

urr

ent

x ra

ted

vo

ltag

e)

Solar InverterIH Cooking

Vehicle

Power Source for PC

1 bit Audio Amp.

GaN

MOSFET

GaN FETs are also applied to RF power amplifiers.

Applications for Power DevicesApplications for Power Devices

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GaN HEMT vs. Si Power DeviceGaN HEMT vs. Si Power Device

2014: IGBT with 3-D trench and field stop approach

GaN HEMT has larger breakdown voltage and smaller on-resistance

* GaN-based device has better power handling capability

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Application Advantages

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Potential Applications of GaN-based Power Devices

12

Automotive

Manufacturing apparatus

Home Appliances

Power Supply/ Convertor

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Electric Vehicle Configuration

Data from Toyota Central R&D Labs. (IEDM 2010)

DC/DC boost converter and DC/AC inverter are key modules to drive the AC high power motor from battery energy.

DC/DC buck converter is needed for the accessories.

Inverters consist of power modules that in turn contain many power devices. Therefore, power devices are key components for electric vehicle.

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Power Device Requirements for EVs

• Breakdown voltage: It is needed to over 1000 V, taking the surge capability into considerations.

• On-resistance: It is as low as possible to reduce the power loss, to minimize the size and to reduce the cost.

• Normally-off: E-mode is required for the simple inverter control board and the fail-safe viewpoint.

U.K. Mishra et al, IEDM (2010)

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Market forecast of GaN power devices

Significant boost in market demand

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GaN High Electron Mobility Transistor (HEMT)

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AlGaN/GaN HEMTEc= 68% Eg

- Unlike other HEMT structures, 2DEG charges in GaN HEMT is induced by: Polarization field & surface traps

Substrate

GaN

AlGaNS DG

2DEG

17

*No doping is required

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Polarization effect in AlGaN/GaN HEMT

AlN

GaN

AlN

Ga

N

GaN(relaxed)

AlGaN(tensile)

Psp

Psp Ppz

Origins of spontaneous polarization:i) Lack of inversion symmetry of the wurtzite structure

ii) High electronegativity of nitrogen atom

2 types of polarization: spontaneous & piezoelectric

For AlxGa1-xN pseudomorphically grown on GaN:

Spontaneous:

Psp (x) = -0.090x – 0.034(1-x) + 0.019(1-x) Cm-2

Piezoelectric:

Ppz (x) = -0.0525x – 0.0282x(1-x) Cm-2

Net fixed polar charge at the AlGaN/GaN interface:

= Ppz + Psp - Psp

AlGaN GaN

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AlxG1-x N Epz

Without material doping in AlGaN or GaN, formation of 2DEG as a result of polarization field and surface traps

2DEG: Polarization field + Surface states

Surface states form after the material growth

Electrons at the surface are driven into the channel by the strong Epz

-

+

Net polarization charge

Net polar charges induce electric field Epz in AlGaN

- source: UCSB

Source of carriers

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2DEG: Band diagram

No Polarization field

No Surface trap

No ns

Polarization field (3.06MVcm-1)

Surface trap =1.36x1013cm-2

ns= 1.34x1013 cm-2

Background doping: 1x1015 cm-3

- source: UCSB

2DEG

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2DEG: AlGaN critical thickness

Surface potential,

s

tcrit Surface trap level, Et

AlGaN thickness, t:

1. t < tcrit : surface traps filled with electron (neutral)

2. t , Epz increases the surface potential s

3. t > tcrit (s > Et) electrons transfer to channel 2DEG

4. tcrit depends on the Et and Epz.

ns = surface states

- source: UCSB

Minimum thickness

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1. When Al% increase polarization field increase, ns increase.

2. Al% increase, mobility decrease due to i) alloy scattering, ii) interface roughness

3. Al>35%, large stress in AlGaN, film crack, mobility drops abruptly.

Al=35%, Ns=1.9x1013

The effect of Al concentration

Source: National Research Council Canada

Film crackingEt

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Growth of GaN Materials on Si Substrate

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Advantages of Growing III-nitrides on Si Substrate

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Epitaxial relation between GaN and Si

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Lattice mismatch lattice mismatch between GaN and Si is 17% High dislocation density in GaN layer(1010cm-2)

Meltback etching At high temperature Ga and Si form an alloy leads to

deterioration of the substrate and the epilayer

Meltback etchingGaN layer shows a rough surface

Deep hollows in Si substrate

Problems associated with GaN on Si (111)

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Problems associated with GaN on Si (111)Major problem is thermal expansion mismatch

Thermal mismatch between GaN and Si is 54%High tensile stress cause “cracks” in GaN when cooling from

high growth temperatureCracks and GaN thickness is trade off.

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Thomas Swam MOCVD System2 ~ 6 inch Si substrates

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GaN reactor cleaning and conditioning GaN reactor cleaning and conditioning

Using long bake-out at 1050oC for 30 minutes in hydrogen between each GaN deposition run to remove the Ga from the susceptor and chamber and gas lines

Pre-treatments of Si substrate Pre-treatments of Si substrate

The Si(111) substrates were chemically cleaned by H2SO4: H2O2: H2O (3:1:1) and BOE HF(20:1) before being loaded into the reactor

In situ cleaning in reactor In situ cleaning in reactor

The Si(111) substrates were in situ cleaned at 1050oC for 30 minutes under a hydrogen atmosphere

Epitaxy Process

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Temperature

HT/LT/HT AlN Graded AlGaN /GaN

Pressure

TMAl

TMGa

550℃

100 torr 50 torr

300 torr

1050℃1035℃

800℃

1035℃860℃

Layer

Layer growth sequence and growth conditionLayer growth sequence and growth condition

NH3

H2

In situ cleaning

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The solution for growth of GaN on Si (111) Substrate

☆ Multilayer AlN (HT-AlN/LT-AlN/HT-AlN) were used. The growth of multilayer AlN on Si Substrate as the buffer

♣1st: HT-AlN is used to prevent the reaction of Si with the Ga and Nitrogen

♣ 2nd: LT-AlN is used as a nucleation layer for growth of the top AlN, and stop the extension of cracks and defects from the 1st AlN

♣ 3rd:HT-AlN is to form a high quality AlN with lower defect density for further growth of GaN layer

♣ 4th:Graded AlGaN is used to compensate the strain between the GaN and AlN films

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Single AlN layer thickness =30nm

crack

Multilayer AlN thickness =100nm

crack free

Optical image of AlN films on Si substrate

50μm

50μm

Sample 1 Sample 2

Si[1-10]Crack direction

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0 50 100 150 200 2500.0

0.5

1.0

1.5

2.0

2.5

3.0

AlN

(00

4) X

RD

Mos

aic

FW

HM

(d

eg)

AlN film thickness (nm)

AlN crystal quality versus AlN film thickness

APPLIED PHYSICS LETTERS 91, 222111 2007

The FWHM of the XRD rocking curve decreases when the AlN thickness increases.

This means that to reach a high quality AlN film, enough AlN thickness is necessary.

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0.3 0.6 0.9 1.2 1.5 1.80.1

0.2

0.3

0.4

0.5

0.6

GaN

(00

4) X

RD

Mos

aic

FW

HM

( d

eg)

AlN (004) XRD Mosaic FWHM (deg)

Dependence of GaN crystal quality on AlN crystal quality

APPLIED PHYSICS LETTERS 91, 222111 2007

AlN film quality has significant influence on the quality of the GaN film grown

Also confirms that in order to grow high quality GaN films, high quality AlN buffers are necessary.

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Effect of Buffer layer structure on GaN film grown on 6” Si(111) substrate

Sample 1 2 3 4 5 6

Buffer Type SingleHT-AlN

*Multilayer-AlN

*Multilayer-AlN

*Multilayer-AlN

*Multilayer-AlN

*Multilayer-AlN/ AlGaN

Buffer-layer thickness (nm)

30 100 60 120 150 200

GaNthickness (μm)

0 0 0.5 0.5 2 0.8

FWHMGaN(004) N/A N/A 0.54° 0.315° 0.120° 0.223°

FWHMAlN(004) 2.75º 1.02° 1.66° 0.865° 0.52° 0.343

Wafer size(in) 6 6 6 6 6 6

Cracks yes no yes yes yes no

Radius of curvature(m)

80.45 32.17 25.24 48.65 72.91 238.96

Bow (μm) -23.32 -54.36 -71.3 -52.3 -45.65 -8.63

*Multilayer-AlN:HT-AlN/LT-AlN/HT-AlN

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Sample GaN

Thickness(μm)

*AlNThicknes

s(nm)

GradedAlxGa1-xN

Thickness (nm)

FixedAlxGa1-xN

x fraction

FixedAlxGa1-xN

Thickness (nm)

AlNstrain(εa)

AlNXRD (004)

FWHM(deg)

GaNstrain(εa)

GaNXRD (004)

FWHM(deg)

A 0.8 200 0 0 0 0.378 0.717 0.146 0.322

B 0.8200 500 0.25 200 0.335 0.319 0.137 0.228

C 0.8200 500 0.50 200 0.312 0.357 0.132 0.242

D 0.8200 500 0.42 200 0.300 0.293 0.120 0.158

Layer thickness, composition and induced strain for sample A~D with different buffers * multilayer AlN(High Temperature/Low Temperature/ High Temperature AlN)

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XRD ω-2θ scan of GaN films grown on various types of multilayer AlN/graded AlxGa1-xN/fixed AlxGa1-xN composition buffers

XRD data of sample with different buffer layers

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Crack-free GaN sample on 6” Si (111) substrate

Ref: APPLIED PHYSICS LETTERS 91, 222111 2007

With the combination of multilayer AlN and AlGaN buffers, high quality crack-free GaN is grown on 6’’ Si substrate

NCTU’s GaN on Si

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*Δω = Kσxx cm-1 GPa-1 ,K= 4.3Free-standing GaN E2 (TO)= 567.5 cm-1

Raman shifts of the E2 (TO) phonon peaks

A:566.8 cm-1 B: 566.6 cm-1 C: 566.9 cm-1 D:567.2 cm-1

The values of the tensile stress in the GaN films sample A = 0.162 GPa sample B = 0.209 GPa sample C = 0.139 GPa sample D = 0.069 GPa

*Guha, F.Shahedipour, R. C.Keller, V. Yang and B. W. Wessels, Appl. Phys. Lett. 78,58(2001)

In-plane Stress Measurement by Raman

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Reciprocal space mapping for GaN with AlN/AlGaN buffer on Si (111) substrate

APPLIED PHYSICS LETTERS 91, 222111 2007

afilmGaN=3.1928Å , afilm

AlN=3.1203Å abulk

GaN=3.189Å ,abulkAlN=3.111Å

εa = [(afilm- abulk)/ abulk ] *100%

GaN :εa,GaN= 0.12%, AlN :εa,AlN = 0.3%

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Weak Beam @ g=[0002] Weak Beam @ g=[10-10]

The dislocations density in GaN film is much lower than those in AlGaN and AlN films.

Double AlGaN buffer layers can reduce threading dislocation propagation.

Screw and mixed dislocations Edge and mixed dislocations

Growth of high quality GaN film on Si substrateby using AlN and Graded AlGaN Buffer Layers

Si Substrate

HT/LT/HT AlN

Al0.29Ga0.71NAl0.07Ga0.93N

GaN

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Si

Si

0.4 μm GaN on Si 1.2 μm GaN on Si

Dislocation density is reduced from 5.88×109 to 2.04×108 cm-2 by increasing GaN thickness from 0.4 μm to 1.2 μm.

Low dislocation density GaN film can be obtained using double AlGaN buffer layers.

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GaN HEMT Device Fabrication

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v AlGaN

GaN

Substrate

GaN

Substrate

GaN

Substrate

GaN

Substrate

Source Drain

AlGaN

GaN

Substrate

Ohmic Gate

Passivation Nitride Via Air-Bridge

v v vAlGaN AlGaN AlGaN

AlGaN

GaN

Substrate

Mesa

Source Drain

Process Flow

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・ Low Rc of 0.4mm achieved (by 1/5)

Ti

MoAl

Au

GaN

AlGaN

GaN

AlGaN

GateSource

Multi-layer structure (Ti/Al/Mo/Au)

Smooth surface morphology up to 850C

800 850 9000

1

2

3

Rc

(m

m)

Anneal Temp.（C）

Ti/Al/Mo/Au

800 850 9000

1

2

3

Rc

(m

m)

Anneal Temp.（C）

Ti/Al/Mo/Au

Ti/Al/Mo/Au Ohmic Contact Technology

Drain

45

Ni/Au

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Top view- resist dose

Heavy line dose in middleLight area dose on the sides

Metal profile after evaporation

Re-entrant resist profile creates metal discontinuity for liftoff

Resist profile after developing

PMMA top layer, less sensitiveP(MAA-MMA) middle layer, sensitivePMMA bottom layer, less sensitive

substrate

substrate

substrate

Metal profile after liftoff

Bottom resist layers define stem and head of mushroom gate

Formation of mushroom gate using a tri-layer resist process:

Gate Lithography

--source: Cornell university

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• Gate resistance is an important parasitic resistance source

• Rg = Zg/A, where Z g is the gate width and A the cross-sectional area of the gate

• Increasing cross section area of the gate is essential in reducing gate resistance for sub micron gates

SEM image of a mushroom gate with <0.2 m footprint

Source: Cornell university

Mushroom Gate

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NCTU CSDLab Department of Materials Science and Engineering

Compound Semiconductor Device Laboratory – CSD Lab.

Large device can be connected by electro-plated Au air bridge

Images of Au Air-Bridge (for high current)

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GaN HEMT Devices Characteristics

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• Maximize I Maximize nS, • Maximize nS

Maximize PSP, PP

Maximize Al mole fractionwithout strain relaxation• Maximize Minimize effective gate length Minimize Lg and gate length extension• Maximize Minimize dislocations Smooth interface

Vmax

Imax

V

max max max18

S

P V I

I V n

DC Device Level Issues

- source: UCSB

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G

Electrons in Surface States

Lg

AlGaN

- - - - - -

- - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-

---

- - - -

Dislocation

Electrons in

buffer traps

Point Defect

Electrons in surface states and/or buffer traps deplete the channel causing gate length extension

Severe consequence: Dispersion between small signal and large signal behaviors because of the large trap time constant

Vds (V)

I d (

5 m

A)

DC

AC

Load line

Dispersion

- source: UCSB

Dispersion At High Frequency Operation

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SG D

OFF-state

Depletion layer

SG D

ON-state

Current collapse due to surface traps

Drain Voltage

Dra

in C

urr

ent

0

Current collapse

Non-Ideal Power Operation

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• Expected power is less than predicted power due to RF dispersion

• Pulsing gate with 200 ns pulse have been plotted to get the i-v curves under conditions similar to RF

--source: Cornell university

Current Slump in HEMTs

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A Si3N4 passivation layer improved power performance

After passivation usually perform at 60 –70 % of the expected power level

Passivation: Remedy for Current Slump

--source: Green, et al, IEEE Electron Device Lett., June 2000, p. 268

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J0

3-point Test Fixture: measurement under point bending

20 /3 LhJyy

• h : Thickness of sample• J0 : Deformation in the

center• L : Length of sampleIn this work, εyy = 1.47×10-4

= 2.82×10-4

= 3.94×10-4

h

L

Force

Cylindrical bar

(Phys. Status Solid B, 211, 309 , 1999)

Effect of External Stress on Surface State

0 2 4 6 8 100

200

400

600

800

1000 DC without strain Pulse without strain Pulse under strain

ID (

mA

/mm

)VD (V)

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AlGaN

GaN

Substrate

First SiNx layer : 100nm

Second SiNx layer : 550nm (Stress)

AlGaN

GaN

Substrate

First SiNx layer : 100nm

Tensile strain would degrade the transient drain current due to the additional surface states

0 2 4 6 8 100

100

200

300

400

500

600

700

800

900

VD ( V )

ID

( m

A/m

m )

0 2 4 6 8 100

100

200

300

400

500

600

700

800

900

VD ( V )

ID

( m

A/m

m )

Bias Point : Vd = 0 V , Vg = - 6 V

Pulsed I-V under Tensile Strain by SiNx

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Figure. Schematic conduction band diagram for an AlGaN/GaN HFET showing the various space charge components.

Donor-like surface states are a likely source of 2DEG electrons in AlGaN/GaN HFETs.

Polarization Charges

(Appl. Phys. Lett., vol. 77, no. 2, 2000)AlGaN

+ + + + + + + + + + + + + + + + + + +

GaN

Substrate

- - - - - - - - - - - - - - - - - - - - - - - - - - sp pz SIP

(SIP: Stress-Induced polarization)

- - - - - - - - - - - - - -

+ + + + + + + + + + +

+ + + + + + + + + + + + + + + + + + +

GaN

Substrate

- - - - - - - - - - - - - - - - - - - - - - - - - - sp pzAlGaN

Additional states

Stress

2DEG Electrons and Surface States

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S.I. SiC Sub.

Ti/Al

GaN

AlGaN

Source

Field Plate SiN Film

Drain

Gate

Relaxed Electric Field by Field Plate

- Suppress Current Collapse

- Enhance Breakdown Voltage

Field-Plate Technology

Function of field-plate:

1. Reduction in drain current dispersion phenomena

2. Enhancement of breakdown voltage

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• Reduction of drain current dispersion

Device cross-section with field plate gatePulsed I–V characteristics measured with 200 ns pulse-width

+Vg

+++- - - -Gate

Without field plate (Vg=2V)

Without field plate (Vg=2V)

With field plate (Vg=2V)With field plate (Vg=2V)

Functions of Field-Plate gate

--source: IEDM Conf., 1998,pp. 59–62 IEE E.L.,2004, Vol.40, No.1 IEEE TED.,2001, Vol.48, pp. 560–566

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• Enhancement of breakdown voltage

FP

Gate

Device cross-section with field plate gateSimulated distribution of the electric field along the 2-DEG.

without FP

with FP

Functions of Field-Plate gate

--source: IEEE TED.,2001, Vol.48, NO.8

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G

S D

One-step FP

100V0V

0V30V

60V 90V

S D

G

100V0V

0V30V

60V90V

Al0.2Ga0.8N

GaN

SiO2

G Slanted FP

S D100V

30V 60V 90V0V

0V

G

S D

Multi-Step FP

100V

30V 60V 90V0V

0V

Multi-Step FP vs Slanted FP-1

--source: Fukui University, Japan

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0

1

3

2

4E

lect

ric F

ield

(M

V/c

m)

0 1 2-1

3 4 5 6

Distance from Source (mm)

Vds=100VVgs=-5V

Without FP

One-step FP

Multi-step FP

Slanted FP

Multi-Step FP vs Slanted FP-2

--source: Fukui University, Japan

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--source: UCSB

Breakdown Voltage Enhancement by Slanted Gate

Off-state BV: 200V 1900V

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GaN HEMT for Switching Applications

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GaN HEMTs for Switching Application

• Converter (DCDC)

Fig.1 Buck Converter

Fig.2 Boost Converter

• Inverter (DCAC)

- Buck converter (high V low V)- Boost converter (low V high V)

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Ideal Switching Device

Requirement for switching device

Current

Voltage

Low on-resistance

High breakdown voltage

Power Loss = I X V ≠ 0Efficiency < 100%

• Low on-resistance• Fast switching • High breakdown voltage• High Temperature stability

GaN HEMT

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• FP MIS-HEMT Switch• SiC-SBD connected• Vout=Vin/(1-D)

Vin=175V, Vout=350V--source: Toshiba Corp., Japan

Hybrid Boost Converter Circuit

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• ID,max= 367 mA/mm (Vgs=2V)

• Ron,spec = 3.6mΩ·cm2 • The Breakdown voltage = 940V• Power efficiency = 94.2% ( 1MHz)

44x lower than the Si-limit

--source: Toshiba Corp., Japan

Switching Characteristics

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-- Source: Hong Kong University of Science and Technology

Basic Configuration

Integration Boost Converter Circuit

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Power Efficiency

69% of total loss

• Vin=10V, Vout=21V , D=55%• Power efficiency = 84%

-- Source: Hong Kong University of Science and Technology

Switching Characteristics

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Enhancement-mode HEMT(E-mode HEMT)

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Criterion of Operation Modes Key factor of definition: Threshold voltage (Vth)

-5 -4 -3 -2 -1 0 1 2 3 4 50

100

200

300

400

500

600

700

800

I D (m

A/m

m)

VG (V)

D-mode

Vth= -3 V Vth= 0.7 V

VthE-mode

Vth = gate bias (VG) intercept of extrapolation of drain current

(ID)E-mode operation:

Vth > 072

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Advantages of E-mode device

Advantages:

Simplified circuit reducing size & cost

Reducing power consumption

Providing fail-safe

Properties of operating

condition:

Single-polarity power supplyVDS VGS

E-mode ＋ ＋D-mode ＋ －

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How to realize E-mode operation

E-mode HEMT

Reducing on-state resistance Recessed gate

Modulating Schottky barrier

height F-plasma treatment

p-GaN cap

Substrate

i-GaN

GaN

S DGAlGaN

Substrate

i-GaN

GaN

S DG

Substrate

i-GaN

S DGAlGaN

GaNF-

Recessed Gate P-GaN cap F-plasma treatment

AlGaN

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Sapphire

2 μm i-GaN

13 nm AlGaN

S DG

1 nm AlN

CF4 plasma treatmentSi3N4 layer

Schematic cross-section and transconductance characteristics F-treated E-mode AlGaN/GaN HEMTs

-8 -6 -4 -2 0 2 40

100

200

300

400

500

600

Vth = 1.4 V

I D (m

A/m

m)

VG (V)

D-modeE-modeE-mode+annealing

Vth = -2.3 V

0

40

80

120

160

GM (m

S/m

m)

D-mode E-mode E-mode + PTA

IDSS (mA/mm) 450 20 210

Vth (V) -2.3 N/A 1.4

GM (mS/mm) 150 5 100

Characteristics of F-treated E-mode device

NCTU CSDLab

F-treated E-mode MIS-HEMTsAl2O3 (nm) 16

IDSS (mA/mm) 520

GM (mS/mm) 100

Vth (V) 5.2Sapphire

2 μm i-GaN

13 nm AlGaN

S DG

1 nm AlN

Si3N4 Al2O3

0 2 4 6 8 10 12 14 16 18 200

100

200

300

400

500

600

700

I D (m

A/m

m)

VD (V)

VG = 11 ~ 1 V , in step of -2 V

520 mA/mm

-1 0 1 2 3 4 5 6 7 8 9 10 110

100

200

300

400

500

600

I D (m

A/m

m)

VG (V)

0

20

40

60

80

100

120

Vth= 5.2 V

GM (m

S/m

m)

520 mA/mm

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NCTU CSDLab

Improvement of forward turn-on voltage by MIS-HEMT

gate leakage current and gm curves of F-treated E-mode AlGaN/GaN HEMTs

• High-k gate insulator improved gate leakage current towards high-turn-on voltage

• High Von characteristics could improve output current density

without limiting by gate leakage phenomenon

-15 -10 -5 0 5 10 151E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

0.1

1

10

Von = 2 V

I G (m

A/m

m)

VG (V)

E-modeMIS E-mode

Von = 12.7 V

-2 -1 0 1 2 3 4 5 6 7 8 9 10 11 120

100

200

300

400

500

600

700

800

I D (m

A/m

m)

VG (V)

0

20

40

60

80

100

120

140

160

180

200

220

240

GM (m

S/m

m)

E-modeMIS E-mode

Von = 12.7 VVon = 2 V

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NCTU CSDLab

New Device Structures

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NCTU CSDLab

E-mode GaN MIS-HEMTs with Triple Cap Layer

• Triple cap layer increases Ns of 2DEG by 80%High current density

• High-k gate insulator modulates Vth up to 3V

-- Source: Fujistu Laboratory, Japan

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NCTU CSDLab

E-mode GaN HEMTs with p-type Injection Gate

• Replace conventional Schottky gate with p-GaN hole injection gate Vth shifts to +0.45V

• Low on-resistance (3.4 mΩcm2) due to 2DEG -- Source: Meijo University, Japan

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NCTU CSDLab

Hole Injection gated GaN HEMTs

99.3% Efficiency 3-Phase Inverter Using Injection Gated GaN HEMTs

-- Source: Panasonic Corp., Japan

Output waveform @900W operation

Efficiency of GaN-based Inverter well exceeds Si-based IGBT inverter

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NCTU CSDLab 82

Source: Marlodt, et al., J. Appl. Phys., vol.48 , 2009, Kambayashi, et al., IEEE Elec. Dev. Lett., vol. 28, No. 12, 2007

0.06

0.05

0.04

0.03

0.02

0.01

0.00

+ Vth

MOSFET: Alternative for E-mode Operation

NCTU CSDLab

• UCSB(2004), Toyota Motor(2007), ROHM Co.(2008) and Sumitomo Electric Industries(2010) have reported the vertical devices.

• Advantages: ease of packaging with heat release, reduction of wafer area, free of the surface traps (current collapse).

• The current collapse becomes remarkable under high voltage operation

AlGaN

n--GaN

SG

S

n-GaN substrate

D

p-GaN p-GaN

HT-SiO2

Source: Toyota Central R&D Labs. (JJAP, Vol. 46, No. 21, 2007) Source: UCSB. (JAP, Vol. 95, No. 4, 2004)

Constant voltage contour lines

Vertical Device

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NCTU CSDLab

Published Data of Vertical DevicesBV On-resistance Vth Reference

UCSB 200 V 2.5 mΩ-cm2 Device Research Conference (2010)

Toyota Motor 2.6 mΩ-cm2 -16 V Jpn. J. Appl. Phys. 46 (2007)

RHOM Co. 9.3 mΩ-cm2 App. Phys. Express 1 (2008)

Sumitomo Electric 672 V 7.6 mΩ-cm2 +0.3 V App. Phys. Express 3 (2010)

Challenges: Cost of GaN substrateEpitaxial quality (threading dislocation)

Vertical devices have a great potential for power switching applications; however, the development of the vertical devices is quite primitive, making it impossible to evaluate the vertical device performance precisely.

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• GaN electronic devices on Si substrate are promising choices for future high power switching applications.

• AlGaN/GaN heterojunction possesses high electron concentration due to its strong polarization effect and high breakdown due to the large bandgap.

• Multiple AlN and AlGaN buffer layer structure is useful to reduce the stress and to improve the crystal quality of GaN grown on Si substrate.

• Field plate technique helps to reduce current slump and to increase the breakdown voltage.

• High efficiency power electronic circuits using GaN HEMTs as switching devices have been demonstrated.

• Enhancement-mode HEMT is required for EV power device applications.

• New GaN device structures have been demonstrated for future E-mode power applications

Summary

85