Green Technology Research Center Droop, ESD and Heat dissipation of Flip-Chip Power LEDs Prof. Liann-Be Chang Vice Dean & Director Engineering College

Green Technology Research Center

Droop, ESD and Heat dissipation of Droop, ESD and Heat dissipation of Flip-Chip Power LEDs Flip-Chip Power LEDs

Prof. Liann-Be Chang Vice Dean & DirectorVice Dean & Director

Engineering College Engineering College

Green Technology Research Center (GTRC)Green Technology Research Center (GTRC)

Page 2 Green Technology Research Center

Outline

Epitaxial technology

LED process technology Flip Chip technology


MOCVD 磊晶設備

2 sets of MOCVD ( Nippon Sanso)

1 set of MOCVD ( Aixtron)


MOCVD 附屬設備

氮氣儲存房

層流台＆防潮櫃特殊氣體房

氫氣儲存房JPC 廢氣處理塔

廢氣處理塔


MOCVD 附屬量測設備

金相顯微鏡

高解析度 X 光繞射儀

可對磊晶片做初步的表面分析

可快速對成長完之磊晶片做精確的晶格結構分析


化合物半導體製程無塵室


綠色科技研究中心製程實驗室


圖形化基板技術


LED 晶粒製程設備

Flip-Chip Bonder Wafer Bonding Bonder


Wire & Bump Bonder


LED 標準亮度量測系統

IS-250 ( 直徑 25cm) Keythley2420


積分球燈具量測系統

SLM-20T ( 直徑 50cm)Agilent E3634A (50V;4A)


LED 光學量測系統

穿透反射量測儀 LED遠場角量測儀


紅外線熱影像量測儀

SC620顯微鏡頭 :25um

測溫範圍 :-40~1500o


LED 熱阻量測分析儀

Operating Current (mA)

Forward Volt. (VF)

ΔTj-a (oC)


Apparatus(1F)3 sets of MOCVD ( Nippon Sanso + Aixtron)

MOCVD


Apparatus(9F) Measurement Equipments

Device Process Equipments

Clean Room


Methodology used in GTRC to Improve LED Performance

Method Enhance luminance Thermal reliability ESD

Epi-

growth

Patterned Sapphire Substrate Ⅴ

ZnO Template on Sapphire Ⅴ

DH LED prevent droops Ⅴ .

Chip

process

Surface textured Ⅴ

Bottom Metal reflector Ⅴ

Micro Channel/Photonic crystal Ⅴ

Top TCO layer Ⅴ Ⅴ

BondingWafer bonding Ⅴ Ⅴ Ⅴ

Flip- chip bonding Ⅴ Ⅴ Ⅴ


MOCVD epitaxial technology


Low Temperature n-GaN LED Structure

Sapphire

GaN nucleation layer, 25 nm

u-GaN, 2 um 1130 oC

n-AlGaN/GaN SLs, 2/2 nm 1130 oC × 5 pairs

n-GaN, 2 um 1130 oC

LT-n-GaN underlying layer, 0, 30, 50, 70, 140 nm

845 oC

InGaN/GaN MQW, 2/10 nm795/845 oC × 5 pairs

p-AlGaN/GaN blocking layer, 2/2 nm 980 oC × 20 pairs

P-GaN, 20 nm 980 oC

Inserting LT n-GaN layer


Optical & Electrical Characteristic

n-GaN

thickness20 mA

0 nm 5.595E-7

30 nm 6.093E-7

50 nm 6.364E-7

70 nm 6.744E-7

140 nm 4.966E-7


Pattern Sapphire Substrate LEDs

PSS

GaN nucleation layer, 25 nm

u-GaN, 2 um 1130 oC

n-AlGaN/GaN SLs, 2/2 nm 1130 oC × 5 pairs

n-GaN, 2 um 1130 oC

LT-n-GaN underlying layer, 70 nm 845 oC

InGaN/GaN MQW, 2/10 nm795/845 oC × 5 pairs

p-AlGaN/GaN blocking layer, 2/2 nm 980 oC × 20 pairs

P-GaN, 20 nm 980 oC

平台 (flat-top)

三角形 (pyramid)


Optical & Electrical Characteristic

2 times

SampleAve. center wavelength

at 20 mA

Ave. LOP (mcd)

at 20 mA

conventional 464.0 80.8

三角形 (pyramid)

465.65 147.51

平台 (flat-top) 467.72 180.74

74% up


Epitaxial Growth : LED on ZnO TemplateEpitaxial Growth : LED on ZnO Template

Sapphire

LED structure

ZnO buffer (300 nm)


Improving the luminescence by selective activation or ion implantation


Reflectance and Contact Resistanceof Ni/Ag-Based Metal Contacts on p-Type GaN

Ni/Ag

Ni/Ag/Au

Ni/Ag/Ti/Au


Micro Channel LED


Electron confine (blocking) effect

For sample B, except an additional 20-nm-thick p-type Al0.25Ga0.75N EBL inserted between the active layer and the p-type AlGaN/GaN superlattice structure to enhance the electron- blocking effect, the other growth conditions and structures were the same as those for sample A.The light-output power of sample B increases more rapidly and becomes greater than that of sample A in the measurement range from 25 to 130 A/cm2.

Applied Physics Express 3 (2010)


Electron decelerating effect

Appl. Phys. Lett. (2010).Appl. Phys. Lett. (2010).


Efficiency droop research by double-hetero structure LED


Wafer Bonding Technology

At present, wafer bondingtechnology is used widely


The proposed FlipThe proposed Flip-Chip Structure on MOS submount

use MOS heat sink & ESD protecting substrates heat flow can through the submount

with high thermal conductivity material

high reflect material heat


Core Technology : Pick/Place and U.S. Bonding


Top View of Flip-Chip Power LED


PN Junction & MOS Structure Submount

Conventional FCLED on PN Junction Submount

The Proposed FCLED on MOS Protective Submount


ESD Handling Capability

Non flip-chipped LED FC-LED on PN junction


ESD Handling Capability

FC-LED on MOS

Zc = 1/jωc is small for large capacitance submount


Output Power Intensity

Non Flip-chip LED luminance would be saturated at a large current injection

The best performance was flip-chip LED on AlN submount because AlN had higher thermal conductivity than Si


Flip-Chip AC-LED

We can easily design an 24 V AC-circuit directly on the submount through FC technology


Different LED chip on Si substrate thermal analysis

Si Substrate

Thermal ImageCLED FCLED (20 gold

bumps)VLED

CLED FCLED VLED

69oC

78oC


Remote Phosphor


Researchers from Taiwan’s Chung-Gung University have determined the diffusion mechanism into GaAs….

Sep,2007


Thank you for your attention

Documents

Green Technology Research Center Droop, ESD and Heat dissipation of Flip-Chip Power LEDs Prof. Liann-Be Chang Vice Dean & Director Engineering College