Yu cu:Sinh vin vit code v bin dch chng trnh

Vo netlist kim tra mch

Chy m phng kim tra kt qu

xem v d minh ha i y (design decoder2to4)xem v d minh ha i y (design decoder2to4)

V du: module cua Haft Adder

4

VD: cau truc Mux 2 to 1

VD: cau truc Mux 4 to 1 s dung Mux 2 to 1

VD: thiet ke MUX 4 to 1 dung cau truc phan cap

//module top

module mux4to1(q,sel,a,b,c,d);

input [1:0] sel;

input a,b,c,d;

output q;

wire tmp1,tmp2;

//module instantiation

module mux2to1(q,s,a,b);

input s,a,b;

output q;

wire selbar,a1,a2;

wire tmp1,tmp2;

mux2to1 M0 (tmp1,sel[0],a,b);

mux2to1 M1 (tmp2,sel[0],c,d);

mux2to1 M2 (q,sel[1],tmp1,tmp2);

endmodule

not(selbar,s);

and (a1,selbar,a);

and (a2,s,b);

or (q,a1,a2);

endmodule

V du:

V du2:

Hy ch ra v tr cc bin

wire trn s mch

V d: m t mch logic sau dng dataflow model

V d: m t Mux4_to_1 dng dataflow model

V du: mux2to1 dung dataflow model

V d: m t Mux4_to_1 dng dataflow model

V du: m t mch cng 4 bit dng dataflow model