HDL Debugging with Debussy Jul. 2004 - search …read.pudn.com/downloads58/sourcecode/embed/206147/debussy0407… · ... Finite State Machine Extraction and Analysis Tool ... Debussy

財團法人國家實驗研究院國家晶片系統設計中心

HDL Debugging with Debussy

Jul. 2004

© 2000, Novas SoftwareDuplication, reuse or transfer of ownership requires advance written authorization Page 1

Module 1 OverviewModule 2 Design UnderstandingModule 3 Watch WaveformModule 4 Debug with Simulation ResultModule 5 Misc.Module 6 nLint

財團法人國家實驗研究院國家晶片系統設計中心

HDL Debugging with Debussy

Jul. 2004


Module 1 OverviewModule 2 Design UnderstandingModule 3 Watch WaveformModule 4 Debug with Simulation ResultModule 5 Misc.Module 6 nLint

NOVAS Software, Inc.

for complex ICs, ASICs & Systems

The Engineer’s Desktop™The Knowledge-Based ™

HDL Debugging &Analysis Environment


Module 1 OverviewModule 2 Design UnderstandingModule 3 Watch WaveformModule 4 Debug with Simulation ResultModule 5 Misc.


Introduction to DebussySupported Simulators and File FormatsLicenseEnvironment SetupInvoke DebussyCommon User Interface


FSDBFast Signal Database

Gate Level SourceHDL Simulator VCD

File

FSDB R/W APICLDBCompact HDL

Language Database

nTrace

Debussy

nSchema nWave

nState

Debussy PLI Routines

High Level HDL Source Code


Debussy - A Complete HDL Debugging EnvironmentFour Key Components

nTrace -- Hypertext Source Code Analysis and Browse ToolnWave -- Universal Waveform Analysis ToolnSchema -- Debugging-Oriented Hierarchy Schematic GeneratornState -- Finite State Machine Extraction and Analysis Tool

Supported PlatformsSUN SOLARIS 2.5 or laterHP-UX 10.X IBM RS/6000 4.X or laterLinuxWindows NT


Supported Verilog Simulators through PLI/VCD filesCadence Verilog-XL 2.X or laterCadence NC-VerilogViewlogic VCS 3.X or laterModel Tech ModelSim EE/Plus 5.1 or laterAvant! PolarisQuickturn SpeedSimAXISSureFire


Supported VHDL simulators through FLI/FMI/VCD filesCadence LeapfrogCadence NC-VHDLModel Tech 5.x or later

Support Mixed Language SimulatorsNC toolsModel Tech 5.x or later

Supported Simulators through VCD filesFintronic FinsimAny simulators that can generate VCD file


Other Simulators (time domain format only)Synopsys (EPIC) Timemill and Powermill (.out)Avant! HSPICE and STAR-SIM (.trX)Silvaco SmartSpice (.raw)

Direct read / Translate to FSDBDirect read : No translation effortTranslate to FSDB : less memory usage and thus better performance in nWave


Add binary to the search pathsetenv NOVAS <install_dir>set path=($NOVAS/bin $path)

Specify search path of license filesetenv LM_LICENSE_FILE <license_file>:$LM_LICENSE_FILE

Specify ASIC symbol library & pathsetenv TURBO_LIBS “<ASIC_NAME#1> <ASIC_NAME#2> .…”setenv TURBO_LIBPATHS “<Directory#1> <Directory#2> …”

/home/debussy/share/symlib/artisan_u.lib++/home/asic1/lib/faraday_l.lib++

% setenv TURBO_LIBS “artisan_u faraday_l”% setenv TURBO_LIBPATHS “/home/debussy/share/symlib /home/asic1/lib”


Invoke Debussy by command :

debussy [<options>] [<source files>]

Some options : - vhdl | verilog : specify language type for import design from source (verilog by default)

- top <topModule> : specify top module for import design- lib <libName> : specify library name- f <fileName> : specify a file which list all source files


Debussy takes all the simulator command line options.

Invoke Debussy the same way as you invoke Verilog:

debussy [<your verilog options>]

Use Makefile fileAdd Debussy to your Makefile with the same options as you run Verilog.Extract all the options from verilog.log file and save them to an option file like run.f.You can invoke Debussy by : debussy -f run.f


Select with Mouse -- Always use Left Mouse ButtonClick the LMB to select single design objects like signals, instances, ... Hold the Shift key and click the LMB to add object to selection list.Drag LMB through an area to select the objects enclosed.

Drag & Drop with MousePerform the cross window operations.Press and hold the middle mouse button, then drag the selected objects and drop to the destination window.Press and hold the Right Mouse Button, then select the Drag/Drop command.

Context Sensitive Menu with Right Mouse ButtonContext sensitive with the object be pointedClick Right Mouse Button and select command.


Import DesignTraverse DesignTrace Driver and LoadSchematic ViewPartial SchematicFSM Extraction


SourceWindow

HierarchicalBrowser

MessageWindow


Two ways to import designFrom library From file

Why design libraryUse library in VHDL design Batch mode compilation for Verilog / VHDLVerilog incremental compilationMixed language design (Compile two languages into the same database)


Compile VHDL / Verilog code to libraryUse vhdlcom to compile VHDL source code to libraryUse vericom to compile Verilog source code to librarySyntax

vericom / vhdlcom [<options> ...] [<files>]Options -lib <libname> : the library name which design is compiled into.(default: work)

Example:vhdlcom –lib asic025 –93 -f cells.fvericom –lib work –inc –f run.f


Command line Specify library : -lib <libname> (default : work)Specify top : -top <cell name>+e.g. debussy –top “work.system work.cpu”

GUI modeFiles->Import Design->From LibrarySelect top scope from the list of Design Unit


Need library mapping before compiling VHDL design for which use library in it

Map library logical name to physical location in debussy.rcSyntax

[VHDL_libraries]logical name = physical location

Example@debussy rc file Version 1.0 ...[VHDL_libraries]work = ./work.lib++vital = ./work.lib++asic = ./asic025.lib++


VHDL Library Define Syntax- Example:

library IEEE;use std.standard.all;use IEEE.std_logic_1164.all;use vital.functions.all;“IEEE” and “vital” are logical library name

Search sequence of rc files:- (Setting in latter file will overwrite in former one)

1. <product>/etc/debussy.rc2. $HOME/debussy.rc3. ./debussy.rc


Language format- VHDL-87- VHDL-93- Verilog

Select source files or the file list to “Add”

Top Design UnitVerilog : Find top scope automaticallyVHDL : a design unit list window will pop up for user specifing top scope after compilation.


Update design in Debussy databaseUse Files->Reload Design if design is changed.Re-compilation

From File : all source files will be re-compiledFrom Library :

VHDL - incremental compile modified files by defaultVerilog - incremental compile modified files with -inc

Reload Design command will update nTrace, nSchema with new design and reload waveform data in nWave.


Expand/Collapse design tree by clicking on the Plus / Minus icon

The Open Folder icon indicate the current scope displayed in the source window.

Double click on a design unit to view the content in the source window.

Traverse Design - Hierarchy Browser

Different icon for unused task/function


Pop view up from portSelect a port of a design unitTrace->Pop View Up From Port

Push view in from portSelect a net connects to the port of an instanceTrace->Push View In From Port


Color-coded source code display with built-in syntax-directed checker and editor.Cursor will become a hand-sign when falling on an instance, module ,task or signal.Double click to hyperlink between design unit definition and reference. Double click on a signal name to find the driver.The color can be changed in Tools->PreferencesDisplay Parameter or Variable Defines with tips.


Quick Locating Strings in Source Window

Search in current file Use Find String on toolbar with case sensitive.

Search in all files / current fileUse Source -> Find String… to find with case sensitive / insensitive.


Double click on a signal to trace its driver.Click on Trace Load or Trace Driver icon to trace the selected signal's driver or load.Trace history to keep track of the last 32 trace results; Forward and Backward commands to recall.Use Show Next/Previous to cycle through the driver/load in the current Scope.If there are multiple drivers located in multiple instance, click on Show Next/Previous Instanceicon to cycle through them.


Forward History

Trace Driver

Trace Load

Show Next

Show Previous

Show Previous Instance

Show Next Instance

Backward History


Select an instance in Hierarchical Browser and click on New Schematicicon

A nSchema window will be opened and the content of the instance is displayed. (hierarchical schematic)

D&D an instance from Hierarchical Browser to icon

You can execute View->Schematic View in nTrace to use the nSchemaas the main window, which includes the Hierarchical Browser.

You can execute Tools -> New Schematic in nTrace and nSchema to invoke nSchema in different view.

Hierarchical, full scope schematic

Hierarchical, partial schematic

Flatten, partial schematic


nSchema will generate RTL schematic for your RTL Design from synthesis point of view.

nSchema will generate a hardware meaning symbol for each RTL statement (either continuous assignment or always block).

The RTL block will represent the following thingsBlock type -- latch, flip-flop or combination logicSignal type -- clock, reset, set, flip-flop output, latch output

or tri-state output



Tools -> Options -> Preferences -> Schematics -> RTL Extraction -> Detail RTL

Detail RTL

Same schematic as 4.4


• Double click on an bottom level RTL Block will bring up the corresponding source code in an INFORMATION dialog box.

• Directly Drag&Drop a schematic object to nTrace will display the corresponding source code.


• Select obejcts(instance, signal …) that you want to view.

• Directly Drag&Drop objects into Full Hierarchical Window will

change to corresponding scope and highlight them.

• Directly Drag&Drop objects into partial schematic will add them.


Schematic -> Find In Current Scope... finds signals or instances in current scope from the list.Schematic -> Find Singal/Instance… finds signals or instances in whole design.Schematic -> ViewMark


Three kind of schematic windows supported• Full Hierarchical Window – show complete objects in

specified scope• Browser Window – show partial schematic in specified

scope.• Flatten Window – show partial schematic in flatten view

Full Hierarchical Window

Flatten Window

Browser Window


View partial schematic of full design(cross hierarchy).Focus on a specified primitive for debugging -Select a primitive and Tools->New Schematic->Flatten Window

Focus on a specified net’s driver/load or path -Select a net and Tools->New Schematic->Driver / Load /

Connectivity / Fan-In Cone / Fan-Out ConeDouble click on instance pin to expand driver/load.Select object and use <Delete> key to remove object from schematic.

Trace net to register/tri-state or design boundaryFan-In Cone – useful to show all logics that affect the specified netFan-Out Cone – useful to show the clock tree


Trace All Paths Between Two Points

Specify two points by entering the net names or D&D from the schematic.The results are shown either directly in the schematic or in a generated partial schematic.

Trace from one instance’s output port to another instance’s input port.

1-process, 2-process, or 3-process with conventional encoding of the state variable.

2-process example on right.

module FSM_2Proc (clk, rst, a, b);input clk, rst, a, b;reg [1:0] cs, ns;parameter [1:0] S0=2'b00, S1=2'b01,S2=2'b10, S3=2'b11;always @(posedge clk or posedge rst)

if (rst)cs=S3;

elsecs=ns;

always @(a or cs)begin

ns=cs;case (cs)S0 : if (a) ns=S1;S1 : ns=b ? S2 : S3;S2 : ns=S0;S3 : if (a & b) ns=S2;default: ns=S0;endcase

endendmodule


Double click on the state block to invoke nState.Option to view logic gates instead of bubble diagram:View -> Viewing Mode -> No FSM


View -> State ActionView -> Transition ConditionView -> Transition Action


OverviewDisplay Simulation Result

Open a simulation output file and Get signal waveformBus OperationsSearch - Value, Constraint, Label MarkerSignal Processing - Logical Operation, Complex Event

ComparisonAnalog Waveform

OverlapAnalog Expression


Click on the New Waveform icon to invoke nWave.You can invoke standalone nWave under UNIX by typing:

Unix% nWave


Screen and Mouse Buttons Definitions

Mouse in Signal Window- LB: select/deselect Signal/Group- MB: move Signal Cursor Position- RB: Invoke Context Sensitive Menu- LB Double Click on a Group Name

to Expand/Collapse Group- LB Double Click on a Bus Name

to Expand/Collapse Bus

Mouse in Value Window- RB: select bus value display format

Mouse in Waveform Window- LB: Set Cursor Position- MB: Set Marker Position- RB: Zoom Cursor- LB Drag: Zoom Area

Mouse in Full Scale Ruler- LB: Set Cursor Position- MB: Set Marker Position- LB Drag: Zoom Area

To Resize Signal/Value Window- LB Drag on Window Boundary

Signal Cursor Position

SignalWindow

ValueWindow Full Scale Ruler Scroll Bar

Tool BarCursorPosition

MarkerPosition Delta

Pull Down Menu Zoom Scale Ruler


ZoomDrag the area you want to seeFast zoom on the Full Scale Ruler Zoom CursorZoom Out, Zoom In(2X), Fit

PanLeft, Right, Up, Down with menu command or bind keysPan to the area cursor at the centerPan to the area marker at the centerWith scroll bar

Last ViewUse View -> Last View command


Open an FSDB file which is generated by Verilog simulator (through PLI) or Debussy's translator. The default extension for FSDB file is .fsdbIf you open a simulator output file in VCD or SmartSpice format, nWavewill invoke the conversion utility vfast to translate it to an FSDB file with an file extension .fsdb. nWave will open the new FSDB file automatically.

If you open a simulator output file in Spice binary format or Powermill / Timemill format, nWave can either read it directly or translate into FSDB.

Can open several files in the same window

Use the File-> Set Active... to specify which file is activeYou can convert a VCD file to FSDB file in UNIX environment:

vfast <VCD File> [options]


Load FSDB with specified time range

Note : Need Debussy 5.0 format FSDB


Use Signal -> Get Signals... CommandDirectly Drag & Drop signals from nTrace or nSchema to nWave.Select objects and use Add Select Set To Wave in nSchema.Use trace command and then Add Result to Wave in nSchema.

double click on signal or click “Add” button to get signal


Generate waveform for VHDL variable

Approach 1 : fsdbDumpVariable FLIDump to FSDB file directlyNeed to specify the variables separatelyThe naming rules of variables are different between different simulators (ModelSim and NC-VHDL)Ex: fsdbDumpVariable /system/line__85/flag


Generate waveform for VHDL variable

Approach 2 : Calculate variables’ value by DebussyLoad FSDB fileCalculate value of the selected variable by its related signals / variablesOnly support in D&D from nTrace to nWave


Display Bus Value byWaveform -> Signal Value Radix -> Binary, Octal, Hexadecimal, Decimal, ASCII, Alias

Waveform -> Signal Value Notation -> Unsigned / Signed 2's Complement / Signed 1's Complement

Add Alias to Selected BusA Sample Alias File

ADD 8’h00SUB 8’h11 Display SUB instead of 11 on Waveform and Value WindowJMP 8’h12

Create BusFormed from the selected signals to create a new bus inserted at the signal cursor position.

Expand BusDouble click on a bus name to expand / collapse the bus.


Record multiple alias tables in the same file. Easy to choose alias table for a specified signals.Easy to edit alias table through GUI.


Use Waveform -> Signal Value Radix -> Browse Alias ...command to invoke it.Open Auto-created alias table automatically.

Click OK to apply alias for selected signals

Browse different

Alias Tables


You can search bus value and signal transition.For bus signal, use Waveform -> Set Search Value… .For analog signal, use Analog -> Set Search Analog Value… .Search value takes alias.


Use Waveform -> Set Search Constraint… .You can set the width of searched value.Useful for searching glitch (width <= 0).


Labels always visible at the top of curve window

Support Multiple markersUser-defined label for each markerWaveform Marker…


Logical Operation... command creates a new signal from other signals.


Event/Complex Event Search Function as Logic AnalyzerEditing specific Event

Signal->Event->EventEditing complex event from existed Event

Signal->Event->Complex EventSupport Save/Restore


Event/Complex Event Search (cont.)Display captured event on waveform.


Tools->New Waveform to open multiple nWaveWindow->Tile Waveform to tilewindowWindow->Sync. Waveform Viewto synchronize viewing of two windows in viewing area, cursor/marker positionWindow->Sync. Vertical Scrolling to synchronize signal viewing in vertical direction


Open 2 waveformLoad different simulation result to each windowUse Tools Waveform Compare to compare 2 signal /selected signals /2 groupUse Left / Right arrow on toolbar to step through the mismatch errors

mismatch


Conditional Comparison of WaveformsThree ways to define comparison base: clock,

cycle or expressionTools -> Waveform Compare -> Options…

One or two sets of condition signal settings

Support

Time range

Mismatch tolerance

Comparison stop control


Display digital signal value in analog form.- select bus signal and use Waveform -> Analog WaveformDisplay analog signal value in digital form.- select analog signal and use Waveform -> Digital Waveform


Overlay - Merge selected signals to one single signal inserted at the yellow signal cursor position bar.Two options, Auto Fit and Auto Color/Pattern supported.


Select analog signalsAnalog->Zoom Value


Use Analog Expression to process analog waveform.


Module 4 Debug with Simulation Result

List X / Trace XActive Annotation in nTrace / nSchemaActive Trace / Bus ContentionActive Fan-In ConeShow MemoryFSM Analysis


Find all the X of register and tri-state outputs from the simulation result

Organize the list of X signals by occurred time

Support filter the X signals by

time range

signals / scopes

X minimum width

Double clicking to invoke Trace X

(nTrace) Tools -> List X...


Extract X from the opened FSDB and save result

Load the designate signals from a list file

Load the designate scopes from a list file

Search Next/Previous


Support batch mode extractionxloc –o <output file> <FSDB file> [ other xloc options]

Support Save result / Load resultList X -> Build or xloc utility will generate binary format result. The extension name is .xloc.

List X -> Open File load the xloc file.


Generate partial flatten schematic to Show the X signalTrace driver to next register or tri-state outputAnnotate the value change

How to invoke Trace XDouble click on the report of List XMove cursor to the time point where the selected signal is X, and perform Tools->Trace X in nWave


Quickly find the cause of Unknown by one click


Active Annotation in Source Window

Use Source ->Active Annotation to annotate simulation result to source window.It will annotate the signal values at the cursor time and display the values under each signal.It will also display signal transition.Any signals can be annotated if they are dumped, no matter whether their waveform are displayed


You can select a signal in the source window and search its next or previous transition . The transition may be Any Change , Rising orFalling .

Execute the above commands will move the cursor time in nWave, nTrace and nSchema.

Active Annotation - Moving Cursor Time


Note: The waveform displayed hereis just for your reference. Theannotated signals are not necessarily displayed.


Invoke Schematic -> Active Annotation command to annotate the current signal values on nSchema.After turning on Active Annotation, the following icons will be enable on the nSchema toolbar.

You can select a signal first and use left / right icons to advance forward / backward the cursor time by value change, rising edge or falling edge.



Static Trace v.s. Active TraceStatic Trace – trace all the possible drivers based on connectionActive Trace – trace the real driver based on FSDB at the cursor time

How to invoke Active TraceDouble clicking on the waveform Active Trace in RMB menu in nTrace window

The real driving statementList all the drivers

and mark real driver

Double click to invoke Active Trace


Select a signal and invoke Tools -> Active Fan-In Cone togenerate Flatten Window with possible drivers in specified cycletime.

Select a signal and move Cursor Time to the time point that Unknown occurs and invoke Tools -> Trace X to generate Flatten Window with tracing X to next storage element.

Select a signal and move Cursor Time to the time point that Unknown occurs and invoke Tools -> Bus Contention to detect whether it is caused by Bus Contention.


Use List X in nTrace / nWave to list tri-state output which has value X.Double click tri-state bus in the list to invoke Trace X will generate Flatten Window to show the cause of X.

Use Tools -> Bus Contention in nWaveto show all the real drivers.


Show active driver in partial schematicSelect the signal which has multiple drivers in nWaveChange cursor time to where you want to find the real driverPerform Tools->Bus ContentionShow the partial flatten schematic of the real driver and annotate current value


Two situations need to find out X RegisterSimulation fail caused by timing violationSimulation fail caused by un-initialized storage element

How to Find out X RegisterUse List X in to list register output which has X.Double click on a signal in the list to invoke Trace X togenerate Flatten Window for this specified signal.Double click on instance port to expand driver.



Fan-In Cone v.s. Active Fan-In ConeTrace Fan-In Cone to extract partial schematic which contains all the possible logic that affect the signal

Back trace from here!


Active Fan-In Cone to trace the subset which have events occurred during specified period from the fan-in cone

Back trace the signal to find the driving logic had events during the last 200 ns


Use Debussy PLI $fsdbDumpMem to record memory contents in FSDB.Record memory contents only when $fsdbDumpMem is executed.Support changing value radix for memory value and address.

Binary to Hexadecimal


Search specified value at current time point.Click Search Next and Search Previous to find all fitted fields.

The field fits the pattern will highlight.


Show Memory Contents in nWave

Directly Drag & Drop selected memory to nWave.The operation of memory is same as that of individual signal.


FSM-> Analysis Reportto display a report.Inputs, Outputs, Clock and state signals report.State table list.Load simulation result to detect unreached state and state transition.Save to File commandprovided.


State Sequence Animation

FSM -> State Animation



nTrace : Tools -> Extract Interactive FSM…nSchema : Tools -> Extract Interactive FSM…Use State Animation in each nState window.



Save Session / SignalDebussy PLIStart Interactive Simulation ControlInvoke and Control SimulatorSet BreakpointsSet FocusStep Through Source CodeWatch SignalsUser-Defined CommandnLint


Save Session...– Save the debugging status to a session file which includes :

Displayed Waveform and Their SettingAll the Windows and Their ContentPreferenceBookmark

Restore Session...– Recover previous debugging status from a session file.


Save Signals - Save current displayed signals to an ASCII file for future restore.

Restore Signals - Display the signals with what you saved in the previous session.

Note:- If there is a file opened in nWave,

the Restore Signals command will ignore the Open command in theabove .rc file.

- Save Session command in nTracewill save the signals too.

- If there are signals created by other signals by user, the original signals must be kept.

Magic 271485Revision 1.0

; Window Layout <x> <y> <width> <height> <signalwiviewPort 5 30 960 332 102 67

; File list:; openDirFile [-d delimiter] [-s time_offset] path_name fopenDirFile -d / "/ae6a/evan/temp/Verilog/RTL" "deb44

; file time scale:; fileTimeScale ### s|ms|us|ns|ps

; signal spacing:signalSpacing 3

; windowTimeUnit is used for zoom, cursor & marker; waveform viewport rangezoom 0.000000 12500.000000cursor 6250.000000marker 4150.000000


PLI commands to Dump FSDB - Verilog

$fsdbDumpvars([<level>], <scope | signal>*) $fsdbDumpfile(“<FSDB name>”) $fsdbDumpMem(<reg name>, [<start addr>, [<size>]]) –Dump the contents of specified memories.

$fsdbSwitchDumpFile(“<new FSDB name>”) –switch dumping to another FSDB file

$fsdbAutoSwitchDumpfile(<file size>, “<FSDB name>”,< number of file>) –Limit FSDB file size and switch dumping to new FSDB file automatically

$fsdbDumpon - Turn on the FSDB dumping$fsdbDumpoff - Turn off the FSDB dumping$fsdbDumpflush - Force to Dump Result to FSDB file


Create library in working directorycd ~working_directoryvlib work

Copy novas.vhd into working directory and compliecp /usr/debussy/share/PLI/modelsim_fli53/SOLARIS2/novas.vhd \ ./novas.vhdvcom -work novas.vhd

Set environment variable for modelsim FLIsetenv LD_LIBRARY_PATH /usr/debussy/share/PLI/modelsim_fli53/SOLARIS2/:$LD_LIBRARY_PATH

Refer to the novas packageuse novas_lib.pkg.all;

.....fsdbDumpvars(0, "top");


Simulation Commands to Dump FSDB - VHDL

fsdbDumplimit - Limit FSDB file sizefsdbDumpfile - Specify FSDB file namefsdbDumpvars - Dump the specified scope.fsdbDumpSingle - Dump the specified signal.fsdbDumpvariable - Dump the specified VHDL variable.fsdbSwitchDumpFile - Switch dumping to another FSDB file.fsdbAutoSwitchDumpfile - Limit FSDB file size and switch dumping to new FSDB file automaticallyfsdbDumpflush - Force to Dump Result to FSDB filefsdbDumpMem - Dump the contents of specified memories.


fsdbextractextract partial content of original FSDB to new FSDB by scope or time range.% fsdbextract verilog.fsdb –s /system –level 1 \/system/I_cpu/I_ALUB –level 0 –o new.fsdb

fsdbmergemerge multiple FSDB into one FSDB file.% fsdbmerge 1.fsdb 2.fsdb –o all.fsdb

fsdbreportReport value change of the specified signal to a text file% fsdbreport verilog.fsdb –s /system/data –bt 0 –et 4000


Before You StartVHDL: You must link the FLI/FMIprogram provided by Debussy with your VHDL/Verilog simulator first.Note: Only support Modelsim, LeapFrog, NC_VHDL, Verilog_XL, NC-Verilog, Speedsim and VCS is supported at this release.

Please set simulator with Tools -> Options -> Preferences… command.


InteractiveToolbar

Start Interactive Mode

- Use Tools -> Interactive Mode to go to Interactive Mode.- A new toolbar will be added in nTrace.- Two menu Simulation and Debug will be added in nTrace.


Click on the Run/Continue icon to start Verilogsimulator. Verilog simulator will compile your design and go to Interactive Mode right away. Click on the Stop icon to stop your simulator while it is running.You can have the simulator run to some time by entering time value in the Time text field.Use Simulation -> Reset to reset simulator.Use Simulation -> Finish to finish simulation.Use Simulation -> Kill Simulator Process to kill the simulator process.


You can double click on the line number in source window to set a breakpoint.Double click on the line number again to delete the breakpoint.Use Debug -> Breakpoints to set and control breakpoints.


- You can use the above commands to step though your source code in different style.

- You can turn on Active Annotation to annotate signal values to source code. The values annotated will be updated in real time.

Next Unit Time Step

Next Event


Use Debug -> User-Defined Commands to bring up the user-defined commands window which contains the Verilog commands user defined.User can resize the window and place it anywhere.


Click on edit button to bring up editing user-defined commands window to add or edit commands.

The editing is effective right away and stored to your environment automatically.

Press <Insert> key to modify.


Button Name : The button name of this command shown on the command window.Command : The Verilog command.Keyword in Command Line :

${Arg:<String>} - With such keyword in Verilog command Debussy will pop up a form for user to enter a value , which is used as the argumentfor this command , while user click this command button.

${SelVars} - Use the selected signals in the source window as arguments.

${SelVar} - Use the selected signal (only one signal allowed) in the sourcewindow as arguments.

${treeSelScope} - Use the selected instance in Hierarchical Browser as argument.

\n - <CR Return> you have to add this at the end of your Verilogcommand if you want this command be executed immediately.

Note : Command is case sensitive


Example 1:

Next ? Time #${Arg:Next Time} $stop;.\n- When user push this command button the following form pop up.

- User needs to specify a number in Next Time Field and press OK.- For this example, Modelsim will run 1000 Time Unit and stop.


Example 2:

Force Variable Force ${selVar} = ${Arg:New Value};\n- User needs to select a signal in the source code window first and then

click this command button. A form will be popped up:

- User can specify the value to force signal.- For this example, Modelsim will force the selected signal to 1


Example 1:

Next ? Time #${Arg:Next Time} $stop;.\n- When user push this command button the following form pop up.

- User needs to specify a number in Next Time Field and press OK.- For this example, Verilog will run 1000 Time Unit and stop.


Example 2:

Force Variable Force ${selVar} = ${Arg:New Value};\n- User needs to select a signal in the source code window first and then

click this command button. A form will be popped up:

- User can specify the value to force signal.- For this example, Verilog will force the selected signal to 8'H00


HDL desing rule checker for Verilog/VHDLCreate syntax and semantics correct HDL codeEarly-stage checking of EDA tool compliant

Simulation, Synthesis, DFTTarget all abstract levels (behavior, RTL, gate-level)

Purify coding errors based on hardware meaning (ex: asynchronous loop, clock used as data, …)Enforce naming convention and coding style


Command line options:nLint {[GUI options]|[batch options]} [general options] [simulator options]GUI options: -gui (invoke with GUI mode)batch options:

-out <output_file>: ascii format of the checking result-df <file_name>: specify one source file not to be checked-dm <module_name>: specify one module name not to be checked-uf <file_name>: specify the file list not to be checked

general options:-rs <rs_file>: specify extra rule setting file-udr <udr_directory>: specify the location of the user defined rules

simulator options: same as Debussynotes:

-help: to list all optionsgeneral options: apply to batch and GUI modesbatch options: ignored by -gui option


Import DesignMain window

File -> OpenFrom command lines

Compile DesignClick hierarchyRun -> Compile

Suppress FilesSuppress module

RMB -> UnCheck


E/DRule enable / disable

TOFFsuppressed rule

Rule settingRule setting file (.rs)Default nLint.rs in <nLint_inst_dir>/etcnLint.rs in user’s home directorynLint.rs in working directoryThe file path in environment variable NLINTRSThe file path in command line option -rs


reportDB (File -> Save, File -> Save As ...)Binary database to save complete informationUser can load the result into nLint GUIDefault extension name is .rdb

violation listGeneral violation messages in ASCII formatFile -> Export Violation List …Batch mode: nLint -out <output_file>


NOVAS Software, Inc.

2025 Gateway Place, Suite 480San Jose, CA 95110

1-888-NOVAS-38 (1-888-668-2738)

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Printed on January 4, 2001.

Version

This manual supports Debussy 5.0 and higher versions.

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All rights reserved. No part of this manual may be reproduced in any form orby any means without written permission of:

NOVAS Software, Inc.2025 Gateway Place, Suite 480San Jose, CA 95110 U.S.A.

Copyright © 1996-2001 NOVAS Software, Inc.

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Debussy is a registered trademark and Knowledge-Based Debugging is atrademark of Novas Software, Inc.

The product names used in this manual are the trademarks or registeredtrademarks of their respective owners.

Restricted Rights

The information contained in this document is subject to change withoutnotice.

Contents

Laboratory 1 1Objective ............................................................................................................................. 1

1. Invoke and Quit Debussy.................................................................................. 12. Invoke Debussy with Importing a Verilog Design............................................ 23. Invoke Debussy with Replaying What You Had Done Before......................... 2

Laboratory 2-1 3Objective ............................................................................................................................. 3

1. Build Library from Map File. ........................................................................... 32. Bulid a Symbol Library from Synopsys .lib File. ............................................. 43. View Your Symbol Libraries. ........................................................................... 4

Laboratory 2-2 7Objective ............................................................................................................................. 7

1. Import Gate Level Design from File. ................................................................ 72. Set Library's Environment Variables and then Import Design from File again.83. Import Design from Library.............................................................................. 8

Laboratory 2-3 11Objective ........................................................................................................................... 11

1. Import Design from File. ................................................................................ 112. Import Design from Library............................................................................ 12


1. Import Design from File. ................................................................................ 152. Import Design from Library............................................................................ 15


1. Import Mixed-Language Design..................................................................... 172. Invoke Debussy with Importing Design from Library.................................... 17

Laboratory 3 19Objective ........................................................................................................................... 19

1. Compile a Mixed Language Design................................................................ 192. Import Design from Library to Debussy......................................................... 193. View Hierarchy and Traverse Your Design from Hierarchy Browser............ 204. From Source Code Window, You Can View Source Code, Traverse Design andTrace Signals' Drivers/Loads/Connectivity......................................................... 21

5. Understanding Your Design from nSchema ................................................... 236. Understand FSM from nState.......................................................................... 257. Quit Debussy................................................................................................... 25


1. Invoke Debussy with Importing Mixed Language Design from Library. ....... 272. Load Simulation Result................................................................................... 273. Display Signals' Waveform............................................................................. 284. Now We Assume the Transition from 3 to 55 of ALU[7:0] at Time 1051 WasWrong and We Have to Find Out the Real Cause(s). ......................................... 28


1. Invoke Debussy and Load the Gate-Level Design. ......................................... 332. The Signal in Question is carry_flag. ............................................................. 333. Load Gate-Level and RTL Simulation Results ............................................... 344. Display the Waveform of the Instance, carry_flag_reg. ................................. 345. Compare the Simulation Result ...................................................................... 356. Isolate the Problem.......................................................................................... 36


1. Run Verilog-XL Interactive Mode Simulation ............................................... 372. Invoke Debussy with the Verilog Design, then Choose Verilog-XL Simulator forRunning Verilog-XL Interactive Mode in Debussy. ........................................... 383. Set Breakpoints, Watch Interested Signals...................................................... 384. Run Verilog-XL Simulation............................................................................ 395. Re-Run Verilog-XL Simulation...................................................................... 40


1. Run NC_Verilog Interactive Mode Simulation............................................... 432. Compile and Elaborate the Verilog Design for NC_Verilog .......................... 443. Invoke Debussy with the Verilog Design ....................................................... 444. Use User-Defined Commands to Run the Simulation..................................... 45


1. Run ModelSim VHDL Interactive Mode Simulation ..................................... 492. Compile and Elaborate the Verilog Design for NC_Verilog .......................... 493. Invoke Debussy with the VHDL Design......................................................... 504. Use User-Defined Commands to Run the Simulation..................................... 51

Debussy 5.0 Hand-On Labs Laboratory 1 •••• 1

Laboratory 1

ObjectiveThis lab is purposed to give you a brief on invoking Debussy. Please execute each action of"%" below.

1. Invoke and Quit Debussy

STEP 1:Invoke Debussy.

% Debussy &

Note This action will open an nTrace window. Debussy will open a log directory,DebussyLog, to keep some information.They are Debussy.cmd and turbo.log. compiler.log will be opened if youimported a design into Debussy. You can invoke Debussy by % debussy aswell.

STEP 2:Quit the invoked Debussy.

% On nTrace's Pull-Down Menu, click File and then choose Exit.

Note We will use File->Exit for this kind of action later.

2 •••• Laboratory 1 Debussy 5.0 Hand-On Labs

2. Invoke Debussy with Importing a Verilog Design


% debussy -f run.f &

Note This will open a log directory, debussyLog. Under it, there are three log files,compiler.log, debussy.cmd and turob.log.


% File->Exit

3. Invoke Debussy with Replaying What You Had Done Before


% Debussy -play Debussy.cmd &


% File->Exit

Debussy 5.0 Hand-On Labs Laboratory 2-1 •••• 3

Laboratory 2-1

ObjectiveFor your owned or licensed cell libraries, you need to have symbol libraries before importingyour Gate level design into Debussy. With symbol libraries, Debussy recognizes the requiredproperties, such as, input/output/inout pins, clock and data pins of storage elements, thecontrol pin of tri-state and mux, etc.

By default, Debussy will reference two symbol libraries. They are

A. <Debussy_Inst_Dir>/share/symlib/default_l.lib++ and

B. <Debussy_Inst_Dir>/share/symlib/default_u.lib++

Under <Debussy_Inst_Dir>/p_symlib directory, there are some built standard cell librariesfor various foundries.

To build symbol libraries, we provide two approaches.

A. From map file and

B. From Synopsys's .lib file.

Below contains two examples of library building. Please follow each action of "%".

1. Build Library from Map File.

STEP 1:Use map2SymDB utility to build a symbol library.

% map2SymDB simple.map

Note This will build mapLib.lib++.

4 •••• Laboratory 2-1 Debussy 5.0 Hand-On Labs

STEP 2:Build symbol library with a designated library name and lowercased cell and pin name.

% map2SymDB -o simple_l -L -l simple.map

Note This will build simple_l.lib++ with lowercased cell and pin name. Please use -help option to know map2SymDB's use model.

2. Bulid a Symbol Library from Synopsys .lib File.

STEP 1:Use syn2SymDB utility to build a symbol library.

% syn2SymDB synopsys.lib

Note This will build SIMPLE.lib++, where "SIMPLE" is the declared library name insynopsys.lib.

STEP 2:Bulid symbol library and create a map file with a specified library name.

% syn2SymDB -m -o simple_u synopsys.lib

Note This will build simple_u.map, and simple_u.lib++. With -help option, you willknow syn2SymDB's use model.

3. View Your Symbol Libraries.

STEP 1:Replay the steps those had been done in the lab of importing RTL level design.

% Debussy -play replay.cmd &

STEP 2:View the built symbol library.

% On the opened schematic window (nSchema), press Shift+L.

% On the opened Load Symbol form, fill "." in Library Path and "simple_l" in LibraryName, then click OK.


Note On nSchema, you will find the symbols of "simple_l.lib++".

STEP 3:Quit Debussy.

% On nTrace window, File->Exit.

Note You can quit Debussy from nTrace window only. For other invoked windows,you can use File->Close to close them.


Laboratory 2-2

ObjectiveDebussy provides two approaches to import your designs:

A. Import design from file and

B. Import design from library

For Gate-Level Designs, you need to build your owned libraries and set two requiredenvironment variables properly to import your design correctly and view your design innSchema. Please execute each action of % below as the labs of Gate level design importing.

1. Import Gate Level Design from File.

STEP 1:Import gate level design through a pre-prepared run file.

% Debussy -f run.f &

STEP 2:View the compiled result from Debussy.

% On opened nTrace, File->View Import Log

Note The compiled result is stored in DebussyLog/compiler.log. Why there are somany errors? Those errors were caused by you did not set TURBO_LIBS andTURBO_LIBPATHS environment variables properly.


% File->Exit


2. Set Library's Environment Variables and then Import Design from Fileagain.

STEP 1:Set library's environment variables.

% setenv TURBO_LIBPATHS ../lab2-1% setenv TURBO_LIBS SIMPLE

STEP 2:Import gate level design.


STEP 3:View schematic.

% On Hierarchy Browser, Click + of i_cpu(CPU)

% Drag & Drop i_ALUB(ALUB) from Hierarchy Browser to New Schematic icon.

Note On the opened nSchema, you will see the schematic composed by the builtsymbols.


% On nTrace, File->Exit

3. Import Design from Library.

STEP 1:Compile gate level design.

% vericom -f run.f

Note This will compile the design into work.lib++.

STEP 2:Import design from pre-compiled library.


% Debussy -lib work -top system &

STEP 3:View the schematic view.

% On Hierarchy Browser, Click + of i_cpu(CPU)

% Drag & Drop i_ALUB(ALUB) from Hierarchy Browser to New Schematic icon




Laboratory 2-3

ObjectiveThis lab is purposed to give you a brief on importing a Verilog RTL design into Debussy.Please execute each action of "%" below.

1. Import Design from File.

STEP 1:Import design as the same way to run a Verilog simulation (specify all options and sourcefiles on command line).

% Debussy +dump+strength \../design_src/verilog/src/system.v \../design_src/verilog/src/pram.v \-v ../design_src/verilog/src/mem.v \../design_src/verilog/rtl/TopModule.v \../design_src/verilog/rtl/ALUB.v \../design_src/verilog/rtl/CCU.v \../design_src/verilog/rtl/PCU.v \../design_src/verilog/rtl/alu.v \../design_src/verilog/rtl/BJkernel.v \../design_src/verilog/rtl/BJsource.v

STEP 2:View the compiled result.

% On nTrace's message window, you will see the compiled result.

% File->View Import Log

Note The imported result will be kept in DebussyLog/compiler.log.


% File->Exit


STEP 4:Import design as the same way to run a Verilog simulation (specify all options and sourcefiles in a run file).


STEP 5:View the imported design.

% On Hierarchy Browser, click + of i_cpu(CPU)

Note After the action, i_ALUB, i_CCU and i_PCU will be expanded fromi_cpu(CPU).

% Drag&Drop i_ALUB(ALUB) to New Schematic icon

Note You will see meaningful symbols, such as mux and storage elements in theopened nSchema.




STEP 1:Compile the Verilog design.

% vericom -f ../design_src/verilog/rtl/run_rtl.f


STEP 2:Import design from library by the specified library name and root (or top) module.


STEP 3:View the imported design.


% On Hierarchy Browser, click + of i_cpu(CPU)

% Drag&Drop i_ALUB(ALUB) to New Schematic icon




Laboratory 2-4

ObjectiveThis lab is purposed to give you a brief on importing a VHDL RTL design into Debussy.Please execute each action of % below.

1. Import Design from File.

STEP 1:Import design from a run file.

% Debussy -vhdl -f run.f &

STEP 2:View the imported design on nSchema.

% On Set Top Module window, double click system to choose it as the top module.

% On Hierarchy Browser, click + of i_cpu(cpu(blk))

% Drag&Drop i_alub(alub(rtl)) to New Schematic icon


% File->Exit


STEP 1:Compile your VHDL design.

% vhdlcom -f run.f



STEP 2:Import design from library by the specified library name and top architecture.


STEP 3:View the imported design on nSchema.

% On the Import form, click system to choose it as the top design.

% On Hierarchy Browser, click + of i_cpu(cpu(blk))

% Drag&Drop i_alub(alub(rtl)) to New Schematic icon


% File->Exit


Laboratory 2-5

ObjectiveTo import mixed-language design, only importing from library is supported. First, you haveto compile your design into Debussy. Then import your mixed-language design from library.

A. Use vericom to compile all Verilog design files; and

B. Use vhdlcom to compile all VHDL design files.

Please execute each action of "%" below.

1. Import Mixed-Language Design

STEP 1:Compile Verilog part.

% vericom -f run_verilog.f

STEP 2:Compile VHDL part.

% vhdlcom -f run_vhdl.f

2. Invoke Debussy with Importing Design from Library

STEP 1:Import design from library by specifying the library name and root (or top) module.


Note We will have some more detail analysis to understand this mixed languagedesign later.



% File->Exit


Laboratory 3

ObjectiveThis lab will give you a brief scenario on design understanding. The design is in mixedlanguage. Please execute each action of "%" below.

1. Compile a Mixed Language Design

STEP 1:Compile Verilog source code.

% vericom -f run_verilog.f

STEP 2:Compile VHDL source code.

% vhdlcom -f run_vhdl.f

2. Import Design from Library to Debussy

STEP 1:Import design by the specified library and top module.


Note nTrace window will be opened. On nTrace, it contains three windows.

a. On the left side, it's the Hierarchical Browser to show design hierarchy.

b. On the right side, it's the Source Code window to display the design's content.

c. On the bottom, it's the Message window for reporting the result of operations.


3. View Hierarchy and Traverse Your Design from Hierarchy Browser

STEP 1:Collapse the design tree of system.

% Click at "-" which locates on the left side of system(blk).

Note "-" will be change to "+". From Source Code window, you can see system is inVHDL.

STEP 2:Expand the design tree of system.

% Click at "+" which locates on the left side of system(blk).

Note "+" will be changed to "-".

STEP 3:Expand the design tree of i_cpu and change the viewing scope of Source Code window toCPU module.

% Double click at i_cpu(CPU).

Note From Source Code window, you will know CPU is in Verilog.

STEP 4:Expand the design tree of i_ALUB(ALUB) and change the viewing scope of Source Codewindow to ALUB module.

% Double click at i_ALUB(ALUB).

Note On Source View Window, the scope will be changed to ALUB which is aVerilog module. Also, the tree of i_ALUB(ALUB) was expanded.

STEP 5:Change the viewing scope to arithlogic.

% Double click at i_alu(arithlogic(arithlogic)).

Note On Source View Window, design scope was changed to arithlogic which is aVHDL entity.


STEP 6:Change the viewing scope to CPU module.

% Double click at i_cpu(CPU).

4. From Source Code Window, You Can View Source Code, TraverseDesign and Trace Signals' Drivers/Loads/Connectivity.

STEP 1:Jump to the first instantiation.

% On Source Code window, double click at CPU in line 30.

Note On Source Code window, the design scope had been changed to line 107 ofsystem. Line 107 is the Verilog instantiation of CPU.

STEP 2:Jump to the module declaration.

% Double click at i_CPU on line 107.

Note Now, the design scope was changed back to CPU module.

STEP 3:Trace signal's drivers.

% Double click at data in line 35.

Note This action is used to find the drivers of the clicked signal. You can see all thetraced drivers are reported in the Message Window.

STEP 4:Trace the next or previous drivers in the same design scope.

% Click Show Next and then Show Previous icons.

Note This will jump to the drivers in the same design scope. For this case, it isi_pram(pram2(pram)).


STEP 5:Trace the next or previous drivers in different design scope.

% Click Show Previous In Hierarchy and then Show Next In Hierarchy icons.

Note This will jump to the drivers in different design scope.

STEP 6:Jump to the driver's location from Message Window.

% On Message Window, double click

*<D> ../design_src/mixed/vhdl/RTL/PCU_record.vhd(100): data <= n_q0;

Note This will directly jump to the driver you are interested.

STEP 7:Change the viewing scope to i_cpu.

% On Hierarchy Browser, double click icpu(CPU).

STEP 8:Select a signal, data[7:0] bus.

% On Source Code Window, click at data in line 35.

STEP 9:Add a bookmark.

% Source->Toggle Bookmark

STEP 10:Trace loads of data[7:0].

% Click Trace Load icon.

Note This will list all of loads that are drove by data. You can do STEP 4 ~ 6 tojump to the load in the same way as tracing signal's drivers.


STEP 11:Jump to the interested bookmark.

% Source->Bookmark->1

Note This will go back to line 35 of TopModule.v.

STEP 12:Trace the connectivity of data[7:0].

% On Source Code Window, click at data in line 35.

% Trace->Connectivity

Note This will trace all of connections of data and report them on Message Window.

5. Understanding Your Design from nSchema

STEP 1:Invoke nSchema window.

% Drag&Drop i_ALUB(ALUB) from Hierarchy Browser to New Schematic icon.

Note This will display RTL in schematic representation.

STEP 2:Know the content of extracted RTL symbols.

% Double click at any mux symbol

Note A View Source Code window will be opened to show the contents of thesymbol.

% Drag&Drop any mux symbol from nSchema to nTrace.

Note The respective code of the symbol will be highlighted and selected.


STEP 3:Select the signals those were selected in nTrace window.

% Drag&Drop the highlighted source code on nTrace to nSchema.

STEP 4:Jump to the marked bookmark.

% (nTrace)Source->Bookmark->1

STEP 5:Select data[7:0] bus again.

% On nTrace, click data in line 35.

STEP 6:Select data[7:0] bus on nSchema.

% Drag&Drop data from nTrace to nSchema.

Note On nSchema, the design scope will be changed from system.i_cpu.i_ALUB tosystem.i_cpu.

STEP 7:Push down the design hierarchy of ALUB

% On nSchema, double click at ALUB.

STEP 8:Pop up the design hierarchy.

% On nSchema, click PopView Up icon.

Note This will pop up design one level.

STEP 9:Generate the fan in cone logic of ALU[7:0] bus

% On nSchema, select second output from the top on the ALUB symbol.


% (nSchema)Tools->New Schematic->Fan-In Cone

Note The fan-in cone logic of ALU[7:0] will be displayed in another nSchemawindow. The fan-in cone logic is in flatten mode. Click any extracted symbolblocks to select them, you will know their design hierarchy.

6. Understand FSM from nState

STEP 1:Invoke nState from nSchema.

% On the first opened nSchema, click PopView Up icon until it reaches to system level.

% Double click at fsm_master symbol block

% Double click at the FSM symbol to invoke nState.

STEP 2:Show states' behave.

% Turn on (nState) View->State Action to display each state's action.

% Turn on (nState) View->Transition Condition to display each transition's conditions.

% Turn on (nState) View->Transition Action to display each transition's actions.

STEP 3:Show the FSM's properties.

% Turn on (nState)FSM->Machine Properties to display FSM's properties.

STEP 4:Show the content of a state.

% Drag and Drop ST0 from nState to nTrace's Source Code window to show its content.

7. Quit Debussy% (nTrace)File->Exit



Laboratory 4-1

ObjectiveThis lab will give you a brief scenario on how to debug your design with simulation result.Please execute each action of "%" below.

1. Invoke Debussy with Importing Mixed Language Design from Library.

STEP 1:Use the library pre-compiled for the lab of understanding you designs.


Note In debussy.rc file, the work library had mapped to../../understanding/work.lib++.

2. Load Simulation Result.

STEP 1:Invoke nWave window.

% On nTrace toolbar, click at New Waveform icon or Tools->New Waveform.

STEP 2:Load the simulation result.

% On nWave toolbar, click Open File icon or File->Open.

% On the Open Dump File, double click demo.fsdb to open it.

Note To load simulation result, you can do it from (nTrace)File->Load SimulationResult, too.


3. Display Signals' Waveform.

STEP 1:Get signals from FSDB's tree structure.

% Click Get Signal icon and then select some signals and OK.

STEP 2:Get IO boundary of i_ALUB.

% On Hierarchy Browser, click at "+" of i_cpu(CPU), then Drag&Drop i_ALUB(ALUB)to nWave.

4. Now We Assume the Transition from 3 to 55 of ALU[7:0] at Time 1051Was Wrong and We Have to Find Out the Real Cause(s).

STEP 1:Annotate the simulation result onto nTrace's Source Code window.

% (nTrace)Source->Active Annotation

STEP 2:Find out where is the transition from.

% On waveform window, double click at the transition from 3 to 55 of ALU[7:0] at time1051 ns.

Note This action will show you the active drivers of the signal at the transition onnTrace's Source Code window. For this example, it's line 96 ofi_alu(arithlogic(arithlogic)).

STEP 3:Calculate VHDL variables' value. (So far, none of VHDL simulators provide functions todump VHDL's variables).

% Drag&Drop result in line 96 from nTrace to nWave.


Note Drag&Drop a variable from nTrace to nWave, Debussy calculates VHDL'svariable value of the same process.

STEP 4:Find out all drivers of result.

% Double click on result in line 96 of nTrace.

Note There are 14 drivers reported on the message window. It will be timeconsumed if we trace back the logic of all drivers. Will you do that? Let's findthe real active drivers to reduce the efforts dramatically.

STEP 5:Find the real driver (active trace) of result (Please note, the time is 1051 ns now.).

% Click Backward History icon on nTrace toolbar for backwarding to STEP 4.

% RMB->Active Trace to find the real drivers of result.

Note RMB means click the Right Mouse Button. Now, result in line 65 was selected.It means the real driver is coming from this line.

Note There will pup-up a warning message since the time was changed back by1ns. The changed back was resulted from the delay of after 1 ns; in line 96.

STEP 6:Find the real drivers of the traced real drivers.

% Select a_var which is the real driver of result and RMB->Active Trace to find out thereal driver of a_var.

% Select "a" which is the real driver of a_var and RMB->Active Trace to find out thereal driver of "a".

Note signal "a" will be changed name to "X0" in ALUB.v since the designconnectivity.


Note You can do the active trace again. But, wouldn't it be great if we could see aschematic that shows only the logic driving "IDB" (the active driver of "X0"),indenpendent of hierarchy? Let see the following.

STEP 7:Generate the Fan-In Cone for "IDB".

% Select "IDB" in line 80 on Source Code window and then Tools->New Schematic->Fan-In Cone

Note An nSchema is opened with the logic driving "IDB". You can select someblocks to know they are from different hierarchy and in flatten mode.

STEP 8:Annotate simulation result on the generate Fan-In Cone window.

% (nSchema)Schematic->Active Annotation

STEP 9:Analyze the generated Fan-In Cone to find the real cause. Please zoom into regions thoseyou want to know the value of nets detailly by yourself.

% IDB is driven by a MUX, so you have to know the value of the select line in order toknow which input is active. The select line is 0 now, so the first (the topest) input is whatwe need to concentrate in advance.

% The top input of the MUX is coming from a storage element. Double click the input pinof the storage element to trace the logic back. It is another mux with the select line valueis 1.

Note Fan-In Cone will stop at storage elements, functional blocks, FSMs andprimary IOs.

% Double click at the second input of the MUX, it's a functional block.

% Double click at the input of the functional block, it's the logic drove by a tri-state.

% Select the output of the tri-state and then, generate another Fan-In Cone to makeschematic more clean by Tools->New Schematic->Fan-In Cone.

% On the newly opened nSchema, it's schematic with the output is drove by a tri-stateand memory component.

% Annotate simulation result from Schematic->Active Annotation.


Note The enable pin of the tri-state is low active and now its value is 1. So it meansthe output is driving by the memory.

STEP 10:Analyze the memory's content to know what resulted in the transition (from 3 to 55 ofALU[7:0]).

% Display memory content by (nTrace)Tools->Memory, File->Get Memory->Variableand Time->Sync Cursor Time.

Note You can step through time and see the memory values change.

% Steps forward or backward on the memory content window until time is 900ns.

Note On the second Fan-In Cone schematic window, you can see the output valueis 34->55 which is 55 coming from. This is the cause of ALU[7:0] changingfrom 3->55. (If you step forward on the memory content window again, thetime will shift to 1200ns that is not the cause since the timing is wrong.)


Laboratory 4-2

ObjectiveThis lab will give you a scenario on how to debug your design when you find un-matchesbetween RTL and Gate-Level simulations. Please execute each action of "%" below.

1. Invoke Debussy and Load the Gate-Level Design.

STEP 1:Build Gate-Level symbol library.

% syn2SymDB synopsys.lib

STEP 2:Set environment variable for the built symbol library.

% setenv TURBO_LIBPATHS .% setenv TURBO_LIBS SIMPLE

STEP 3:Compile the Gate-Level design.

% vericom -f run.f

STEP 4:Load the compiled design.


2. The Signal in Question is carry_flag.

STEP 1:Find carry_flag through a string search.


% (nTrace)Source->Find String, enter carry_flag. Deselect Match Case, choose In AllFiles, then click Find.

STEP 2:On the nTrace's message window, you can find carry_flag is the output of carry_flag_reg.

% On the message window, double click on the driver, TFD2.

Note This will figure out the position of the instance.

3. Load Gate-Level and RTL Simulation Results

STEP 1:From nTrace, invoke an nWave.

% Tools->New Waveform or click New Waveform icon.

STEP 2:Load Gate-Level simulation result.

% (nWave)File->Open->gate.fsdb

STEP 3:Open another nWave from the opened nWave.

% (nWave)Tools->New Waveform

STEP 4:From the newly opened nWave, load the RTL simulation result.

% File->Open->rtl.fsdb

4. Display the Waveform of the Instance, carry_flag_reg.

STEP 1:Drag&Drop the instance carry_flag_reg to both nWave windows.


% Drag&Drop carry_flag_reg from nTrace to both nWave windows

STEP 2:Tile and synchronous both nWave windows.

% On the Gate-Level nWave window, Window->Tile Waveform

Note You can tile windows on any nWave window.

% On the Gate-Level nWave window, Window->Sync Waveform View

% On the RTL nWave window, Window->Sync Waveform View

5. Compare the Simulation Result

STEP 1:Select carry_flag on both nWave windows.

% On the Gate-Level nWave window, select carry_flag.

% On the RTL nWave window, select carry_flag.

STEP 2:Compare the simulation result.

% On the Gate-Level nWave window, Tools->Waveform Compare->CompareSelected Signals

Note One error was reported and the Search By toolbar will be changed to SearchBy Mismatches.

STEP 3:Locate the mismatch.

% On the Gate-Level nWave window, click the right arrow toolbar.

Note The input to the register in Gate-Level design (carry) changes right around theclock edge to cause the mismatch.


6. Isolate the Problem

STEP 1:Show active driver of carry in nTrace.

% Double click on the rising edge of carry.

STEP 2:On nTrace, generate Fan-In Cone for carry.

% (nTrace)Tools->New Schematic->Fan-In Cone

Note It will take couple seconds since the Fan-In Cone is big.

STEP 3:Since there are too much logic, we need to reduce it to easily analyze.

% On the Gate-Level nWave, select carry and the rising edge, then Tools->Active Fan-In Cone, specify 10ns in Back Trace Time Period, then click Apply button.

Note Now, the Fan-in cone logic had been reduced and it is very clean for you todo further analyses.


Laboratory 5-1

ObjectiveThis lab will give you a scenario on how to control your Verilog-XL simulation in Debussy.Before your start, modify ../../SOURCEME to set your working environment properly. In thislab, Solaris2 platform will be taken as the working platform. Please execute each action of"%" below.

1. Run Verilog-XL Interactive Mode SimulationYou have to link Debussy provided PLI to Verilog-XL by Cadence's vconfig utility. Thecr_vlog_sol2_dym file is the pre-prepared configure file. In the file, it marked how toconfigure vconfig to generate the shared libraries by a dynamic PLI linking at the beginningof the file. Also, to execute cr_vlog_sol2_dym to generate shared libraries, you have to set thecorrect environment variable for

a. CDS_INST_DIR, and

b. DEBUSSY_INST_DIR

STEP 1:Generate shared libraries for linking PLIs

% source ../SOURCEME% cr_vlog_sol2_dym

Note Two shared library libpli.so and libvpi.so will be created. For differentplatforms, the configured file and the generate shared libraries will bedifferent. Take HP as an example, it will generate libpli.sl and libvpi.sl.

STEP 2:Add the path of the shared library to LD_LIBRARY_PATH environment variable.

% setenv LD_LIBRARY_PATH /usr/dt/lib:/usr/lib% setenv LD_LIBRARY_PATH \.:$CDS_INST_DIR/tools.sun4v/lib:$LD_LIBRARY_PATH


2. Invoke Debussy with the Verilog Design, then Choose Verilog-XLSimulator for Running Verilog-XL Interactive Mode in Debussy.

STEP 1:Invoke Debussy with the Verilog design.


STEP 2:Choose the simulator to Verilog-XL and control the simulation to stop at 0 initially andremember the Breakpoints.

% Tools->Options->Preferences->Simulation->Verilog-XL

% Turn on Stop At Time 0

% Turn on Remember Breakpoints For Next Simulation

% Click OK button.

Note If you run the simulation under the same directory, the setting will be kept untilyou modify it. (The setting is kept in ./debussy.rc file.)

STEP 3:Change Debussy's working mode to interactive mode.

% Tools->Interactive

Note The toolbar was changed to interactive mode's toolbar.

3. Set Breakpoints, Watch Interested Signals.

STEP 1:Set a line breakpoint.

% Double click at the line number 78 on line number section.

Note If you double click in line 78 on Source Code Window, this won't set the linebreakpoint successfully.


STEP 2:Set a conditional breakpoint.

% Debug->Set Breakpoints, double click i_cpu on Hierarchy Browser to change theviewing scope on Source Code Window to CPU, then Drag&Drop alu_mode in line 39 tothe Signal field, then click Any Changed button.

STEP 3:Set Time-based breakpoint.

% Fill in 350 in Time Field and click Break At Absolute Time button.

STEP 4:Watch some interested signals.

% Tools->Watch Signals

% Drag&Drop alu_mode in line 39 to the opened Watch window.

4. Run Verilog-XL Simulation

STEP 1:Compile the design.

% Click Run/Continue icon on the toolbar or Simulation->Run/Continue

Note You will see the design was compiled for Verilog-XL and some information,such as, opened verilog_i.fsdb and the pre-set breakpoints on messagewindow. In Watch window, value of the watched signals is NF.

STEP 2:Continue the Simulation.

% Source->Active Annotation

Note The value of all signals are NF (Not Found) since The simulation didn't startyet.

% Click Run/Continue icon.


Note The simulation is stop at line 78, the line break. In Watch window, the value ofall_mode[2:0] was changed from NF to X since the initialization had beendone.


Note The simulation still stop at 25 ns since the breakpoint, alu_mode changedfrom X to 0, occurred.


Note The simulation will stop at 350, the time-based breakpoint.

% Click Next Event icon

Note It stooped at line 69 of Bjsource.v, the time is 350 ns.

% Click Next Unit Time Step icon

Note It stooped at line 69 of Bjsource.v, but the time is 351 ns.


Note It stooped at 550 ns which was caused by alu_mode[2:0] was changed from 0to 3.

% Remove Any Change on system.i_cpu.alu_mode from Breakpoints window.


Note The simulation is terminated since it reaches 12500ns. The obviously declaredfinish time in line 70 of system.v.

5. Re-Run Verilog-XL Simulation

STEP 1:Compile the design.

% Click Run/Continue icon on the toolbar or Simulation->Run/Continue


STEP 2:Continue the Simulation.

% Source->Active Annotation


Note The simulation is stop at line 78, the line break.


Note The simulation will stop at 350, the time-based breakpoint since thebreakpoint of alu_mode[2:0] had been removed.


Note The simulation is terminated since it reaches 12500ns. The obviously declaredfinish time in line 70 of system.v.


% File->Exit


Laboratory 5-2

ObjectiveThis lab will give you a scenario on how to control your NC_Verilog simulation in Debussy.Before your start, modify ../../SOURCEME to set your working environment properly. Wewill use Solaris2 platform to go through the lab. Please execute each action of "%" below.

1. Run NC_Verilog Interactive Mode SimulationTo run NC_Verilog interactive mode simulation, you have to link Debussy provided PLI toNC_Verilog by customizing the Cadence provided Makefiles. You can get the originalMakefiles from <CDS_INST_DIR>/tools/inca/files directory. In this lab, we customizedthem for dynamic link already. To know how to customize the Makefiles, please look atDebussy's installation document.

To execute Makefile to generate shared libraries, you have to source ../../SOURCEME or setthe correct environment variable for

a. CDS_INST_DIR

b. INSTALL_DIR, and

c. DEBUSSY_INST_DIR

STEP 1:Generate shared libraries for linking PLIs.

% source ../SOURCEME% make -f Makefile.sun4v shared_libs

Note Two shared library libpli.so and libvpi.so will be generated. For differentplatforms, the customized options in Makefiles and the generate sharedlibraries are different. Take HP as an example, it will generate libpli.sl andlibvpi.sl.

STEP 2:Add the path of the shared libraries to LD_LIBRARY_PATH environment variable.


% setenv LD_LIBRARY_PATH /usr/dt/lib:/usr/lib% setenv LD_LIBRARY_PATH \.:$CDS_INST_DIR/tools.sun4v/lib:$LD_LIBRARY_PATH

Note For ncxlmode and ncverilog executable, you have to use the same flow to linkthe provided PLI.

2. Compile and Elaborate the Verilog Design for NC_Verilog

STEP 1:Prepare NC_Verilog working environment.

% ncprep -f run.f +overwrite

Note This will generatea. ncvlog.args for compilationb. ncelab.args for elaboration, andc. ncsim.args for simulation.

STEP 2:Compile Verilog design with -LINEDEBUG option to enable line breakpoint and showcurrent position.

% ncvlog -f ncvlog.args -LINEDEBUG

STEP 3:Elaborate Verilog design with -access +r to set default access visibility.

% ncelab -f ncelab.args -access +r

Note We won't run ncsim here since we will control the simulation in Debussy.

3. Invoke Debussy with the Verilog DesignInvoke Debussy with the Verilog design, then choose NC-Verilog simulator for runningNC_Verilog interactive mode in Debussy.

STEP 1:Invoke Debussy with the Verilog design.



STEP 2:Choose the simulator to NC-Verilog and control the simulation to stop at 0 initially andremember the Breakpoints.

% Tools->Options->Preferences->Simulation->NC-Verilog

% Turn on Stop At Time 0

% Turn on Remember Breakpoints For Next Simulation

% Click OK button.





4. Use User-Defined Commands to Run the Simulation

STEP 1:Start the simulation.

% Click Run/Continue icon

STEP 2:Open nWave window.

% Click New Waveform icon

% Drag&Drop i_cpu(CPU) from Hierarchy Browser to nWave

Note The signal's values are x or XX.

STEP 3:Edit User-Defined Commands.


% Debug->User Defined Commands

% Click Edit button on the opened User-Defined Commands form

% On the Editing form, click the left side of the secondary line

% Type Next 500 Time and then Enter key to change command from Next 1000 Timeto Next 500 Time

% Click the right side of the secondary line

% Type run 500 -relative\n and then Enter key to change command from run 1000 -relative\n to run 500 -relative\n

STEP 4:Add a User-Defined Commands.

% On the Editing form, click the left side of the bottom line

% Type Next Cycle and then Entry key

% Type Next 50 -relative\n and then Entry key

% Click OK

STEP 5:Run the Verilog Simulation.

% On User-Defined Command form, click Next 500 Time button

Note The simulation time is going to 500 ns and waveform of the displayed signalsis changing.

% Click Next Cycle button

Note The simulation time is going to 550 ns.

% Click Next > Time button and fill in 25, then OK.

Note The simulation time is going to 575 ns.

STEP 6:Finish the simulation.

% Click Run/Continue button


Note The simulation time is going to 12500ns that is the obviously declared finishtime in line 70 of system.v.

STEP 7:Terminate the simulation.

% Simulation->Finish


% File->Exit


Laboratory 5-3

ObjectiveThis lab will give you a scenario on how to control your ModelSim/VHDL simulation inDebussy. Before your start, modify ../../SOURCEME to set your working environmentproperly. Then execute each action of "%" below.

1. Run ModelSim VHDL Interactive Mode SimulationTo run ModelSim VHDL interactive mode simulation, you have to link Debussy provided FLIshared library to ModelSim. To Link the FLI, in ../../SOURCEME, please set the followingtwo variables properly.

a. DEBUSSY_INST_DIR, and

b. MTI_HOME

STEP 1:Link the provided FLI shared library to ModelSim by adding the path of the provided FLI toLD_LIBRARY_PATH.

% source ../SOURCEME% setenv LD_LIBRARY_PATH \ $DEBUSSY_INST_DIR/share/PLI/modelsim_fli53/SOLARIS2% setenv LD_LIBRARY_PATH /usr/dt/lib:/usr/lib:$LD_LIBRARY_PATH

2. Compile and Elaborate the Verilog Design for NC_Verilog

STEP 1:Use vlib to create work and novas library directories.

% vlib work

Note If work/ directory existed, please use rm -rf work to remove it.

% vlib novas


Note If novas/ directory existed, please use rm -rf novas to remove it.

STEP 2:Use vcom to compile design into modelsim's library directories.

% vcom -f run.f% vcom -work novas ../design_src/vhdl/src/novas.vhd

3. Invoke Debussy with the VHDL DesignInvoke Debussy with the VHDL design, then choose ModelSim simulator for runningModelSim interactive mode in Debussy.

STEP 1:Compile the VHDL design into Debussy library.

% vhdlcom -f run.f

STEP 2:Invoke Debussy with the VHDL design.


STEP 3:Choose the simulator to ModelSim and control the simulation to remember the breakpoints onnext simulation.

% Tools->Options->Preferences->Simulation->ModelSim

% Click OK button.






4. Use User-Defined Commands to Run the Simulation

STEP 1:Start the simulation.

% Click Run/Continue icon

STEP 2:Open nWave window.

% Click New Waveform icon

% Drag&Drop i_cpu(cpu(blk)) from Hierarchy Browser to nWave

Note Some signal's value are U or UU those are the initialized VHDL values.

STEP 3:Run the VHDL Simulation.

% Debug->User Defined Commands

% On User-Defined Command form, click Next 1000 Time button

Note The simulation time is going to 1000 ps since the time unit defined inmodelsim.ini is 1 ps.

% Click Next ? Time button and fill in 10000, then OK

Note The simulation time is going to 11000 ps.

% On the Message Window, in the VSIM n> prompt, keyin run 12500 ns, then return

STEP 4:Terminate the simulation.

% Simulation->Finish


% File->Exit

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