High-Frequency IC Design & Test Webinar Part 1 (Design) Proprietary / Page 3 Logistics! If you experience any technical difficulties, call WebEx technical support – (866) 779-3239

High-Frequency IC Design & Test Webinar

Part 1 (Design)

Inphi CorporationJune 24, 2003

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Inphi Proprietary / Page 2

Introduction! Why this webinar is important

– Attendees will learn innovative techniques for high-frequency and high-speed design. This seminar will give engineers access to experts who will share techniques applicable for design and test.

! What to expect– This webinar focuses on best practices for high-frequency and

high-speed design and test. Development engineers will present techniques for creating leading-edge products. All presentations cover actual product development and test results.

! Who should attend– Engineers developing instrumentation, military, microwave, or

optical network equipment components, modules, or subsystems. The common thread is high-frequency and broadband design at 0–5 GHz and up to 0–100 GHz, and the drive for significant performance improvements.

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Logistics! If you experience any technical difficulties, call

WebEx technical support– (866) 779-3239 toll free (U.S.)– (916) 463-8262 toll (International)

! Brief Q&A session to follow each presentation– Please submit questions online using the Q&A tab– If you have additional questions following the event,

please send an email to [email protected]

! To download the presentation after the event, please visit www.inphi-corp.com and follow the instructions on the home page

mailto:[email protected]

http://www.inphi-corp.com/

June 25, 2003 Page 4

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Outline Outline ! Process Technologies for High-Speed IC Design

– Dr. Gopal Raghavan, CTO

! Device Modeling– Dr. Robb Johnson, Director of Technology

! CAD Tools for Very High Speed IC Design– Jeff Yen, Senior Design Engineer

! Package Design for High-Speed ICs– Roberto Coccioli, Senior Design Engineer

Process Technologies for High-Speed IC DesignDr. Gopal Raghavan, CTO

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Overview

! Technology choices

! Applications

! Reliability

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Technology ChoicesTechnology Choices! FET technologies

– Silicon" CMOS 0.13 µm gate lengths

– Gallium arsenide (GaAs) " Psedomorphic high electron mobility transistor (pHEMT)

! Bipolar technologies– Indium phosphide (InP)

" 1.0 µm emitter width" Double heterojunction bipolar transistor (DHBT)" Single heterojunction bipolar transistor (SHBT)

– Silicon germanium (SiGe)" 0.13 µm emitter width" DHBT

– Gallium arsenide (GaAs)" 2.0 µm emitter width" DHBT

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Why Multiple Technologies ?! Different applications need varying

– Voltage swing– Power dissipation– Integration / complexity– Speed– Noise levels– Cost

! Many of these parameters trade off against each other– e.g. high voltage implies lower speed for a given

structure / material! Different technologies optimized for

different applications

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FET Technology

GaAs pHEMTSi nMOS

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Bipolar Technology

Low emitter, base resistanceLow yield

Low emitter, base resistancePlanar process = high yield

Passivated surfaces

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Bipolar Technology (con’t.)

n Sip SiGe

n Si

Si Based

n GaAs

p GaAs

n AlGaAs

n GaAs

p GaAs

n InGaP

GaAs Based

n GaInAs

p GaInAs

n AlInAs

n InP

p GaInAs

n InP

InP Based

SHBT

DHBT

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InP Technology for High-Speed ICs! Higher electron velocity in InP

– Thicker base and collector layers compared to Si, SiGe, and GaAs

" Lower capacitance" Lower current density for peak performance" Lower Vbe

" Better breakdown

0 5 100

1

2

3

V (1

07C

M/S

)

E (kV/cm) electric field

ELECTRON VELOCITY

0 5 100

1

2

3

7

InPGaAs

Si

GaInAs

780 mV

0.1

0.0 0.4 0.8 1.2 1.6 2.0VBE (V)

J c(A/c

m

GaAsHBT

100

1

10InP

0.1

0.010.0 0.4 0.8 1.2 1.6 2.0

VBE

J c(A/c

m2 )

220 mV

Si BJT

100

1

10

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InP Technology for High-Speed ICs (con’t.)

! Gold interconnect! Semi-insulating substrate! Low-k dielectric! Backside vias available! Currently 1 µm feature size

– Easily scaled to smaller geometries – Inexpensive– Limited number of process steps

! Limited integration

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High-Speed Circuit Examples

96 GHz InPStatic Divide-by-2

~150 mW

10 Gbps CMOS1:4 Demux + 4:1 Mux

Back-to-Back~300 mW

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InP High-Speed Circuit Examples

13 GHz D flip-flop~0.3 ps jitter rms

~10 ps rise/fall time

1:4 DemuxOperation at 80.6 Gbps

Beat Test

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Complexity / Speed TradeoffTransistors

100M CMOS

pHEMT

SiGe

InP

10K

1K

100

Speed10 GHz 100 GHz

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Voltage Swing / Speed Tradeoff! InP has higher electron velocity and breakdown voltage

than silicon! For same speed, tcoll (Si) < tcoll (InP)! InP devices have higher breakdown for same speed! Alternatively, InP devices are faster for same breakdown

0 5 100

1

2

3

V (1

07C

M/S

)

E (kV/cm) Electric Field

ELECTRON VELOCITY

0 5 100

1

2

3

7

InPGaAs

Si

GaInAs

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Breakdown Voltage / Speed Tradeoff

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Cost Tradeoffs

$0

$40

$80

$120

$160

$200

1000 10000 100000 1000000No. of Die (Volume)

Cos

t

SiGe 1

SiGe 2

InP HBT

pHEMT

Mask cost limited Yield / wafer size limited

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Device Requirements for Optical Mach-Zehnder Drivers

! High voltage swing (~7 V p-p, 12.5 Gbps)

! High breakdown voltage ( > 8 V)

! High speed (ft > 100 Ghz)

! Technology choices– GaAs pHEMT– GaAs bipolar– InP DHBT (Inphi choice)

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Technology Comparison

441External Components

434Reliability

551Gain

542Die Size

415Power Dissipation

412Device Speed / Performance

InP DHBTGaAs HBTGaAs pHEMT

1-5 scale, 5 = best

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Reliability! Process reliability varies from CMOS

(extremely mature) to InP DHBT (relatively new)

! Foundry evaluation should include detailed reliability evaluation

! Mature foundry should have reliability data on actives and passives and design rules for reliability

! Much of this information is proprietary

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Conclusions

! Numerous choices for high-speed process technologies

! Choose the optimal process for a particular application

! In general, the newer the process, the more time required to get it into production

Device ModelingDr. Robb Johnson, Director of Technology

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Why Model?

! State-of-the-art technologies often do not have state-of-the-art models

! Competitive edge over other companies using the same foundry

! Better understanding of device characteristics and their strengths and weaknesses

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Modeling Challenges! Accurate models over temperature

and bias up to 100 GHz

! Devices with fT up to 200 GHz require good calibration and de-embedding

! Standard models in simulators are optimized for silicon-based devices

! Corner models are needed to accommodate process variations

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Hardware Platform! RF source

– Agilent 8510C vector network analyzer

– Agilent 8510XF millimeter-wave controller (50 MHz – 110 GHz)

! DC source– Agilent 4142B modular DC

source / monitor

! Probe station– Karl Suss PA200 automated prober– Trio-Tech thermal chuck

(–40°C – 200°C)

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Software Platform

! Agilent IC-CAP– Instrument controller for measurements– Tied into Spectre and ADS for simulation

! Cadence CIC (custom IC) design tools– Analog design environment – Spectre– RF design environment – Agilent EEsof RFDE

! Agilent ADS

! IDS DataPower– PCM and circuit data analysis

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Parasitic De-Embedding! Pad parasitics must be de-embedded from device

measurements! Simple LC model of pads not accurate at f > 50 GHz! Distributed CLC network more accurate up to 100 GHz

0

10

20

30

40

50

60

0 20 40 60 80 100 120

Frequency (GHz)

Imag

(Z11

)

Measured DataImproved ModelStandard Model

DUT

Standard Model

L C

DUT

Improved Model

LC/2C/2

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Overcoming Model Deficiencies! Standard model does not adequately model

capacitance as a function of voltage and temperature! Custom model to improve model

Standard Model Improved Model

Voltage (mV)

Cap

acita

nce

(fF)

Voltage (mV)

Cap

acita

nce

(fF) Increasing

Temp

MeasuredData

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Corner Modeling

! Create models based on physical measurements (e.g. sheet resistance) rather than arbitrarily fitting parameters

! Use PCM data to determine process corners and create device corner models

fT (GHz)

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Conclusions

! Parasitic de-embedding of pads can be achieved with distributed model

! Model limitations can be overcome with custom model implementation

! Corner models can be achieved with synergy between process control monitor data and model parameters

CAD Tools For Very High Speed IC DesignJeff Yen, Senior Design Engineer

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Very High Speed Circuit Types! Broadband, analog, & mixed signal

– Optical network physical layer components

" Optical – electronic interface» Transimpedance amplifiers» Limiting amplifiers, AGC amplifiers» Modulator & laser drivers

" Serializers / deserializers (high-speed – low-speed interface)

» Mux / demux» Frequency dividers» Clock multiplier and clock recovery PLLs» High-speed logic gates

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Very High Speed Circuit Types (con’t.)

! Discrete high-speed logic components– Ultra high performance logic gates

! Test & measurement systems– Can incorporate any of the above

! Narrowband analog circuits– Millimeter-wave components: oscillators,

amplifiers, mixers, nonlinear filters

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Circuit Design Methods! Several types of analysis necessary

– Time domain analysis for irregular & regular signals– Frequency domain analysis

" Frequency response" Return loss" Noise performance

– Mixed-mode analysis" Simulation of mixed behavioral + physical circuits

! Very high frequency effects must be included– Familiar ground for narrowband circuit design– Transmission lines, passive structures must be modeled– Sophisticated device & passive element modeling

required

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Cadence Custom IC Design Suite! SPECTRE simulator engine

– SPICE-like DC & time domain simulations– Sophisticated frequency domain simulations– Advanced BSIM3, VBIC models for CMOS, bipolar,

BiCMOS design! Versatile design automation

– Composer schematic capture– Virtuoso layout editor– Assura design verification

" Also supports Mentor Graphics’ Calibre

! Standards-based mixed-mode simulation– Supports Verilog-HDL, Verilog-A, Verilog-AMS,

VHDL behavioral models! Tool of choice for lower speed design

flows moving to higher speeds

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Agilent EEsof ADS Software! True electromagnetics-based frequency domain

simulation– Unrivaled capabilities for incorporation of distributed

circuit effects– Interfaces with finite element electromagnetic system

model– Superior custom device modeling capabilities– Mature nucleus “software of choice” for frequency

domain simulation! Limited schematic, layout, design verification,

mixed-mode simulation capabilities! Tool of choice for narrowband design flows

moving to broadband, mixed signal

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Broadband Amplifier Design Example Agilent EEsof ADS

! Demonstrate advanced capabilities suited to very high speed circuit design– Broadband amp simulation example– VBIC bipolar transistor model + Inphi

proprietary design model– Physically modeled transmission line

" Highly accurate analytical frequency domain (convolved into time domain) representation

" Readily verified over broad frequency range against measured S-parameters of IC structures

– Sophisticated stimulus and results display features

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Schematic Entry & Testbench Setup! Amplifier circuits

– Cherry-Hooper* broadband amp with CML amp load

– Comparison of results with and without transmission line

! Signal source & device model– Input signal from LFSR (linear feedback shift

register) generating pseudorandom binary data sequence

" Broadband spectrum input signal– Inphi proprietary model derived from device

measurement, model extraction with ICCAP, proprietary enhancements

*K.Ohhata et al; IEEE JSSC, v.34, no.9, Sept. 1999*E.M. Cherry, D.E. Hooper; Proc. IEE, v.110, no.2, Feb. 1963

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Schematic EntrySchematic Entry

Current mode logic(CML) load stage

Cherry-Hooper amp

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Testbench SetupTestbench Setup

CML loads

Coplanar coupled

lines

ProprietaryVBICmodel

interface

LFSR pseudorandombit sequence generators

Cherry-Hooper amps

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Simulations ResultsSimulations Results

! Transient simulation with implicit frequency domain simulation

! Use “eye” function for displaying data bit eye diagram

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ConclusionsConclusions! Both time and frequency domain

simulations can be used! Accurate transmission line models are

beneficial! Sophisticated device models are imperative! CAD software options available! Agilent EEsof ADS example

– Showed benefit of transmission line model– Readily implement proprietary device model– Mixed time & frequency domain simulation

Package Design for High-Speed ICs Dr. Roberto Coccioli, Senior Design Engineer

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Overview

! Review of package design issues

! Package design flow

! Issues in wideband electromagnetic simulations

! Examples of Inphi’s package analysis and packaged products

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Package Design Issues! Electrical signal integrity

– Power and ground distribution networks and decoupling

– Controlled impedance transmission lines– Manufacturing tolerance for substrate

thickness, line width / space– Transmission line discontinuities and

transitions" First level interconnect" Second level interconnect

– Matched line length: each pair, each group of pairs

– Crosstalk effects

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Package Design Issues (con’t.)Package Design Issues (con’t.)! Thermal management

– Power generation concentrated in small areas, lower thermal conductivity for III-V materials

– End user application and environment determine thermal path and optimal thermal solution

! Mechanical integrity– Design rules for assembly not optimal for

high frequency– Manufacturing tolerances– Second joint level reliability

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Choice of Package Technology

! Electrical specifications– Data rate, rise / fall time, and jitter determine

maximum tolerable losses and affect choice of material set

– Metal losses affect tail; dielectric losses affect mainly rise / fall time

– High data rate (≥ 40 Gbps) requires connector interface, which increases volume and cost

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Choice of Package Technology (con’t.)! Thermal considerations

– Power dissipation and application environment affect package configuration (cavity up/down)

– Heat spreaders must be used for power ICs

! Mechanical– Less mature and more sensitive technologies

require hermetic packages (glass wall, ceramic, or metal)

– Sensitivity of design to manufacturing tolerance influence choice of technology and vendor

! Cost– Drive toward CSP for 10 Gbps and below– Multiple suppliers

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EM and Circuit Simulation Tools! IE3D (Zeland Software)

– Numerical method based on integral equations– 2D and a half (layered dielectric, vertical current flow) – Ideal for planar circuits and transmission lines

! HFSS (Ansoft)– Numerical method based on differential equations– Full 3D capability, essential for 3D transitions and

geometries typical of packages– Frequency-dependent metal and dielectric losses can

be taken into account

! ADS (Agilent)– Initial analysis of transmission lines and discontinuities– Extraction of equivalent circuit models

! SpectreRF (Cadence)– Time domain analysis – Chip-to-package interaction

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Electrical Design and Modeling! High-speed digital circuits have wider frequency

bandwidth than microwave circuits

! Discontinuities cannot be matched with narrowband design techniques– Chip-to-package transitions– On-package transmission lines, vias– Transition to printed circuit board

! Full-wave electromagnetic (EM) simulations and optimization on wide bandwidth are necessary– Electrical properties of materials are rarely known over the

required frequency bandwidth– Usual assumptions can lead to models that are not

physically consistent

! Final step is the extraction of equivalent circuit models for IC package simulations

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Wideband EM Simulation! Correct definition of materials’ electrical

properties is key to physically consistent results– Inductive component of skin effect1

– Correct frequency dependence of dielectric losses2

! Dielectric constant ε(ω) = ε’(ω) – jε’’(ω) of physical, causal materials satisfies the relation3

! Constant loss tangent approximation, generally used for narrowband microwave simulations, provides inconsistent results over a wide frequency band

ε’(–ω) = ε’(ω) ε’’(– ω) = –ε’’(ω) tanδ(–ω) = –tanδ(ω)

1Arabi et. al., IEEE MTT, July 19912Coperich et al, IEEE ADVP, May 20023Diaz, Alexopoulos, IEEE AP, Nov. 1997

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Wideband EM Simulation (con’t)

! Time domain response of transmission line with loss tangent constant with frequency is non causal1(curve a)

! Time domain response of TL with physically consistent material properties is causal1(curve b)

! Each type of material loss has its own signature on time domain signal1

1Svensson et. al., IEEE ADVP, May 2001

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EM Optimization of Package Transitions ! Chip-to-board signal path analysis and optimization

– Example: 7 x 7 mm LCC package, 25 Gbps– Low cost (1/10 of metal package)– Small size (1/100 of metal package)– Integrated decoupling capacitors

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Chip-to-Package Interaction! Transient simulation in Cadence

– Measured rise/fall time 8.89 ps / 8.44 ps, jitter 1.45 ps– Simulated rise/fall time 8.05 ps / 8.13 ps– Simulated rise and fall does not take into account

traces on board

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Thermal Analysis! Thermal analysis of packaged chip determines operating

temperature of devices in actual application environment

! Thermal analysis also provides layout design guidelines for thermal performance for a given technology

[°C][°C]

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Second Level Joint Reliability! Reliability requirements for telecom applications

affect choice of materials (ceramic, lid, solder balls)

! Result of simulated accelerated stress test are correlated to expected field lifetime

Calculated Viscoplastic Strain Energy Density per cycle under ATC 0 – 100°CModel of Cavity Down BGA

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Conclusions

! Full-wave EM simulation / optimization techniques are key elements of high-speed digital package design

! Accurate wideband EM simulation requires physically consistent material properties definition

! Algorithms to extract causal equivalent model from EM simulations to be used in circuit simulators are needed

! Thermal and mechanical considerations must be taken into account at the initial stages of package design

Reference Material

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Presenter BiographiesDr. Gopal Raghavan, CTO. Dr. Gopal Raghavan has over 20 years of experience in high-speed circuit design and device modeling. From 1982 to 1994, Dr. Raghavan was a senior engineer with Intel Corporation engaged in CMOS circuit design and process development. Prior to founding Inphi, Dr. Raghavan was a principal engineer at Conexant designing integrated circuits for 10 Gbps SONET applications. Dr. Raghavan has won several awards, including the Hughes Hyland Patent Award (1998) and the Ross Tucker Award from TMS/IEEE (1993). He holds 10 patents and has published more than 30 technical publications. Dr. Raghavan holds M.S. and Ph.D. degrees in electrical engineering from Stanford University as well as a B. Tech degree in electrical engineering from the Indian Institute of Technology.

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Presenter Biographies (con’t.)Dr. Robb Johnson, Director of Technology. Dr. Robb Johnson comes to Inphi from IBM Microelectronics, where he managed the SiGe Technology Development Group in Burlington, Vermont. While with IBM, Dr. Johnson was instrumental in the development of their SiGe BiCMOS processes. Throughout his career, Dr. Johnson has worked on the design, fabrication, characterization, and modeling of transistors and passive elements at radio frequencies and has implemented them in basic RF building blocks. Dr. Johnson has authored or co-authored more than 25 papers and conference proceedings in the fields of silicon-on-sapphire MOSFETs and SiGe HBTs. He received his B.S., M.S., andPh.D. in electrical engineering from the University of California, San Diego.

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Presenter Biographies (con’t.)Jeff Yen, Senior Design Engineer. Jeff Yen has an extensive background in high-frequency and mixed-signal circuit design. At Cognet, he developed multi-gigabit CMOS clock and data recovery circuits and limiting amplifiers. At Conexant, he designed a variety of integrated circuits for SiGe/SiBiCMOS and GaAs HBTs for 12.5, 10.7, and 2.5 Gbps systems, including laser and modulator drivers, limiting amplifiers, CDR frequency acquisition circuits, loss of lock/loss of signal detection circuits, and MUX clock multiplier PLL ICs. Mr. Yen holds an M.S. in Electrical and Computer Engineering from the University of California, Santa Barbara and a B.S. in Electrical Engineering from Cornell University.

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Presenter Biographies (con’t.)Dr. Roberto Coccioli, Senior Design Engineer. Dr. Coccioli comes to Inphi from Conexant, where he designed high-density organic and ceramic interconnects for flip-chip assemblies. He has designed packages for 2.5, 10, and 40 Gbps systems using mixed electromagnetic and circuit design analysis and has performed extensive verification of measured versus designed performance parameters. Dr. Coccioli holds two U.S. patents in electronic packaging. He has written 31 technical papers for international journals and 55 contributions for international conferences as well as co-authored a book entitled Quick FEM for Electromagnetic Waves. Dr. Coccioli received his Ph.D. in electrical engineering from the University of Florence.

Documents

High-Frequency IC Design & Test Webinar Part 1 (Design) Proprietary / Page 3 Logistics! If you experience any technical difficulties, call WebEx technical support – (866) 779-3239