Network of excelleNce oN HigH PerformaNce aNd embedded

arcHitecture aNd comPilatioN

tHe 8tH iNterNatioNal coNfereNce oN HigH PerformaNce aNd embedded arcHitectures aNd comPilers (HiPeac 2013), 21-23 JaNuary 2013, berliN, germaNy

welcome to tHe autumN comPutiNg

systems week iN gHeNt, belgium,

15-17 october 2012

www.HiPeac.Net

info 32

appears quarterly october 2012

acaces & PumPs: summer aNd scHool

Never mixed tHis well

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message from tHe HiPeac coordiNator

coNteNt

intro

I hope you all have enjoyed a relaxing summer break. This summer, the bad eco-nomic news was overshadowed by the Olympic Games, undoubtedly the major media event of 2012. At the end of the summer, we were brought back to busi-ness with the various court rulings between Apple and Samsung. It is clear that the war for the mobile market has really started. For many years, Apple was the reference, but other companies are claiming their share too, and Microsoft still has to join the club with Windows 8 in autumn. To win this war, it might not be enough to have the best ideas, the best designers and engineers, and the best marketing staff. One might also need to have on board the best lawyers. And even if you have them, there is no guarantee that all court rulings will be in your favour. The key question is who will profit most from this evolution: the companies, the customers, the investors, the lawyers, innovation?

In July, 203 participants enjoyed the annual ACACES summer school in Fiuggi, Italy. As in previous years, this community flagship event received a high appreciation score

from the participants. I would like to thank all the instructors for their excellent contributions. Next year’s summer school will be announced in January 2013.

In October we organize the fall Computing Systems Week in my home town Ghent, October 15-17. As part of this event, we will also organize the first HiPEAC Industry Partner Program, in which we bring industry and academia together to think about common challenges. With more than 20 activities taking place over three days, the event will be a major networking opportunity for the HiPEAC community. This event is especially important in preparation of proposals for the January 2013 call ICT-2013.3.4, worth EUR 72.5 Million. This is the biggest call in computing systems since the start of FP7.

In January 2013, there is the HiPEAC Conference, which will take place in Berlin. This is the second year that we outsource the reviewing process for the conference to ACM TACO, and again we have received many high quality submissions for the conference. We already have 10 papers accepted, and 36 papers got an invitation

intro

2 message from the hipeac coordinator

3 message from the project officer

hipeac activity

4 mateo 2012: multicore architectures and their effective operation

5 Barcelona computing Week: pumps 2012

6 acaces 2012 report

7 pumps+acaces 2012 trip report

7 joint seminar: poznan university of technology and rWth aachen university

hipeac announce

8 Book on optical interconnects for future data center netWorks

8 formal analysis techniques for gpu kernels: a tutorial at hipeac 2013

hipeac news

9 hipeac memBer andré seznec Wins first intel research impact medal

9 neW hipeac memBer: nicolas sklavos, tei of patras

10 google anita Borg scholarship aWarded to hipeac phd student

10 tu delft researchers receives Best student paper aWard at nanoarch'12

11 freescale hosts first hipeac phd internship

12 modelling 3d-stacked memories With virtual platforms

13 ppmc: on chip memory manager and scheduler for vector processor

in the spotlight

14 fp7 reflect project: rendering fpgas to multi-core emBedded computing

15 multipartes 2012 advisory Board gathered relevant european stakeholders from academia and industry

16 fp7 eu-incoop project: fostering eu- india cooperation in computing systems

18 phd news

20upcoming events

to submit a revised version. The evaluation of the revised versions will be ready by mid-November. All authors of accepted papers will get an invitation to present their work at the conference. Their paper will be carefully copyedited, published in ACM TACO, and indexed in all major publi-cation databases. The conference itself will be a major networking event for the computing systems community in Europe. There will be 39 workshops and tutorials taking place during the conference, and all HiPEAC companies and FP7 computing systems projects will be invited to promote their research and activities at the conference.

Koen De Bosschere_________

HiPeac info 32 3

intro

The discussions on Horizon 2020, the next European framework programme for research and innovation that will run from 2014 to 2020, are under way in the European Parliament and the Council. The European Commission has proposed to focus Horizon 2020 funds on three key objectives: excellent science, competitive industries and better society. Information and Communication Technologies (ICT) will play a role in each one of these key objectives. Specifically through the "com-petitive industries" (or Leadership in Enabling and Industrial Technologies - LEIT) part, the European Commission proposes six main activity lines for ICT research. One of the proposed main activity lines focuses explicitly on next generation computing to give much more momentum to European computing research and innovation.

The proposed main activity lines are:• A new generation of components and

systems: engineering of advanced and smart embedded components and systems. The objective is to maintain and reinforce European leadership in technologies related to smart embedded components and systems. It also includes micro-nano-bio systems, organic electronics, large area integration, underlying technologies for the Internet of Things (IoT) including platforms to support the delivery of advanced services, smart integrated systems, systems of systems and complex systems engineering.

• Next generation computing: advanced computing systems and technologies. The objective is to leverage European assets in processor and system architec-ture, interconnect and data localisation technologies, cloud computing, parallel computing and simulation software for all market segments of computing.

• Future Internet: infrastructures, technologies and services. The objective is to reinforce the competitiveness of European industry in developing, mastering and shaping the next generation Internet that will gradually replace the current Web, fixed and mobile networks and service infrastructures, and enable the interconnection of trillions of devices (IoT) across multiple operators and domains that will change the way we communicate, access and use knowledge. This includes Research and Innovation on networks, software and services, cyber security, privacy and trust, wireless communication and all optical networks, immersive interactive multimedia and the connected enterprise of the future.

• Content technologies and information management: ICT for digital content and creativity. The objective is to provide professionals and citizens with new tools to create, exploit and preserve all forms of digital content in any language and to model, analyse, and visualise vast amounts of data, including linked data. This includes new technologies for language, learning, interaction, digital

message from tHe ProJect officer

preservation, content access and analytics; intelligent information management systems based on advanced data mining, machine learning, statistical analysis and visual computing technologies.

• Advanced interfaces and robots: robotics and smart spaces. The objective is to reinforce European scientific and industrial leadership in industrial and service robotics, cognitive systems, advanced interfaces and smart spaces, and sentient machines, building on increases in computing and networking performance and progress in the ability to build systems that can learn, adapt and react.

• Micro- and nanoelectronics and photonics. The objective is to take advantage of the excellence of Europe in this key enabling technology and support the competi-tiveness and market leadership of its industry. Activities will also include research and innovation on design, advanced processes, pilot lines for fabrication, related production technolo-gies and demonstration actions to validate technology developments and innovative business models.

Panos Tsarchopoulos_________

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hipeac activity

On the occasion of the 60th birthday of Professor Mateo Valero, distinguished researchers and industry representatives in the field of computer sciences gathered in Barcelona for a day and a half of technical presentations

mateo 2012: multicore arcHitectures aNd tHeir effective oPeratioN

The workshop had the dual purpose of providing an opportunity for attendees to listen to insights from outstanding inter-national researchers while also honoring one of HiPEAC's key personages and its first coordinator, Professor Mateo Valero, on the occasion of the 60th anniversary of his birth.The workshop chairs, Yale Patt (University of Texas at Austin) and Nacho Navarro (BSC and UPC), brought together a remarkable group of 31 distinguished speakers, who gave talks and participated in a panel

session to convey important insights from their unique leadership positions. Conference sessions centered on topics such as computer microarchitecture, multicore programming, heterogeneous computing, compilers and programming models.The MATEO 2012 speakers represented practically every major research institution in the US, as well as principal investigators from the European community, including such notable HiPEAC members as Koen De Bosschere, Avi Mendelson, Per Stenstrom, André Seznec, Olivier Temam, Georgi Gaydadjiev and Theo Ungerer. The work-shop brought well-known players in this field, including six winners of the prestigious Eckert Mauchly prize (popularly known as the Nobel Prize for computer architecture) and four Maurice Wilkes prize winners, the most highly recognized prize addressed to younger researchers for outstanding con-tributions to computer architecture. These distinguished researchers and industry representatives in the field of computer sciences have in some way collaborated or have been in contact with UPC Barcelona Tech and the FIB’s Computer Architecture Department, the former CEPBA and the BSC.The one and a half day workshop concluded with a stimulating panel discussion on “The Role of Computer Architecture over the

MATEO'12 invited speakers.

The MATEO 2012 workshop (www.mateo12.org) was held on the 28th and 29th of June in the premises of the Universitat Politecnica de Catalunya, Barcelona. More than 300 members of the international industrial and academic computer architecture community participated in this event, organized by the Barcelona Supercomputing Center, Universitat Politecnica de Catalunya and HiPEAC Network of Excellence, with the sponsorship of Microsoft Research, IBM and Intel.

The panel discussion, chaired by Professor Yale Patt.

HiPeac info 32 5

hipeac activity

next 25 years”, chaired by Professor Yale Patt.After the panel, the assembly moved to the second reason for coming to Barcelona on June 28 and 29, to honor Professor Valero on the occasion of his 60th anniversary. For more than three hours, colleagues from as far away as Seattle, Washington and as near as BSC recounted their stories about Mateo, and their appreciation for what he has meant to them personally, to UPC, to the European community, and to the Computer Architecture field.

Nacho Navarro, BSC/UPC, Spain_________

Workshop participants pose with Professor Valero's birthday cake.

For the third year in a row, the Barcelona Supercomputing Center and Universitat Politecnica de Catalunya organized and held the Barcelona Computing Week: PUMPS 2012

barceloNa comPutiNg week: PumPs 2012

PUMPS (Programming and tUning Massively Parallel Systems) is an annual five-day summer school co-organized with the University of Illinois. During this week, a group of 95 international students learn efficient GPU and HPC programming directly from world-renowned experts in the field: Wen-mei Hwu (U. of Illinois), David Kirk (NVIDIA) and Isaac Gelado (BSC).

Organized under BSC's CUDA Center of Excellence teaching program and with the sponsorship of NVIDIA and the HiPEAC Network of Excellence, the PUMPS summer school has become a reference in Europe on GPU and HPC programming. This year again, more than 250 applications were received from students and researchers from all around the world.

Summer school co-directors Wen-mei Hwu (U. of Illinois) and Mateo Valero (BSC-UPC), and Nacho Navarro, local organizer and manager of BSC's “Accelerators for HPC” group were able once again to offer a unique learning experience, combining theoretical lectures and hands-on labs in a comprehensible manner that allowed the students to grasp some of the advanced concepts required in order to program massively parallel systems.

Breaking with the previous years' model of offering different tracks for advanced and beginner attendees, this year's summer school focused on advanced techniques and optimizations for GPU and HPC programming. Some of the topics covered were: data locality, reducing output

interference, dealing with non-uniform, sparse and dynamic data, improving data efficiency in large data traversal, extending computation to multiple GPUs, and a session dedicated to the OmpSs programming model and Paraver analysis tool, taught by Rosa Badia (BSC/CSIC) and Xavier Martorell (BSC/UPC).In addition, this year's attendees enjoyed a special invited talk from NVIDIA Fellow Manuel Ujaldón (U. of Málaga) on approaches to GPU computing, as well as a very interesting talk by David Kirk (NVIDIA), which provided insights on NVIDIA's brand new Kepler architecture and CUDA 5.0.

Based on the great feedback received last year, the summer school again offered the students the opportunity to present their work in a poster session.A jury composed of the summer school instructors and BSC's senior researchers evaluated their work and agreed to award two students the Best Poster Award: Victor A. Gil for his work “Parallelization of non bonding interaction gradient calculation in PELE++”, and Apostolis Glenis for his work “Applying Smith-Waterman to movie effect detection on CPUs, GPUs, and FPGAs”.

Víctor García, BSC/UPC, Spain_________

PUMPS 2012 attendees.

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hipeac activity

“After hearing only good comments about the HIPEAC summer school, I

decided to apply this year. I consider myself a lucky guy for getting a chance to participate in it”

acaces 2012 rePort

This year, following last year's good experience, the summer school was held again in Fuiggi, Italy. Getting there was well planned and organized so that we only had to arrive at one of the three pick-up spots in Rome - afterwards there was a shuttle bus service, arranged by the organizing committee.

I had a lot of headaches registering for the courses since there were so many good topics given by well-known lecturers. We could choose only one course in each of the four slots, since the courses in each slot were taught in parallel. I managed to choose two new topics and two from areas of my PhD research.

Accommodation was great with a fantastic room service. I was given a double room, which was shared with my colleague. I would recommend that future participants apply for a double room, since it allows HiPEAC to accommodate more participants.

The pace of the summer school was intense. Courses were starting after break-fast: two slots in the morning and two slots after lunch, with coffee and snack breaks following the first slot. I really appreciated the large tables at lunch and dinner, which meant up to ten people could share one table. It was a good move towards better networking during the meals. Once the courses were over for a day, we had free time before dinner to spend either in the spa centre at the hotel, or to take a walk around town and to try the Italian specialities. I really enjoyed the

famous Italian ice cream and pizzas. I also made a couple of excursions - to the old town and to the nearby lake. After dinner, we had plenty of time to hang around and get to know each other better. It was also a nice opportunity to exchange research ideas with the other participants.

With the start of the first course, we were given course materials. The courses were awesome and the lecturers were keen on

answering our questions to the very details. Hooray for that! The course presentations were made available on-line a couple of weeks after the summer school. Wednesday afternoon was no-courses day, but poster session day. I presented a poster myself, and thus had to answer many very interesting questions, which boosted my research efforts back home. After the poster session and seeing what other people are working on, I became interested in a couple of new areas of research that I am keen to pursue. Also, I really like the poster session proceedings.

On the last night of the summer school, we had a party in the open air under the clear sky. Lovely dinner, live music and people in a good mood made it such a great night. This was the first time for me to try Limbo dance, and I liked it. The party continued until one o'clock after midnight. The next morning, the shuttle service took the sleepy participants back to Rome.

All in all, the ACACES summer school was an amazing experience. This was my first summer school out of Barcelona, and I really enjoyed it. I would like to use the opportunity to thank the members of the organizing committee, the sponsors, the lecturers and all the fellow participants for making this summer school such a great success.

Nikola Rajovic, BSC/UPC BarcelonaTech, Spain_________

ACACES 2012 family photo.

World-class experts served as lecturers for the summer school.

Students presenting their research during the poster session.

HiPeac info 32 7

PumPs+acaces 2012 triP rePort

The most important reason that PUMPS was so successful is that it covered all kinds of design patterns related to optimi-zations for many-core processors. The design patterns, taught through well-pre-pared intensive lectures and hands-on labs, will enable us parallel programmers to take on all kinds of challenges that we face on an almost daily basis. The Roofline

model, for instance, shows how straight-forward it can be to get past the memory bandwidth slope and achieve the most from the hardware. This is an example of the many benefits arising from the effort invested in organising PUMPS. ACACES was the greatest learning experience I had in a single week: the lectures were well detailed and future oriented. Best of all, you could choose which four to attend from a lecture pool of twelve, all tailored to specific research areas! I also learnt many new things just by talking with the other attend-ees; there were more than 200 of them, all like-minded individuals. If you are either doing research or developing next-genera-tion compilers, this summer school is one of the best opportunities waiting for you.It should also be pointed out that, for both summer schools, the location and logistics (accommodation, lunches, coffee breaks)

This event continues a series of seminars co-organized by RWTH during the past years, made possible by HiPEAC’s mobility mechanisms

JoiNt semiNar: PozNaN uNiversity of tecHNology aNd rwtH aacHeN uNiversity

On June 29th 2012, the members of the Institute of Communication Technology and Embedded Systems (ICE) from the RWTH Aachen University visited the chair of Wireless Communication at the Poznan Technical University (PUT) in Poland for a full-day technical seminar. This event con-tinues a series of seminars co-organized by the RWTH during previous years, made possible by HiPEAC’s mobility mechanisms. As reported in past issues of the HiPEACinfo newsletter, previous seminars brought together researchers from the RWTH with top researchers from Edinburgh University, Imperial College London and the Tampere University of Technology. This year, with HiPEAC expanding to new EU member states, ICE decided to pay a visit to the

renowned group headed by Prof. Krzysztof Wesołowski. While previous seminars focused on embedded architectures and tools, this seminar had a strong emphasis on algo-rithms for wireless communications. The technical agenda opened with introduc-tory presentations from Prof. Szulakiewicz and Prof. Wesołowski, followed by techni-cal presentations from the PUT staff, which revolved around OFDM and cognitive systems, as well as VLSI testing algorithms and methodologies. After the lunch break, Prof. Ascheid and Prof. Leupers introduced the ICE institute. The introduction was fol-lowed by technical presentations from the ICE staff, covering algorithms and architec-tures for wireless receivers, tools for wire-

less transceiver design and an overview of today’s multi-core system simulation tech-nologies. The seminar day was rounded up with a joint dinner organized by PUT at a beautiful place along the Lake Malta. Both the technical and the social programs were accompanied by lively discussions on common research areas as well as items that were new to one or other of the research groups. In the end, the heads of both research institutions agreed on keeping the communication alive and embarking upon new projects in the future. This successful and rich experience should encourage other established HiPEAC members to visit top research groups from new EU member states. Their contribu-tions will surely strengthen EU-wide research on computing systems.

Jeronimo Castrillon, RWTH Aachen University, Germany_________

“I have had the opportunity to attend a handful of

summer schools, all of them on parallel programming. Now I wanted to tell you why and how PUMPS and ACACES are such unique

experiences.”

were also 5-star quality. Barcelona is one of the greatest places to have fun and also to work, especially if you are into parallel pro-gramming and fancy nights out.The only down side was the lack of quality Internet access at Fiuggi.Many thanks for all the hard work put on in the preparation of these summer schools, to the lecturers, to the TA's, to HiPEAC, and to the other sponsors and also to the attendees. They were all awesome! May the friendships made here last for years.

U. Can Bekar, Koç University, Turkey_________

hipeac activity

HiPeac info 328

Dr. Kachis and Dr. Tomkos of Athens Information Technology, Greece, are co-editors (together with Prof. Bergman of Columbia University) of this newly-published book, which covers optical networks and how they can provide high band width, energy-efficient interconnects with increased communication bandwidth. This volume, with contributions from leading researchers in the field, presents an integrated view of the expected future

requirements of data centers, and serves as a reference for some of the most advanced and promising solutions proposed by researchers from leading universities, research labs, and companies. The work also includes several novel archi-tectures, each demonstrating different technologies, such as optical circuits, optical switching, MIMO optical OFDM, and others. Additionally, Optical Inter-connects for Future Data Center Networks

provides invaluable insights into the benefits and advantages of optical inter-connects and how they can be a promising alternative for future data center networks.

For more information: http://www.springer.com/engineering/electronics/book/978-1-4614-4629-3_________

Christoforos Kachris, Keren Bergman and Ioannis Tomkos

book oN oPtical iNtercoNNects for future data ceNter Networks

This tutorial will help GPU kernel developers write code that is free from concurrency errors

formal aNalysis tecHNiques for gPu kerNels: a tutorial at HiPeac 2013

Formal Analysis Techniques for GPU Kernels (FAT-GPU) will be a half-day tuto-rial at the HiPEAC 2013 conference, Berlin, January 2013, on exciting recent develop-ments in the area of improving the reliability of GPU kernels. The focus will be on bug detection, proving absence of defects, and checking portability of GPU kernel code.

FAT-GPU is supported by the CARP FP7 project, and will be presented by Alastair Donaldson, a Lecturer at Imperial College London who is also the Coordinator of CARP.

The tutorial will be practical, and aimed at researchers and practitioners in the paral-lel programming community who have a reasonable background in GPU program-ming. The tutorial will not assume a back-ground in formal verification or theoretical computer science. Two main topics will be covered:• Verifying race- and divergence-freedom

in OpenCL and CUDA kernels using the GPUVerify tool

• Finding races in CUDA kernels using the GKLEE tool

For more info visit: http://www.doc.ic.ac.uk/~afd/FAT-GPU/Alastair Donaldson,Imperial College London, UK_________

Alastair Donaldson, the presenter of FAT-GPU.

hipeac announce

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hipeac news

Recently HiPEAC Member Dr André Seznec from Inria/Irisa in Rennes received the first Intel Research Impact Medal from the Intel Labs Academic Research Office. Through this medal, Intel recognizes the influential work carried out by André Seznec on "high-performance computer micro-architec-ture, branch prediction and cache architecture". This work has been of "tre-mendous benefit to Intel, the industry, and the academic community as a whole".In 2010, André Seznec was the first member of HiPEAC research community to be awarded an ERC advanced grant, for the DAL project: "Defying Amdahl's Law". The DAL project (2011-2016) aims at impacting

the design and definition of many-core processor chips for the 2020s.André Seznec has also served the HiPEAC community as general co-chair of the HiPEAC conference in 2009. He is the program co-chair for next HiPEAC confer-ence in January 2013 in Berlin. He was also the general chair of the ISCA 2010 confer-ence in Saint-Malo, France._________

The Intel Research Impact Medal acknowledges researchers whose work benefits Intel and the broader industrial and academic community

HiPeac member aNdré sezNec wiNs first iNtel researcH imPact medal

New HiPeac member: Nicolas sklavos, tei of Patras

Dr. Nicolas Sklavos is an Assistant Professor with the Informatics & MM Dept, Technological Educational Institute of Patras, Hellas. He is also adjunct faculty, Assistant Professor, since 2007, with the Computer Engineering & Informatics Dept., University of Patras, Hellas. He holds an award for his PhD thesis on “VLSI Designs of Wireless Communications

Security Systems”, from IFIP VLSI SOC 2003. His research interests include Cryptographic Engineering, System on Chip Design, Computer Architecture, VLSI Design, and Security of Computers and Networks. N. Sklavos has participated in a great number of European and national projects, both research and development, in the areas of his research. He serves as an evaluator of both European Commission Projects (FP7) and as General Secretary of Research and Development, Hellas. He is director of KNOSSOSnet Research Group. Since 2007, he is the Chair of IEEE Hellas GOLD Affinity Group. He is the Editor-in-Chief of Information Security Journal: A Global Perspective Journal, Taylor & Francis Group. He serves as Associate Editor for IEEE Latin America Transactions, IEEE Press, and Computers & Electrical Engineering Journal, Elsevier. He has been Guest Editor of Special Issues for Elsevier & Springer publishers. He was the General Co-Chair of ACM MobiMedia 2007 and General Chair of ATHENA 2011 Summer School. He has participated in the organization of more

than 100 conferences organized by IEEE/ACM/IFIP, as Publicity, Publication Chair, Program Chair and Program Committee member. He has authored or co-authored more than 100 scientific articles, books, chapters, tutorials, in the areas of his research. His published works have received up to 800 non-self citations. Contact him at: nsklavos@ieee.org, http://www.knossosnet.gr.

Nicolas Sklavos, Technological Educational Institute of Patras, GreeceWebsite: http://www.nsklavos.gr/_________

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hipeac news

Sabela Ramos Garea, PhD student of the Computer Architecture Group at the Univer sity of A Coruña, Spain, has been awarded the 2012 Google Anita Borg Memorial Scholarship in the EMEA (Europe, Middle East and Africa) region (http://w w w.google .com/anitaborg/emea/winners.html). This annual scholarship aims to encourage the role of women in computing and technology fields and is awarded based on the strength of female students’ academic performance and leadership experience. Besides the financial prize, scholars and finalists were invited in June to a three-day visit to the Google office in Zürich, where they attended different workshops, panels, breakout

sessions and social activities. They also had the opportunity to present their current research activities in a poster session, where Sabela Ramos showed her work on optimizing message passing in Java for shared memory. This work will be extended with a three-month research visit at ETH Zürich hosted by HiPEAC member Dr. Torsten Hoefler.

Guillermo López TaboadaUniversity of A Coruña, Spain_________

Sabela Ramos Garea from University of A Coruña is one of the recipients of this annual scholarship, which aims to encourage women to excel in computing and technology and become active role models and leaders in the field

Sabela Ramos during her visit to the Google office in Zürich.

google aNita borg scHolarsHiP awarded to HiPeac PHd studeNt

Their paper explores the utilization of fluctuating tokens as an enabler for the stigmergic computational paradigm observed in nature

tu delft researcHers receive best studeNt PaPer award at NaNoarcH’12

The paper entitled “Stigmergic Search with Single Electron Tunneling Technology Based Memory Enhanced Hubs”, authored by Saleh Safiruddin, Sorin Cotofana, and Ferdinand Peper, has been granted the Best Student Paper Award of the ACM/IEEE International Symposium on Nanoscale Archi tectures (NANOARCH '12), held in Amsterdam, The Netherlands, from July 4 to July 6, 2012. Saleh Safiruddin and Sorin Cotofana are with the Computer Engineering Laboratory, Faculty of Electrical Engineering Computer Science and Mathematics, Delft Technical

University. Ferdinand Peper is with the Brain ICT Laboratory, National Institute of Information and Communications Techno-logy, Kobe, Japan. In this paper, they explore the potential of utilizing fluctuating tokens in an attempt to provide hardware support for the stig-mergic computational paradigm, which was first observed in social insects, e.g., ants. Fluctuations have recently been rec-ognized as powerful resources that can be exploited to drive computations, but so far their use has mostly been limited to logic circuits. This paper goes further and Saleh Safiruddin

HiPeac info 32 11

hipeac news

explores a more general framework, in which computation is modeled as a process with a multitude of fluctuating tokens that interact with each other directly or via stigmergy. The paper intro-duces novel computational elements, i.e., Memory Enhanced Hubs (MEHs), which contain functionality to pass fluctuating signals through them, as well as stig-mergic functionality to temporarily store a state and to eventually reset it. The authors proposed implementations of these

concepts in Single Electron Tunneling (SET) technology, which is a strong candidate for such an approach, since it combines a key element of fluctuation-driven systems, i.e., fluctuating tokens, with the potential for manufacturing in traditional materials (silicon) as well as alternatives, such as molecules. A SET based design of an instance of a memory enhance hub is presented and it is demonstrated through simulations that it exhibits the required functionality. Furthermore, the paper

also demonstrates that MEHs networks operating according to the stigmergic paradigm can be potentially constructed.

Saleh Safiruddin, Sorin Cotofana, and Ferdinand PeperTU Delft, The Netherlands _________

HiPEAC-sponsored internship helps Freescale develop cutting-edge compiler toolchain technologies

freescale Hosts first HiPeac PHd iNterNsHiP

As part of its remit to increase industry-academia collaboration, the HiPEAC network sponsors PhD students to under-take industrial internships. In Summer 2012, Tobias Edler von Koch, a PhD student in compiler technology at the University of Edinburgh, spent three months on a research internship working with Freescale Semiconductor at their R&D Centre of Excellence in Glasgow, Scotland. Freescale is the former semiconductor division of Motorola and a global leader in embedded processing solutions. The internship was based in the Network and Multimedia Solutions Group which develops and sup-ports communi cations processors used in a wide variety of areas, such as mobile phone base stations, routers, storage systems, and industrial applications. Software tools are increasingly important to unlock the full potential of such devices. As an innovation-driven company, Freescale therefore takes a keen interest in the latest developments in compiler technologies, which form a core part of the software

toolchain eco-system. The majority of Freescale's current network processor portfolio is based on the Power instruction set architecture. During his internship, von Koch focused on improving support for this architecture in the LLVM compiler infrastructure: "The internship gave me the unique opportunity to put my research experience in compiler engineering into practice and work on all parts of the com-piler framework: from improvements to the Clang front-end and development of new optimization passes to back-end enhancements targeted at improving per-formance for Freescale processors. There is now a much stronger business case for LLVM on Power architectures." LLVM is rapidly gaining ground across industry and academia due to its modularity and clean architecture, and is set to replace GCC as the de-facto compiler standard. With many ideas for future projects resulting from the internship, it is hoped that this project can serve as a starting point for further collab-oration between Freescale and the University of Edinburgh in this area. "Cutting-edge innovation is key to growing our market share in this highly competi-tive industry. An on-going exchange of ideas between industry and academia is of significant benefit to both sides," says Mark Knox of Freescale.

Tobias Edler von Koch & Mark KnoxUniversity of Edinburgh & Freescale R&D, Scotland_________

Tobias Von Koch

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hipeac news

Today’s high-performance and embedded applications are characterised by ever increasing demands on memory band-width and capacity. For this reason, the number of IOs of the memory subsystem is continuously growing. However the number of IO pins is limited by the package. The energy per bit consumed by going off chip is many times higher than the energy required for on-chip accesses. This is because the electrical characteristics of interconnections between chips require complex and power hungry IO transceiver circuits.Moreover, random access latencies and internal cycle times of DRAMs are not decreasing as fast as the microprocessor cycle time. This problem is known in high-performance and embedded computing as the Memory Wall.Three-dimensional stacked memories have been proposed as a promising solution to the power versus bandwidth dilemma and the Memory Wall. These memories reduce the distance between the CPU and the external RAM from centi-metres to micrometres by means of TSV (through silicon via) technology. Random access times are improved but more

importantly, this technology provides a major boost in energy efficiency, in com-parison with standard SDR or DDR/2/3 DRAM devices. The pairing of high-band-width communication with the lower power consumption of 3D integrated memory is an ideal fit for high-perfor-mance and embedded applications. For instance, in a terascale computing node, about 70% of the overall power is con-sumed by the DRAM and its interface. Our exploration of the 3D-DRAM design space

showed that an optimised 3D-DRAM can reduce the energy per bit by 80% in com-parison with an LPDDR2x32 DRAM. Obviously new DRAM architectures require a new generation of DRAM controllers. Therefore our current focus is on design space exploration and optimisation of the controller. Our jointly optimised DRAM and controller architecture features flexible access to the 3D-DRAM subsystem, which enables up to 50% energy per bit savings. For faster simulation and exploration at the system level, we currently develop TLM2.0 based virtual platforms. These platforms allow us to estimate and opti-mise the performance and power for dif-ferent applications quickly.The platforms are based on the Synopsys Platform Architect and the gem5 simula-tion framework. To get an even faster sim-ulation we record transaction traces and play them back with elastic trace players. The traces will be taken either from a cycle-accurate virtual platform or from the gem5 simulator. With this technique the over-head of simulating the whole system with cores and busses is no longer necessary.

Virtual platforms speed up design exploration of 3D-stacked DRAM subsystems

modelliNg 3d-stacked memories witH virtual Platforms

Virtual platform for 3D-DRAM controller exploration with 4 channels.

Future bandwidth requirements and the role of the DRAM controller

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hipeac news

To achieve the maximum performance from FPGA technology, it is required to exploit data parallelism by instantiating a number of SIMD units. The applications executing on such an architecture gener-ate multiple delays due to their irregular data arrangement and the system’s complex scheduling scheme. Therefore as for a conventional SIMD unit, all types of SIMD machine -- vector supercomputers to vector microprocessors -- are required to have efficient vector data access, to improve effective bandwidth and to hide the latency of main memory. Such SIMD vector systems could be a competitive choice for FPGA based System-on-Chip (SoC) designs to meet the demand of par-allelism for HPC benchmarks.

In our previous work, we implemented a memory controller called Programmable Pattern based Memory Controller (PPMC) which handles data movement and com-putation tasks in hardware. This work extends the PPMC based vector system by arranging data/address in hardware and scheduling computations without the intervention of the microprocessor and operating system. We further parameter-ize the data cache to allow a designer to more powerfully trade area for perfor-mance scaling, for data parallel applica-tions. By combining all functions into one chip, the PPMC based vector system has higher complexity, but it becomes smaller, faster, and less power consuming. To decrease time-to-market, specialized hard-

ware accelerator IPs are integrated with the system.The PPMC system is evaluated with memory intensive accelerators -- Graphics, Network Filter applications -- and tested on Xilinx and Altera FPGA boards. With this innovative approach, it is demonstrated that the PPMC core improves system per-formance by reducing the speed gap between accelerators/vector/processors and memory, and by scheduling and managing complex memory patterns without master core intervention. The PPMC system provides strided, scatter/gather and tiled memory access support, which eliminates the overhead.

About the author: Tassadaq Hussain is a Ph.D. researcher at the Universitat Politècnica de Catalunya, BarcelonaTech. Currently his research focuses on studying the use of vector accelerators for super-computing purposes. His main focus is to schedule multi accelerator/vector proces-sor data movement in hardware. At the theoretical level, he is proposing novel architectures for the acceleration of HPC applications.

Tassadaq HussainBSC-Microsoft Research, Spain_________

A HiPEAC collaboration grant was given to Karthik Chandrasekar from TU Delft who will join our group as a guest researcher to deepen his knowledge of DRAMs and DRAM modelling.

More Information on: http://www.uni-kl.de/3d-dram

Matthias Jung, Christian Weis, Norbert WehnUniversity of Kaiserslautern, Germany_________

The Programmable Pattern-based Memory Controller (PPMC).

Physical view of a 3D-DRAM subsystem composed of 4 channels.

Poster presented by Tassadaq Hussain during the seventh Microsoft Research Summer School that took place in Cambridge, U.K., 2-6 July 2012

PPmc: oN cHiP memory maNager aNd scHeduler for vector Processor

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in the spotlight

Project Title:REFLECT (Rendering FPGAs to Multi-Core Embedded Computing)Project Coordinator:Zlatko Petrov, Honeywell Inter national, s.r.o, (Brno, Czech Republic)Partners:• Honeywell Aerospace• Institute for Systems and

Computer Engineering, Research and Development in Lisbon

• Faculty of Engineering of the University of Porto

• Technical University of Delft• Karlsruhe Institute of Technology • Imperial College of Science,

Technology and Medicine• ACE Associated Compiler Experts b.v.• Coreworks, s.a.Project website:http://www.reflect-project.eu Project start date:January 2010Duration: 36 months

“One application, multiple designs according to different requirements”

fP7 reflect ProJect: reNderiNg fPgas to multi-core embedded comPutiNg

functions as possible, it is certainly desirable to limit the number of hardware components in order to reduce size, weight and power of products thus reducing development and maintenance costs.Reconfiguration has been recognized as a key technique to achieve these goals. Designing reconfigurable system solutions, however, is an extremely cumbersome and error-prone process as it requires developers to assume the role of software and hardware experts. As a result, the potential of recon-figuration is only achieved with a high design effort and cost, and is often never fully exploited. The REFLECT project thus aims at developing and demonstrating techniques and tools that enable improved productivity by substantially accelerating development cycles of reconfigurable systems.

Project GoalsThe REFLECT project aims to develop, vali-date and evaluate a novel compilation and synthesis system approach that relies on Aspect-Oriented Specifications to convey critical domain knowledge to all develop-ment steps, and help designers build efficient FPGA-based heterogeneous multi-core compu ting systems. Our research and development agenda aims at developing a new foundation that combines distinct but synergistic areas of research: aspect-oriented specifications, hardware compilation, design patterns and hardware templates. Overall, this project's goals include: • Making reconfigurable technology

acceptable for avionics and audio/video domains• Lowering barrier of adoption of

technology• Enabling system portability to new

and future architectures • Improving productivity

• Accelerating design cycles by more than two orders of magnitude

• Allowing the user to have full control of design flow stages

• Controlling design and mapping in a consistent, systematic and verifiable way

Demonstration anD UseThe REFLECT consortium is evaluating the effectiveness of its approach with codes from the domains of audio processing and avionics. Four applications have been selected: MPEG audio encoding - the ISO reference code for Layer 3 MPEG-2 encod-ing; G.729 - an audio data compression algorithm that compresses digital packets of 10 ms duration; 3D path planning – com-puting a path between the current and goal vehicle positions integrated as part of modern UAVs, Stereo navigation – used in airplane localization in case a GNSS is tem-porarily unavailable and the plane has to localize itself for a period of time.

Project HiGHliGHts• “One application, multiple designs

according to different customer requirements” with reduced verification and validation costs thus substantially reducing overall development costs:• In a traceable way through the

notation of Requirements-Aspects-Design Patterns and Hardware Templates;

• With pre-verified Design Patterns and Hardware Templates for correctness and reuse;

• Systematic approach to Guide Design Flow Stages• Pruning design space exploration given

requirements and derived aspects• Enabling the development of cost-

effective designs• Allowing Specification of Reusable Design

Patterns and Best Practices • Capturing and codifying application- and

platform-specific knowledge and expertise

recent acHievementsIn Q3 2012, the REFLECT partners delivered a flexible integrated toolchain with an Aspect-Oriented design methodology which combines in a unified framework: software and hardware descriptions, application requirements and mapping strategies. The current version of the REFLECT toolchain allows: i) flexibility, i.e. to configure and use

Key innovationsThe need for additional product function-alities, such as safety and security, drives many product suppliers towards the need for increased platform performance. As an example, the next generation of UAVs (unmanned aerial vehicles) are expected to be much more complex in terms of sensing, and correspondingly more power-ful in terms of computing, as required by an increased complexity of underlying device analyses and decision-making pro-cesses. Audio encoding is another example where better performance and improved encoding quality are features of major interest. While these requirements are met by implementing in hardware as many

HiPeac info 32 15

in the spotlight

Project titleMULTIPARTES (MULTI-cores PARtitioning for Trusted Embedded Systems)Project coordinator:Dr. Salvador TrujilloIK4-IKERLAN, SpainPartners:• IK4-IKERLAN, Spain• ALSTOM WIND, Spain• FentISS, Spain• Technische Universität Wien, Austria• TELETEL, Greece• TRIALOG, France• Universitat Politècnica de

València, Spain• Universidad Politécnica de

Madrid, Spain• Visual Tools, SpainProject website:http://www.multipartes.eu/Project start date:September 2011Duration:36 months

Enabling significant cost reduction by hypervisor virtualization for multicore

multiPartes 2012 advisory board gatHered relevaNt euroPeaN stakeHolders from academia aNd iNdustry

The Advisory Board members are Dr. Guillem Bernat (Rapita Systems, UK), Dr. Tasos Dagiuklas (Univ. Messolonghi, Greece), Mr. Patrick Leteinturier (Infineon Technologies, Germany), Mr. Glenn Farrall (Infineon, UK), Prof. Marga Marcos (Univ. Basque Country, Spain), Dr. Michael Paulitsch (EADS, Germany), Dr. Øystein Haugen (SINTEF, Norway) and Mr. Marco Zulianello (ESA, Netherlands). The AB members have diverse expertise, includ-ing certification, multicore hardware, modelling languages, verification and validation for embedded systems (further details on AB members is available at multipartes.eu). This diversity guaranteed that all views were considered and future impacts were anticipated, especially in

The MultiPARTES FP7 project aims to define a comprehensive approach to mixed-criti-cality systems engineering, based on hypervisors as the mechanism for multi-core virtualization in industrial applica-tions. The goal is to reduce cost by 25% and improve computation capability in terms of performance, while ensuring maximum reliability and other criteria (e.g. reduce energy consumption and volume, reduce wires and connectors). With the purpose of providing advice and guidance to the project, a group of experts gathered on July 18th at the first Multi-PARTES Advisory Board meeting. The School of Engineering at Bilbao (Spain) hosted a fruitful discussion on the research work developed by the project so far. Different viewpoints were presented, each sharing their scientific, technological or market perspective and knowledge.

different tools in a design-flow, ii) third party tool integration such as Xilinx ISETM

for synthesis and gprof for performance

profiling, and iii) seamless refinement of requirements down to design through the concept of aspect-design patterns-templates.

Overall, the toolchain allows customization according to the design target. The input to our toolchain consists of: 1) user-provided functional application code in a high-level language (C or MATLAB) and 2) user-provided non-functional require ments and cross-cutting concerns captured using the LARA language for compilation and synthesis onto target multi-core reconfigurable architectures. The toolchain automatically generates a specific hardware/software implementation and can engage in design-space exploration that is controlled by the user using LARA-specified strategies.

The REFLECT project partners are organizing a Fall school for demonstration and training sessions dedicated to the REFLECT design flow. More information about this event is available through our project web page._________

Advisory Board members during AB session in Bilbao (from left to right): Mr. Farrall, Mr. Zulianello, Dr. Haugen and Prof. Marcos

HiPeac info 3216

in the spotlight

Project title:EU-INCOOP (EU-INdia Fostering COOPeration in Computing Techno logies)Project coordinator:Dr. Sotiris Ioannidis, FORTH, GreeceProject Partners:• FORTH, Greece• KYOS SARL, Switzerland• The Open Group• Interactive Technology, Software and

Media Association (ITSMA), India• Centre for Development of

Advanced Computing (C-DAC), India• Indian Institute of ScienceProject website: www.euincoop.euProject start date: 1st October 2011Project duration: 24 months

Supporting EU 's leading position in computing systems while ensuring mutual benefits to both EU and India

fP7 eu-iNcooP ProJect: fosteriNg eu- iNdia cooPeratioN iN comPutiNg systems

The first EUINCOOP event was organised during the HiPEAC Spring Computer Systems Week in Göteborg, Sweden on 24th April 2012. The panel discussions led to a clear understanding of the need for collaboration with India, to complement the research activities in next-generation computing system technologies. The HIPEAC coordinator suggested organising a study/community networking delegation from Europe to visit Indian Competence centres, to develop a better understanding of possible opportunities in Computing systems research, including the exchange of experts and students between Europe and India.

As a follow-up after Göteborg, to identify common research priorities between EU and India and to draw up a preliminary research roadmap, the project EUINCOOP

The project aims to further existing coop-eration and bolster future cooperation through a series of activities spanning from identification of common priorities between the two regions. The project further endeavours to bring out a joint research roadmap to jump start coopera-tion in a few priority areas and to make recommendations to both governments on topics for sustained cooperation. India has an approved plan of 1 billion dollars to invest in developing a supercomputer. To spearhead this mammoth initiative, Indian Institute of Science has been chosen. India’s defence, atomic energy, aerospace and space labs with expertise in design and architecture of supercomputers will be involved to coordinate the project.

the automotive, semiconductor and aero-space sectors.

Modern embedded applications typically integrate a multitude of functionalities with potentially different criticality levels into a single system. The Automotive

industry is a key example. A modern vehicle involves more than fifty control systems such as braking, motor control, entertain-ment, and navigation. Each system has a specific purpose and specific hardware and software to achieve it. Integrating all into one multicore platform will result in a

significant reduction in the occupied space, energy consumption and hardware cost.

Without appropriate preconditions, the integration of mixed-criticality subsys-tems can lead to a significant and poten-tially unacceptable increase in certification efforts. The approach of MultiPARTES is to avoid the increased validation and certifi-cation effort by incorporating mechanisms that establish multiple partitions with strict temporal and spatial separation. In this approach, subsystems with different levels of criticality can be placed in differ-ent partitions and can be verified and vali-dated in isolation.MultiPARTES is partially funded by the EU FP7 program with 2.85 million euros, and it has a total budget of over four million euros. This research work will contribute to strengthening the leadership and excel-lence of Europe in the development of systems and tools for the engineering of dependable multicore embedded systems.More info at:http://twitter.com/#!/FP7MultiPARTEShttp://www.youtube.com/user/FP7MultiPARTES_________MultiPARTES: From single cores to Multi/Many-core

HiPeac info 32 17

in the spotlight

organized, jointly with the EUCLID project, a second event on 7-8 August 2012, in Bangalore. The academic and scientific partner Indian Institute of Science (IISc), which also hosts the Supercomputer Education and Research Centre, provided all necessary logistics for the event. The first day of the workshop was devoted to the supportive discussion to enhance cooperation in complex systems engineer-ing related to computer embedded systems. Noted industry and academic experts from the field delivered talks relating to the current work and level of research in complex systems engineering. Speakers from Indian Institute of Tech-no logy-Delhi, Indian Institute of Science-Bangalore, GE-India Global Research- Bangalore, “Honeywell Technology Solutions”-Banga lore, Tata Innovation Labs, KYOS Technologies-Switzerland and Intel India expressed keen interest in collaborating with Europe to find innovative solutions for important societal challenges which are common to both regions. Day 2 of the workshop concentrated on discussion leading to the priority topics that Indian industry and academia can address on furthering the future of com-

puting systems. It was a fruitful discussion marked with takeaways in terms of con-vergence of immediate research priorities, research needs and expression of interests to collaborate to further mutual interests. The highlight of the workshop was five keynote talks communicating the perspec-tives of industry and academia. Infineon technologies India, Forus Health care India Limited- Bangalore, Centre for Advanced Computing- Bangalore, and Indian Institute of Science- Bangalore participated and discussed collaborative opportunities. Professor Jamadagni from IISc and Dr. Sathya Rao from Kyos Technologies-Switzerland, who are project partners, talked about the many opportunities that FP7 projects offer to countries like India. The response was very encouraging with all participants keen on participating in the upcoming calls. The results of these two workshops will be taken into account in developing the Euro-India joint roadmap for future computing system research.

Sathya Rao,KYOS Technologies, Switzerland_________

Participants during the workshop held in Bangalore.

By Marios Kleanthous,University of Cyprus, CyprusAdvisor: Prof. Yiannakis SazeidesApril 2012

cacHe coNteNt duPlicatioN

This thesis identifies the Cache Content Duplication (CCD) phenomenon. CCD occurs when there is a miss for a block in a cache but the content of the missed block is already in the cache under a different tag. CCD is examined at all levels of the memory hierarchy: (1) single-thread L1 Icache, where a hardware mechanism (CATCH) is proposed that improves perfor-mance up to 25%, (2) multi-thread L1

Icache, where it is shown that Text Cloning can harm performance by 11% and CATCH can recover this loss, (3) L1 DCaches, where the analysis shows mostly zero block dupli-cation, (4) and LLCs for single and multi program workloads, where a CCD-aware cache is proposed, which reduces the Energy delay product by up to 15%._________

PhD news

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PhD news

Transactional Memory (TM) is a promising paradigm for parallel programming that offers an easier-to-use alternative to lock-based synchronization. In this thesis, we provide hardware support for TM that: (1) has a scalable protocol for conflict man-agement, (2) has precise (rather than approximate) conflict management, and (3) supports large transactions, larger than the private caches of a processor core. Our key observation was that even though a

transaction may touch many lines, very few lines actually generate conflicts and significantly impact the performance. By distinguishing between conflicting and non-conflicting lines, we are able to signifi-cantly reduce the hardware requirements._________

camera that can autonomously react to environmental changes, as varying illumi-nation conditions, by changing the image processing algorithms serves as a case study for evaluating the methodology._________

By Sasa TomicUniversitat Politècnica de Catalunya, SpainAdvisors: Dr. Adrián Cristal and Dr. Osman UnsalJuly 2012

By Stefan WildermannUniversity of Erlangen-Nuremberg, GermanyAdvisor: Prof. Dr.-Ing. Jürgen TeichJuly 2012

By Dyer Rolán, Universidade da Coruña, SpainAdvisors: Prof. Basilio B. Fraguela and Prof. Ramón DoalloJune 2012

toward a ligHtweigHt aNd HigH-PerformaNce Hardware traNsactioNal memory

systematic desigN of self-adaPtive embedded systems witH aPPlicatioNs iN image ProcessiNg

This thesis deals with the design of embed-ded systems that are able to adapt their functionality at run-time to changes in their environments. It presents a concept to build computer architectures based on reconfigurable hardware that can replace hardware modules dynamically and par-tially at run-time. Furthermore, a design methodology is introduced which applies mathematical optimization techniques to automatically synthesize and optimize self-adaptive systems on these computer architectures in the presence of stringent design constraints. The design of a smart

cacHe desigN strategies for efficieNt adaPtive liNe PlacemeNt

This dissertation aims to analyze some of the problems commonly found in modern caches and to propose cost-effective solutions to improve cache performance in many different environments. Most of the approaches proposed in this thesis take advantage of the different levels of demand experienced by cache sets, in order to reduce cache miss rates. Throughout this process we used a simple and cost-effective metric to track the state of each cache set, called Set Saturation

Level. It is worthwhile pointing out that our approaches are very competitive and often outperform many of the most recent techniques in the field, despite implying small storage and power consumption overheads._________

HiPeac info 32 19

PhD news

average system performance. These evalu-ations show that, for real-time systems, D-ISP is a promising alternative to common first-level instruction memories._________

of the impact of using the Megablock as a detection unit, over a comprehensive set of benchmarks. Experiments considering a coarse-grained reconfigurable array as RPU reveal an average overall execution speedup of 5.6x over the software execution._________

By Stefan MetzlaffUniversity of Augsburg, GermanyAdvisor: Prof. Dr. Theo UngererJuly 2012

By João Carlos Viegas Martins BispoInstituto Superior Técnico, Lisboa, PortugalAdvisors: Prof. João M. P. Cardoso and Prof. José Carlos Monteiro July 2012

aNalysable iNstructioN memories for Hard real-time systems

maPPiNg ruNtime-detected looPs from microProcessors to recoNfigurable ProcessiNg uNits

This thesis proposes the dynamic instruc-tion scratchpad (D-ISP). The D-ISP features function-based dynamic content manage-ment which ensures that the currently executed function is always contained in the scratchpad. Hence, it guarantees a pre-dictable and instantaneous instruction fetch, once the active function is loaded. The D-ISP was verified in a SystemC model and implemented in an FPGA. Also a static timing analysis was performed. Evaluations quantified the impact of the D-ISP on hardware complexity, WCET estimates, and

This thesis proposes novel techniques for dynamically partitioning applications at the binary level. The approach addresses the automatic migration of computations during runtime, from a general purpose processor to a Reconfigurable Processing Unit (RPU) acting as its coprocessor. The proposed techniques focus on the identifi-cation of loop structures, known as Megablocks, and their mapping to the RPU. The work shows methods and algo-rithms for the detection, identification, implementation, and optimization of Megablocks, as well as an extensive study

must be adapted. This dissertation investi-gates the impact of this new machine interface on operating software and suggests further refinements to the hardware design._________

By Raphael PossUniversity of Amsterdam, The NetherlandsAdvisor: Prof. Dr. Chris JesshopeSeptember 2012

oN tHe realizability of Hardware microtHreadiNg – revisitiNg tHe geNeral-PurPose Processor iNterface: coNsequeNces aNd cHalleNges

The CSA group at the University of Amsterdam is investigating a new design for multi-cores towards faster and more efficient general-purpose processor chips, called “hardware microthreading”. However this design changes the interface between the hardware and software, compared with existing chips, in ways that have not been dared previously. Consequently, before this new design can be fully integrated and evaluated, the concepts underlying existing operating systems and compilers

upcoming events

conference on design and architectures for signal and image Processing (dasiP 2012)23-25 October 2012, Karlsruhe, Germany http://www.ecsi.org/dasip/

the 45th ieee/acm international symposium on microarchitecture (micro-45)1-5 December 2012, Vancouver, Canada http://www.microsymposia.org/micro45/

the 19th ieee international symposium on High-Performance computer architecture (HPca-19)23-27 February 2013, Shenzhen, China http://www.hpcaconf.org

the 18th acm sigPlaN symposium on Principles and Practice of Parallel Programming (PPoPP 2013)23-27 February 2013, Shenzhen, China http://ppopp2013.ics.uci.edu/

the international symposium on code generation and optimization (cgo 2013)23-27 February 2013, Shenzhen, China http://www.cgo.org/cgo2013/

the international conference on compiler construction (cc 2013)16-24 March 2013, Rome, Italy http://www.etaps.org/2013/cc13

the 18th international conference on architectural support for Programming languages and operating systems (asPlos 2013)16-20 March 2013, Houston, TX, USA http://asplos13.rice.edu/

the 16th design, automation and test in europe conference (date 2013)18-22 March 2013, Grenoble, France http://www.date-conference.com/

the european conference on computer systems (eurosys 2013)15-17 April 2013, Prague, Czech Republic http://eurosys2013.tudos.org/

the ieee international symposium on Performance analysis of systems and software (isPass 2013)21-23 April 2013, Austin, TX, http://ispass.org/ispass2013/

the 23rd international conference on field Programmable logic and applications (fPl 2013)2-4 September 2013, Porto, Portugal http://www.fpl2013.org/

tHe 8tH iNterNatioNal coNfereNce oN HigH PerformaNce aNd embedded arcHitectures aNd comPilers (HiPeac 2013),

21-23 JaNuary 2013, berliN, germaNy

info 32

hipeac info is a quarterly newsletter published by the hipeac network of excellence, funded by the 7th european framework programme (fp7) under contract no. ist-217068.website: http://www.hipeac.net.subscriptions: http://www.hipeac.net/newsletter

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