Network of excelleNce oN HigH PerformaNce aNd embedded

arcHitecture aNd comPilatioN

autumN comPutiNg SyStemS week, gHeNt, belgium, october 15-17, 2012

welcome to acaceS’12, fiuggi, italy,

July 8-14, 2012

www.HiPeac.Net

info 31

appears quarterly july 2012

tHematic SeSSioNS Succeed aS NetworkiNg iNStrumeNtS iN HiPeac3

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meSSage from tHe HiPeac coordiNator

coNteNt

intro

Last month, I got the first request by a student from Ghent University to get credit for an internet course he took at Berkeley University. Around the same time, Stanford University announced the results of the introductory course on artificial intelligence, taught by Peter Norvig and Sebastian Thrun, and which attracted no less than 160,000 students, from 190 coun-tries. After checking the website, I discov-ered that that the video fragments for that course were translated by volunteers into 44 languages, including Dutch. Almost daily, I am surprised by the amount of technical knowledge my 12-year old son is soaking up from the web (using YouTube, Wikipedia, Google Translate, …). The clear preference of kids to learn stuff from the web rather than at school, and the high quality web-offerings by renowned insti-tutions might mark the beginning of an educational revolution. It might lead to a situation in which there will be less need for lecture rooms, in which governments might be tempted to cut down budgets for public education, in which students might not be willing to pay high tuition fees anymore. In order words, it may dramati-cally change the current business model of higher education. Will universities in the

long term face the same fate as music shops, video stores, bookshops, and news-papers? And if this happens, what will happen with the research done by these universities, and the innovations that come out of it? In April, we enjoyed the Spring Computing Systems Week in Göteborg, organized by Per Stenström and his team. With 138 attendees, this was a well-attended net-working event. Personally, I very much appreciated the business prototyping workshop by Sören Sjölander from Chalmers Innovation. In this workshop he helped two FP7 projects to think about the commercialization opportunities for their research results. The attendees of this workshop were enthusiastic about the outcome of the event. We plan to organize more such events in the future. The next Computing Systems Week will take place in Ghent, in the third week of October. It will feature the first HiPEAC industry partner event, and several tech-nology keynotes.In April, we also passed the final review of HiPEAC2. The reviewers were pleased by the progress we made over the last four years. They concluded that the network fulfilled its expectations; it has since its

intro

2 message from the hipeac coordinator

3 message from the project officer

hipeac activity

4 hipeac spring computing systems Week, göteborg

6 hipeac csW göteborg - business prototyping Workshop

7 hipeac booth at date 2012

hipeac announce

7 Welcome to multicore day 2012

8 memristors for computing (memco) Workshop

hipeac news

8 paul carpenter takes over hipeac neWsletter proofreading role

8 rWth aachen exhibits maps at design West/multicore devcon

9 photonic interconnect technology for chip multiprocessor architectures

10 hipeac Welcomes neW members from leading slovenian academic and research institutions

11 neW hipeac member: hrvoje mlinaric , university of Zagreb

in the spotlight

12 fp7 alma project: can programming of reconfigurable multi-cores be easier, please?

13 fp7 virtical project: improving performance, programmability, security and Qos of embedded devices

14 fp7 enosys project: integrated modelling and synthesis tool floW for embedded systems design

15 fp7 carp project: european researchers to tackle accelerator programming

16 median project: manufacturable and dependable multicore architectures at nanoscale

17 presto project: fostering analysis on industrial embedded systems development process

18 phd news

20upcoming events

creation triggered fundamental changes in the European computing systems com-munity, and it has created a long lasting impact in Europe. They mentioned the HiPEAC roadmap, the well-attended HiPEAC conference with its journal-first publication model and the yearly ACACES summer school as major accomplish-ments. They encouraged HiPEAC to con-tinue building on a vibrant computing systems community in Europe.This newsletter issue is the summer school issue. This year, we have a very high number of attendees, making it the sec-ond-best attended summer school ever. The summer school also marks the begin-ning of the summer break for me. I wish you a relaxing summer with your family and friends, and I hope to see you again after the summer holiday in good health, and full of plans for the year to come.Take care, Koen De Bosschere_________

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intro

The next Call for Proposals in the FP7-ICT research programme is scheduled for publication in July 2012. I give here the main areas related to the Computing Systems Call for Proposals. Please consult our Cordis web site to find the full official text of the Call and all related information for preparing and submitting proposals including the deadline and the type of proposals for each area.

Next geNeratioN of eNergy- aNd coSt-efficieNt ServerS for data-ceNtreSSystem design addressing the full server eco-system: processor, chip, board, rack, storage, network, data-centre, system soft-ware, applications. Research challenges include: taming the data deluge; holistic integration of hardware and software in future servers including 3D-stacked server chips or optical interconnects; operation and load-balancing over a collection of physically distributed sites. Being highly ambitious (targeting two orders of magni-tude improvements in total cost of owner-ship and energy efficiency) with strong industrial participation and a clear path to commercialisation, projects should deliver a full prototype and validate it under real-life workloads from various application areas including clouds.

coNtrol iN embedded SyStemS witH mixed criticalitieS SHariNg comPutiNg reSourceSInnovative solutions capable of managing design, modelling, verification, validation and certification of networked complex systems featuring an extended functio-nality through seamless integration of mixed criticalities. Focus is on data, energy and system integrity in addition to security, safety and performance when exploiting multi-core chips or heterogeneous distri-bu ted systems. An integrated approach is expected, on the one hand addressing fundamentally new perspectives of control and computing and on the other hand building on existing or emerging approa-ches for standardisation and certification. Work should encompass prototyping and validation of the developed methods and architectures in a minimum of two appli-cation domains.

exPloitiNg SyNergieS aNd StreNgtHS betweeN comPutiNg SegmeNtSBringing together teams from embedded computing and high-performance com-puting to jointly address challenges that are common in these two areas and are magnified by the ubiquity of many-cores and heterogeneity across the whole com-

meSSage from tHe ProJect officer

puting spectrum. Examples of challenges include: low-power and energy efficiency, performance analysis, dependability, time-criticality, hybrid programming, paralleli-sation, compilation, debugging, co-design, customisation, virtualisation, reconfigura-bility. Projects should focus on one specific and credible common challenge and prove a real cross-fertilisation of expertise.

acceSS to Novel comPutiNg tecHNologieS for iNduStryAccess services for technology transfer from academia to industry in computing, including activities to strengthen links to venture capital and promoting entrepre-neurship. The aim is to facilitate the trans-formation of research prototypes to products and services and to introduce lead customers to technologies and tools for multi-core and hybrid systems across the computing spectrum.

Panos Tsarchopoulos_________

Fiuggi

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hipeac activity

Thematic sessions, the new HiPEAC-3 instrument for dissemination of research results and networking

HiPeac SPriNg comPutiNg SyStemS week, göteborg

propose a thematic session, on condition that it is related to the HiPEAC vision. Although the format is not pre defined, a thematic session should be comparable to an informal workshop, with invited con-tributions and a strong presence of active EU projects and HiPEAC companies.

The instrument was exercised for the first time during the Computing Systems Week in Göteborg (April 24-25, 2012). As a result of a first call launched by mid February, a program with eight thematic sessions was designed. In addition, a special thematic session was organized the second day to present the main conclusions of a work-shop held on the previous day to identify viable business ideas in FP7 projects. Before presenting a short summary of each one of the sessions, I just want to thank Fran Cazorla, Grigori Fursin, Georgi Gaydadjiev, Marisa Gil, Stefanos Kaxiras, Hugh Leather, Sathya Rao and Andras Vajda (and their colleagues) for the enthusiasm in organi-zing them. Additional details and slides for most of the presentations are available through the HiPEAC website.

real-time: deSigN for time Predictability aNd comPoSabilityThis thematic session brought together more than 30 people from industry and academia to discuss the approach taken

by the different European projects that were presented (PROARTIS, MERASA, parMERASA, T-CREST, ACROSS, MultiPARTES and HiPARTES). The representative of each project took the opportunity to share the work done in the project and discuss the pros and cons of the different approaches taken by the different projects. Additionally, Thales presented its work on Real-time on multi-core for Flight Management Systems and the CISTER Research Centre presented an overview of its activities in the field. A round-table session of about one hour was held at the end of the session, where some key concepts and challenges in future real-time embedded systems were discussed. The session was successful in bringing together more than 30 people, who par-ticipated vividly in all discussions.

collective cHaracterizatioN, oPtimizatioN aNd deSigN of comPuter SyStemSThe main purpose of this other thematic session on was to build a community inter-ested in a new collective R&D metho-dology and publication model in computer engineering that favours collaborative data sharing and mining. The session fea-tured four presentations, covering the cTuning.org collaborative optimization repository and tools, run-time adaptation for heterogeneous architectures, soft-ware/hardware co-design and multi-objective optimizations. The session was well attended and resulted in active parti cipation and multiple discussions. Most importantly, we managed to identify several collaborative groups that would like to keep in touch to brainstorm common optimization repository and tools for HiPEAC3 and to promote a new publication model where experimental results can be easily validated by the community.

deSigN aNd ruNtime maNagemeNt of recoNfigurable SyStemS In this session, the high design complexity of modern reconfigurable systems was dis-cussed. The four presentations focused on dynamic, partial reconfiguration that not

Panos Tsarchopoulos talked about the next FP7-ICT Call for Proposals during his keynote speech.

Ian Bratt presented the research and product directions in ARM.

As part of the research coordination program, HiPEAC3 includes a new instrument, called Thematic Sessions, which replaces the clusters and task forces in HiPEAC2. Thematic sessions are self-organized and reactive to the needs and interests of the community: any partner or member can

HiPeac info 31 5

hipeac activity

only enables new opportunities for runtime hardware customization but also brings an additional degree of options necessary to consider in the context of the evolving application requirements, e.g. performance, available power, hot spot temperature and reliability level to name a few. The session discussed how to tame the exploding design complexity through various innovative approaches toward runtime reconfiguration. The importance of considering the complete "food-chain" from algorithms and programming models, through runtime system extensions, down to specific architectural and microarchitec-tural provisions was also emphasized. The session also included a panel discussion that covered the following propositions: 1) Everybody is in agreement about the definition of (dynamic) reconfigurable systems; 2) Partial reconfiguration is a mature and widely accepted technology; 3) Designing and managing reconfigurable systems with dynamic reconfiguration is easy; 4) The big winners (the applications / products) for dynamically reconfigurable technology are clearly identified; and 5) Verification, test and debug of partial reconfigurable systems is as complex as in the case of traditional systems. The very lively 30-minute discussion involving all session attendees provided new insights on the majority of the above topics.

ruNtime SuPPort for HomogeNeouS aNd HeterogeNeouS ScHeduliNgProposed as a continuation of the “Programming models and OS” HiPEAC-2 cluster, this session was a success with 75 attendees. The session featured a plenary keynote by Ian Bratt, presenting the research and product directions in ARM, and three talks presenting the results on several European Projects (ENCORE, Mont-Blanc and DEEP) to stimulate ideas in the field as well as future collaborations. They mainly focussed on scheduling for task parallelism, supporting tasks with irregular and dynamic memory footprint and/or real-time constraints, and locality-aware scheduling for heterogeneous architec-tures. The questions at the end gave rise to an interesting discussion about future computers and the runtime to manage and make the most of them.

Power-efficieNcy aNd Program correctNeSS aNalySiS for Scalable multicoreSThis thematic session aimed to shed light on analysis for scalable multicores. As more and more cores are integrated on a chip, better tools and methodologies are needed to analyse the performance, power, and scalability of such architectures and implementations. The session comprised four talks, three of them from research groups at Uppsala University and one from the 2Parma EU project.

mobile SyStemSThe thematic session on “Mobile systems” was organized with the idea to build a community around this topic. The session started with the keynote given by Chris Vick from Qualcomm research, two deeply technical presentations with lots of juicy, science meat to chew on, and a quick tutorial on Android's Dalvik system. On top of that the room had comfy sofas and armchairs, and was mostly full.

euiNcooP ProJectOne of the thematic sessions focussed on the “EUINCOOP project”, whose objective is to stimulate cooperation between EU and India in computing technologies. The three experts from India and five from Europe provided their visionary contribu-tions, including a talk from the EUINCOOP project officer, providing an overview of on-going activities in Europe and future plans for the HORIZON2020 programme. The session was well attended with more than 30 persons. The panel discussions led to a clear understanding of the need for collaboration with India, to complement

the research activities in next generation computing system technologies. The HIPEAC coordinator suggested to organise the study/community networking delega-tion from Europe to visit Indian Compe-tence centers, so as to develop a better understanding of possible opportunities in Computing systems research, including the exchange of experts and students across Europe and India.

tecHNologieS for tHe Next wave of cloud comPutiNgMainly focussed on the new technologies being developed within the FP7 Eurocloud project, the session featured two presenta-tions, one general about the project and another more specific on fault tolerance issues.

buSiNeSS PrototyPiNgOne important aim of HiPEAC is to promote successful technology transfer initiatives. As part of the HiPEAC Compu-ting System Week in Göteborg, Professors Sören Sjölander, Henrik Berglund, Per Stenström, and Georgi Gaydadjiev of Chalmers University of Technology

Thematic Sessions were very successful and enjoyed good attendance.

CSW participants during the reception at the City Hall of Göteborg.

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hipeac activity

The workshop focused on identifying potentially valuable business ideas in out-comes of the research, and on the business side of technology transfer. Prof. Sören Sjölander and Henrik Berglund from the Center for Business Innovation (CBI) at Chalmers University of technology led the workshop, and presented the framework that they developed and that was already applied in various scenarios varying from start-ups to established companies. The ENCORE project was represented with two innovations: the OmpSs programming model, presented by Barcelona Super-computing Center (BSC), and the Formic many-core prototype presented by FORTH, while the MultiCube project was represented with the tool for performing design space exploration.

The workshop provided the opportunity to present the research to experts from industry, and fostered a lively discussion about potential technology transfer to industry. The two projects presented their vision of the potential impact of ENCORE innovations, and that initiated the discus-sion with industry experts on the possible ways to implement technology transfer. As the outcome, potential products, ways to generate value, sales, marketing and support channels were identified.

One of the main lessons learned is that in order to turn research ideas into products, it is crucial to identify the possibilities early on, to be ahead of the competition, and to establish clearly the steps needed for the commercialization. It was clear that in many cases when efforts for starting a successful business do not work, the reason is a lack of customers and the fact that people working on technology usually know the technology much better than they know the market. It was also made clear that selling a product is not a hard problem, but that the main challenge is to get really engaged with customers. To this end, 24/7 customer support is crucial for developing the business. Customer engage ment is usually also achieved by sending experts to customers to learn about

customer structure and way of thinking, in order to provide personalized service. In the case when the technology is useful to the customer, it will be considered as a valuable product in the company.

As an example, in the case of the OmpSs programming model, the main suggestion is that we would need to increase user support. For this, the most suitable option is to establish a spin-off company out of BSC, and start giving support directly to OmpSs users for a financial compensation. Also, a large effort towards improving the debugging capabilities of OmpSs is needed to improve the technology itself.

Overall, the workshop was a very rewarding experience, and we learned the mechanisms that would allow us to start a business based on our research ideas. This can be the starting point for a nice adventure out of it. The outcomes and conclusions of the workshop, together with the summary of business ideas identified for the ENCORE and MultiCube projects was presented at a special session the next day with over 50 participants.

Nikola Puzovic and Xavier Martorell, BSC/UPC, Spain_________

Partners from two European projects, ENCORE and MultiCube, were invited to participate in the Business Prototyping workshop organized by the European Research Center on Computer Architecture (EuReCCA).

HiPeac cSw göteborg - buSiNeSS PrototyPiNg workSHoP

Henrik Berglund referring to Facebook during the Business Prototyping workshop.

organized a workshop that aimed at identifying viable business ideas in tech-nologies developed in two FP7 projects – the Encore and the Multicube projects. Sjölander and Berglund first presented a general framework for how to identify business ideas. Representatives from the projects then presented their technologies and their initial views on which ideas in the technology have commercial value. In a break-out session with small groups composed of participants from the projects and technology experts with business expertise, value propositions and business models were carved out and later on reported back in a plenary session.

A special thematic session was organized the second day to present the main conclusions of the workshop held on the previous day. This session comprised a presentation of the general method for business idea identification followed by presentations of the outcome of the exer-cise when applied to the FP7 Encore and Multicube projects. This exercise gave many unexpected and new insights and sparked a key interest in offering this work-shop in future HiPEAC organized events.

We want to encourage you to submit proposals in the forthcoming calls for thematic sessions. With the summary

presented here, I hope you realized this new HiPEAC-3 instrument is an ideal way to promote your research areas in the HiPEAC community, to share your own research results, and to build a network of researchers from which you can form a consortium for a future project proposal. Volunteering to organize a thematic session is an opportunity to contribute to the HiPEAC community, helping the HiPEAC network to work on the challenges identified in the HiPEAC roadmap and to highlight new ones.

Eduard Ayguadé, BSC/UPC, Spain_________

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hipeac activity / announce

HiPEAC representatives explained the basic aspects and benefits of joining the network to DATE attendees.

HiPeac bootH at date 2012

One of the main goals of HiPEAC is to keep the community updated about the events, research projects and results within the network. The best way to do this is by showcasing HiPEAC and its subprojects in some of the mainstream community events, such as the Design Automation and Test in Europe (DATE) conference. The conference not only features paper presentation sessions in areas ranging from system-level design down to physical IC design, but also includes several keynotes from industry partners and two days for tutorials and workshops. This year's DATE was held in Dresden from March 12th to

16th and comprised 57 regular and 20 special sessions. The conference had a total of 974 submissions and more than 2000 visitors, of which many stopped by our booth to get to know HiPEAC or be updated about our progress.

This year's booth also had the special purpose of introducing HiPEAC-3 to the DATE visitors, so they could learn about the differences between the second and third rounds of the project. Among the HiPEAC members, the most popular subjects were the migration of the publication model of the HiPEAC conference, access to funding for academic activities, and the institution of the thematic sessions as an opportunity for networking. HiPEAC events such as the computing systems week in Göteborg and this year's summer school in Fiuggi were also hot topics. As expected, the insights into the network and the potential bene-fits of joining were most interesting for non-members. As HiPEAC representatives, we explained to them the basic aspects and benefits of the network and encour-aged them to visit the web site, check out our various activities, and to contact HiPEAC management for further informa-tion about joining the NoE.

For the academic side of the booth we pre-sented parSC, a project being developed at RWTH Aachen University in which a SystemC simulation kernel is parallelized (with the purpose of splitting the simula-tion of complex systems) in order to achieve higher simulation speeds on a multi-core host. The project itself attracted a lot of the visitors´ attention, given that SystemC is a widely used modeling lan-guage and that the project tackles one of today's most urgent issues in system level design, i.e. poor scaling of simulation speed with increasing system complexity.

With more than 60 visitors, the booth was a success. As representatives we got into close interaction with members allowing us to tighten links inside the network. We believe we managed to get many non-members interested in joining the HiPEAC community and therefore contributed to spreading HiPEAC not only across the EU but also to other European and non-Euro-pean states.

Juan Eusse & Jovana JovicRWTH Aachen University_________

Juan Eusse in the HiPEAC booth at DATE 2012.

Multicore Day is well established as the most important annual Swedish event in the multicore area.

welcome to multicore day 2012

On September 12, Swedish and international experts from industry and academia will gather in Kista, near Stockholm, to answer the questions: How should we meet the challenge of exploiting multi- and manycore processors in servers, personal computers and embedded systems? What is new in the area? Where are we heading? As in previous years, Multicore Day 2012 will feature excellent keynote speakers, including:

• Kristian Flautner, CTO ARM• Rick Hetherington, Vice President, Oracle• Jim Larus, Principal Researcher, Microsoft

ResearchYou are all welcome to Stockholm in September!

On behalf of the Swedish Multi-core Initiative.Mats Brorsson,KTH and SICS_________

For more information see www.sics.se/multicore2012

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hipeac announce / hipeac news

In the 1970s, Leon Chua claimed that memristors (resistance with memory) should exist, but it was not until 2008 that Stanley Williams at HP Labs came up with the first silicon-based implementation. Since then, physics researchers have explored alternative implementations to improve the physical properties of these devices, while computer science and electrical engineering researchers have explored their potential applications. The goal of MemCo is to bring these two communities together in order to survey the current state of the art, and to foster further interactions between the two communities.

The workshop will consist of prestigious invited talks from the physics and computing domains. For instance, Stanley Williams from HP Labs will give a presentation, as well as Bryan Jackson from IBM (chief architect of the IBM Cognitive Chip). In addition to invited talks, the workshop will include poster sessions for which sub-missions are open until July 31st. The work-shop will take place in La Villa Clythia, a resort located in the French Riviera, in the beautiful town of Frejus from November 19th to 21st. Meals and accommodation will be free of charge, paid for by our sponsors; only travel will be at your expense.

For submissions and registrations, please visit the web site: http://www.trt.thalesgroup.com/ump-cnrs-thales/memco/index.htmThe workshop is chaired by Julie Grollier, in charge of memristor research at the CNRS/Thales physics group, a lab well known for receiving a Nobel prize in physics in 2007 (Albert Fert). Several computer science and electrical engineering institutes from the HiPEAC community are co-organizing the workshop (CEA, IEF, IMS, INRIA).

Olivier TemamINRIA, France_________

Paul carPeNter takeS over HiPeac NewSletter ProofreadiNg role

Dr. Tom Crick from Cardiff Metropolitan University has served as proofreader for this HiPEAC Newsletter for over a year. Due to other commitments, Tom has recently left this role. Dr. Paul Carpenter, an Associate Researcher at the Barcelona Supercomputing Center (BSC), has volun-teered to replace Tom. The HiPEAC commu-nity thanks Tom for the reliable service he performed and welcomes Paul to the Newsletter production team!

Memristors are novel devices with huge potential: they can be used as highly efficient non-volatile memory cells, as switch cells to implement super-dense reconfigurable circuits, and even as storage elements for neuromorphic architectures.

memriStorS for comPutiNg (memco) workSHoP

Dr. P

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Dr. T

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The retargetable compilation framework for heterogeneous multicore systems developed at RWTH Aachen was demonstrated in a leading-edge technology conference and exhibition held right in the heart of Silicon Valley.

The calendar of March 2012 has been marked with an internationally renowned exhibition of the electronics design world, Design West (formerly known as ESC, Embedded Systems Conference). RWTH Aachen University (UMIC Research Centre)

has made its first trip to the event across the pond to present the research cluster in general and demonstrate key research results.Design West took place at San Jose this year (March 26-29), and is built on the

former ESC, the "go-to" industry event for 24 years. Design West 2012 gathered today's leading design engineers from every major industry segment related to advanced systems design into one unified event, across four days, including ESC,

rwtH aacHeN exHibitS maPS at deSigN weSt/multicore devcoN

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hipeac news

Android Summit and Multicore DevCon.MAPS (MPSoC Application Programming Studio), a retargetable compilation frame-work for heterogeneous multicore systems, was demonstrated to a large international, external audience at the booth. It uses both sequential C and a C language exten-sion (CPN) for describing applications in

the form of process networks, and it per-forms optimized temporal and spatial task-to-processor mapping for embedded MPSoC platforms. Supported by UMIC, MAPS has taken the step, over several years of R&D, from basic research to a tool framework that enables programming of real-life complex MPSoC platforms. Besides the booth demos, an in-depth technical presentation entitled “A Compiler Infra-structure for Heterogeneous Multicores" was also given at Multicore DevCon and was well received.The exhibition engagement at the event was a great success. The UMIC cluster was introduced to a larger crowd not only from academia but also from various industrial segments. The MAPS posters and demos including the latest multi-core tablet attracted many visitors to sit down in the booth and interactively discuss the tech-nology with the booth staff. The exhibition provided many new contacts and valuable feedback to help further grow the cluster

and MAPS technology. In addition, our UMIC mobile boomerangs and Jo-Jos became popular giveaways to many exhi-bition visitors. Weihua Sheng, RWTH Aachen University, Germany_________Design West 2012 Venue: San Jose

Convention Center.

Jeronimo Castrillon (right) talks to a booth visitor about MAPS.

Italian consortium addresses advanced silicon photonics technologies, novel network on-chip models and high-efficiency CMP architectures in tight integration

PHotoNic iNtercoNNect tecHNology for cHiP multiProceSSor arcHitectureS

The Photonica project tackles the exploita-tion of novel on-chip interconnection technologies to enable advances in net-work-on-chip (NoC) design, and in turn in the organization and management of chip-multiprocessor systems. The project was funded by the Italian Government within the FIRB "Futuro in Ricerca" program for young and talented researchers. It was one of 100 selected projects out of 4000 applications.The consortium is led by HiPEAC member Davide Bertozzi and is composed of three Italian research groups, whose cooperation began in the context of HiPEAC net-working initiatives. Giovanna Calò from Politecnico di Bari leads the group on advanced silicon photonic devices and is in charge of their design and characteriza-tion. Davide Bertozzi and Gaetano Bellanca lead the research efforts at University of Ferrara, which is in charge of back-annotat-ing technology parameters into more

abstract network architecture models and of performing design space exploration of photonic NoC topologies. Sandro Bartolini, also a HiPEAC member, leads the group at University of Siena, also in collaboration with researchers in Pisa. He aims at identi-fying the most promising CMP architec-tural organizations around a photonic interconnection, as well as defining profile-driven optimizations for application tuning onto the photonic hardware, cache hierar-chy and coherency protocol.The three groups have complementary expertise and their tight interaction can really move the boundary of on-chip inter-connect solutions to the next step.In fact, novel network architectures (from Ferrara), optimized with respect to the physical effects of the technology plat-form (from Bari), can be fed upwards in the design hierarchy (to Siena), where they can be put at work in the context of complete CMP architectures and of real-world multi-

threaded applications running in a full-system environment. As a consequence, feedback and requirements can flow back to the researchers of the technology platform, allowing to focus on the exact phenomena/device that needs to be optimized. This way, solution tuning and refinement can occur efficiently and coher-ently across all design layers.If you are interested in details about the ongoing activities and achievements and/or in evaluating possible collabora-tions on these and related topics, don't hesitate to get in touch with the main investigators.

Contact information: bartolini@dii.unisi.it; davide.bertozzi@unife.it; g.calo@deemail.poliba.itFor more details: http://sites.google.com/site/photonicaproject/home_________

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Institut “Jozef Stefan” (IJS), established in 1949 and named after one of the most distinguished physi-cists of the nineteenth century (Stefan-Boltz mann

law), is now the leading Slovenian inter-disciplinary research organization covering a broad spectrum of basic and applied research in natural sciences and technology. At present it has a research staff of around 800, including about 250 post-graduates and 350 doctors of science.

Roman Trobec received his PhD in Electrical Engineering from the University of Ljubljana in 1988, when he started his research work at IJS. He has led several courses at the University of Ljubljana, Faculty of Electrical Engineering, and Faculty of Computer and Information Science, where he currently holds the position of associate professor. He is a visiting professor in the field of HPC at the University of Salzburg, Department of Scientific Computing. He was a member of the board of directors at IJS from 2003 to 2006 and is currently the head of the Parallel and Distributed Computing Lab within the Department of Communi-cation Systems at IJS. He works on applied projects related to the design and

development of computer networks, digital information systems, bio-signal analysis, and computer simulations. His research interests cover parallel and distributed computing, cloud computing and all kind of networks. The Department of Communication Systems, which will participate in HiPEAC, is concerned mainly with the research, development and design of next genera-tion networks and wireless access systems, and the development of new parallel and distributed algorithms. Other research activities in the department include devel-opment of software tools for testing, mod-elling and simulation of communication systems, digital signal processing in medi-cine, measurements of bio-signals, etc. The department also has close scientific coop-eration with Ljubljana Clinical Centre, the biggest hospital in Slovenia, and with the incubator of innovative enterprises at the Technological park of Ljubljana. Further-more, its members coordinate several COST projects and contribute to several bilateral research initiatives in the region. Website: http://www-e6.ijs.si/~roman/

Franc Novak received BSc, MSc, and PhD degrees from the University of Ljubljana. In 1975 he joined Institut Jozef Stefan, Ljubljana, where he is currently head of the Computer Systems Department. He is also head of the Information and Communi-cation Technologies programme at Jozef Stefan International Postgraduate School and full professor at University of Maribor. He has been coordinating numerous basic research and application projects. He was the scientist in charge of three European Commission projects in the area of elec-tronic system testing and monitoring. He is author or co-author of several journal papers, mostly in the field of electronic testing and diagnosis. He has been member of the technical programme committee of several conferences including DATE, Euro-pean Test Symposium, IMSTW, and DDECS. He chaired/co-chaired sessions on electronic

test topics at EDAC-ETC 1994 and 1995, DATE 2006, and ETS 2008. He was co-chair of the 43rd International Conference MIDEM 2007 and chair of the Workshop on Electronic Testing. He is a member of the IEEE European Test Technology Technical Council. His current research interests include reconfigurable system design and test, built-in self-test and self-repairable systems. The Computer Systems Department headed by Prof. Novak is concerned primarily with design automation of computing struc-tures and systems. Within this broad area, we are concentrating particularly on meta-heuristic approaches to engineering design and logistics problems as well as system design and test. As an integral part of our research activity, members of the department have close contacts and col-laboration with scientists world-wide, through academic links and industrial con-tacts, thus enabling us to keep at the fore-front of this rapidly developing field. An important part of the research activities is related to the development of metaheuris-tic optimization methods and their appli-cations. A part of our research activities in the field of optimization methods covers also self-setting and self-adapting evolu-tionary algorithms.Website: http://csd.ijs.si/novak/novak.html

Roman Trobec and Franc Novak from Institut “Jozef Stefan”, and Stanislav Kovacic from University of Ljubljana join the HiPEAC network.

HiPeac welcomeS New memberS from leadiNg SloveNiaN academic aNd reSearcH iNStitutioNS

Roman Trobec Franc Novak

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hipeac news

The University of Ljubljana (UL), founded in 1919, is the oldest, largest Slovenian university with more than 52,000 graduate and post-graduate students, approx-imately 4,500 teaching and research staff, 3 art acade-mies and 23 faculties. The

UL Faculty of Electrical Engineering (FE) covers diverse areas of study and research, encompassing power engineering, photo-voltaics, electronics, microelectronics, nano-structures, mechatronics, embedded systems, intelli gent control and robotics, metro-logy, quality engineering, biomedical engineering, information, communication, and multimedia technologies.

Stanislav Kovacic received his PhD degree in electrical engineering in 1990 from the University of Ljubljana. He is a professor and a vice dean at the UL FE, and the head of the Machine Vision Laboratory. He lec-tures courses on computer and machine vision, embedded systems, industrial com-munications, and parallel systems. He was a visiting researcher in the GRASP Labo-ratory at the University of Pennsylvania, the Technische Fakultät der Friedrich-

Alexander-Universität in Erlangen, and at the Faculty of Electrical Engineering and Computing, University of Zagreb. His research is focused on various aspects of machine vision, embedded and distributed vision, with applications in medicine, industry and sports.UL FE will participate in HiPEAC with the Machine Vision Laboratory (MVL). The objectives of MVL are education, basic and

applied research in the field of computer vision and related areas with applications in industrial vision, sports analysis, medi-cine, visual surveillance, smart embedded visual sensors and visual sensor networks. During the last ten years the group has developed a strong collaboration with sport experts from different individual and team sport disciplines, e.g. squash, hand-ball and basketball. This collaboration has resulted in a computer vision based technology and a system prototype for tracking, analyzing, recognizing and under standing human motion in targeted sport games. New and better methods for detection, tracking, recognition, under-standing, and behavior analysis based on visual information in the application domains of sports tracking, video surveil-lance, and traffic monitoring are currently the main topics of research. Website: http://vision.fe.uni-lj.si/people/StaneK.html_________

New HiPeac member: HrvoJe mliNaric, uNiverSity of zagreb

Hrvoje Mlinaric is head of department and assistant professor at University of Zagreb - Croatia, Faculty of Electrical Engineering and Computing, Department of Control and Computer Engineering. As assistant professor, he is teaching students com-puter architectures, embedded comput-ing, multimedia architectures and systems. He was in charge of the development of Smart Dust, a hypothetical wireless network of tiny devices. When clustered together, these wireless network devices automatically create highly flexible, low-power networks with applications ranging from climate control systems to entertain-ment devices that interact with informa-tion appliances. He participated in the FP7 “European Education Connectivity Solution” project in order to develop a prototype campus card management system that will serve the unique needs and requirements of European Higher Education Institutions. As senior researcher he participated in the

“Ubiquitous Computing” project, challeng-ing a post-desktop model of human-com-puter interaction, in which information processing has been thoroughly integrated into everyday objects and activities. His current research interests are in the areas of programming platforms and tools for parallel processing, high-performance, multimedia, streaming model of compu-tation, embedded and reconfigurable systems, and programmable logic. Hrvoje Mlinaric is also a member of the Board of Directors of the “Agency for vocational education” and vice-secretary of the Department of Information Systems at the “Academia Scientiarum Tehnicarum Croatica”. He expects to participate in the HiPEAC community in areas such as embedded and reconfigurable systems, parallel processing, high-performance, multimedia, and streaming model of computation.

Contact information: Hrvoje Mlinarichrvoje.mlinaric@fer.hrhttp://www.fer.unizg.hr/hrvoje.mlinaric_________

Stanislav Kovac ic

HiPeac info 3112

in the spotlight

Project title:ALMA (ALgorithm parallelization for Multicore Architectures)Project coordinator:Prof. Jürgen Becker,Karlsruhe Institute of Technology, GermanyPartners:• Recore Systems• Intracom Telecom• Karlsruhe Institute of Technology• Université de Rennes I • University of Peloponnese• Technological Educational

Institute of Mesolonghi • Fraunhofer Institute of Optronics,

System Technologies and Image Exploitation

Project website:www.alma-project.euProject start date:1st September 2011Duration:36 months

Why must a programmer care about the hardware architecture when writing embedded applications for multi-core? The ALMA Consortium develops a tool chain that hides this complexity from the programmer and produces optimized code at the same time, thus turning the 'MUST' into a 'MAY'.

fP7 alma ProJect: caN ProgrammiNg of recoNfigurable multi-coreS be eaSier, PleaSe?

ALMA (Greek for ‘leap’, Aλμα) is an acronym for ALgorithm parallelization for Multicore Architectures. Driven by technology restrictions in chip design, the end of Moore’s law and the quest for increasing computing performance, ALMA is a funda-mental step forward in the necessary introduction of novel computing para-digms and methodologies.

“The ALMA tool-chain will implement parallelization and optimization algorithms for a whole class of multi-cores”, says Nikolaos Voros, scientific coordinator, and professor at Technological Educational Institute of Mesolonghi. “In ALMA, we will show how various embedded reconfigurable multi-cores from Karlsruhe Institute of Technology and Recore Systems can be efficiently programmed using the same tool-chain and the same application code”.

lot of progress in the development of dynamically reconfigurable hardware architectures, and we’ve noted that the software tooling to easily create lean and mean code for the hardware lag behind.” Within the ALMA project, Jürgen Becker continues “We work on corresponding hardware/software co-design and co-syn-thesis techniques. We include the hard-ware description in the software optimi zation, with the ultimate goal to use the same source code and the same tool-chain for various hardware platforms while generating efficient code. Efficient code means a faster embedded system that uses less energy. It is a field in which we can greatly contribute to low power usage in mobiles, wireless communication, cameras – in short, anything that contains a chip.”_________

The ALMA consortium brings together partners from industry and academia. The industry partners Recore Systems and Intra-com Telecom bring in expertise in recon-figurable hardware technology for multi-core systems-on-chip, software development tools and real world applications. The five academic partners contribute their out-standing expertise in reconfigurable com-puting and compilation tools development.

The ALMA project leader, Prof. Jürgen Becker from the Karlsruhe Institute of Technology adds: “Our research focuses on adaptive embedded systems. We’ve seen a

ALMA development flow overview.

The ALMA partners at the kick-off meeting in Athens on November 2011.

HiPeac info 31 13

in the spotlight

Project titlevIrtical (SW/HW extensions for virtualized heterogeneous multicore platforms)Project coordinator:Maria Engracia Gómez,Universitat Politècnica de València, SpainPartners:• Universitat Politècnica de

València • Sysgo • STMicroelectronics • Virtual Open Systems • Università di Bologna • Technological Educational

Institute of Crete • ARM Holdings • Thales GroupProject website:http://www.virtical.eu/Project start date:15 July 2011Duration:36 months

This FP7 project aims to increase functionality, reliability and security of embedded devices at sustainable cost and power consumption, by using the concept of virtualization in heterogenous multicore SoCs

fP7 virtical ProJect: imProviNg PerformaNce, Programmability, Security aNd QoS of embedded deviceS

since embedded systems require particular approaches to meet tight resource budgets and consideration of their particularities.In order to expand the virtualization concept to embedded devices, this project will deliver software/hardware extensions at different layers of the design stack (hardware, operating system, hypervisor and applications) to increase flexibility, programmability, performance, QoS, reliability, security and power saving. This unique integrated approach will allow heterogeneous embedded systems to achieve the aforementioned requirements while meeting the power and cost constraints of embedded systems.The vIrtical consortium consists of five com-panies and three universities collaborating in the extension at different levels of the stack design. The presence of major European industrial players of the embedded domain in the consortium will enable rapid commercialisation of the project outputs, enhancing European competitiveness in the embedded market. _________

Embedded devices have invaded our everyday life thanks to recent advances in wireless networks and the exponential growth of multimedia applications. These devices provide a wide variety of hardware resources, which support a protected execution environment and adaptivity to a diverse range of application functionalities. Within this context, the designer must not only cope with exponentially increasing complexity, but also invoke innovative power-aware methodology to reduce the power consumption. The vIrtical project aims to increase functionality, reliability and security of embedded devices at sustainable cost and power consumption. This is achieved by extending the virtualization concept of the general-purpose domain to the embedded domain.Virtualization is an advanced technology, widely used in the general-purpose computing domain, to provide an effective and clean way of isolating applications from hardware, in order to provide flexibility and security. Its application to embedded systems is, however, still in its infancy,

Target architecture of the vIrtical project.

HiPeac info 3114

in the spotlight

Project title:ENOSYS (IntEgrated ModelliNg and

Synthesis tOol flow for Embedded SYStems Design)

Project coordinator:Dr. Andrey Sadovykh,SOFTEAM, FrancePartners:• Softeam• Axilica• Intracom Telecom• Thales Communications &

Security• Loughborough University• University of PeloponneseProject website:http://www.enosys-project.euProject start date:January 2010Duration:36 months

Allowing the development of complex real-time embedded systems using both automatic and semi-automatic methodologies

fP7 eNoSyS ProJect: iNtegrated modelliNg aNd SyNtHeSiS tool flow for embedded SyStemS deSigN

memory optimisation and interconnect architecture, bandwidth, silicon area, oper-ating frequency and power consumption.

a global overview of tHe eNoSyS metHodologyThe ENOSYS tool set consists of the following: Softeam’s Modelio tool with support for UML/MARTE and Axilica’s FalconML behavioural synthesis tool. Jink DSE (Design Space Exploration) performs design exploration on the system hard-ware/software partitioning by reallocating the initial MARTE UML allocations in the reference model and evaluating the results as the design proceeds automatically through the ENOSYS flow. Additionally, extra exploration paths are available by customising Loughborough University's own

LE1 multi-core processor, choosing different options for the switches in various design automation tools and enabling specific source code optimisations using ACOT, which in turn provides optimisations to address source code optimisation as a transformation of source code (modeled as action language of UML software com-ponents) into a functionally equivalent program.The project includes two end users: Thales and Intracom. Thales' case study consists of a hardware/software implementation of a JPEG2000 encoder in a single SoC, while Intracom selected the transmit chain of a WiMAX 2 (IEEE 802.16m) Base Station PHY layer in both hardware andsoftware, on a field-programmable SoC._________

Design intent is captured precisely in an object-oriented language based on the UML/MARTE modelling language profile, combined with C/C++ to describe system behaviour, and with support for existing hardware/software intellectual property (IP) blocks in a number of formats. The methodology provides code generation for a programmable SoC platform, including the SoC interconnect backbone and multi-level wrappers, which results in behavioural synthesis of the non-CPU-mapped UML objects into hardwired, streaming engines. The tool chain (fully automatic mode) or the designer (semi-automatic mode) can quickly analyze the performance of candidate architectures and determine which will be the most effective, according to the given optimization criteria such as embedded

HiPeac info 31 15

in the spotlight

Project titleCARP (Correct and efficient AcceleratoR Programming)Project coordinator:Dr. Alastair Donaldson,Imperial College London, UKPartners:• Imperial College London • ARM• Realeyes• RWTH Aachen University• Monoidics• Twente University• ENS• RightwareProject website:http://www.carpproject.eu/Project start date:1st December 2011Duration:36 months

The CARP Consortium investigates programming models for accelerated systems, automatic code generation, cost analysis for energy efficiency, and advanced formal verification techniques.

fP7 carP ProJect: euroPeaN reSearcHerS to tackle accelerator ProgrammiNg

and energy consumption challenges of accelerated computing systems, in close collaboration with hardware vendors and domain experts”, said Dr Albert Cohen, senior research scientist at INRIA.“Analysing accelerator software both qualitatively and quantitatively, as well as accurately modelling accelerator hardware using stochastic techniques, is key to optimising energy efficiency of computing systems, ranging from embedded devices to supercomputer installations”, said Prof Joost-Pieter Katoen, from RWTH Aachen University. “The CARP project opens up a whole new application domain for my research, as verifying low-level software for massively parallel accelerators is the ideal test-bed for scaling up my verification techniques for concurrent software,” said Dr Marieke Huisman, associate professor at University of Twente.“Tracking facial features using highly computationally intensive algorithms at real-time often requires specialising soft-ware to each platform of interest. We hope to considerably reduce our software development and maintenance costs by minimising the need to write platform-specific code and making it easier to port our software to future platforms,” said Dr Elnar Hajiyev, technology director at Realeyes._________

“I view accelerator programming as a challenge that must be tackled both from the top-down, via programming frame-works allowing software developers to synthesise efficient platform-specific code from a platform-neutral algorithm repre-sentation, and from the bottom-up, via effective tools for debugging and verifying low-level code,” said Dr Alastair Donaldson, project coordinator and lecturer at Imperial College London.“Effective programming tools are essential to help broaden the adoption of hetero-geneous systems, such as systems-on-chip accelerated by ARM® Mali™ graphics processing units (GPUs). We aim to provide software developers with a variety of programming technologies that range from industry standards, such as OpenCL™, to domain-specific frameworks.The emphasis is on efficiency, performance portability and productivity,” said Dr Anton Lokhmotov, staff engineer, ARM.“Parallel programming is becoming increa singly synonymous with accelerator programming. The CARP project is a unique opportunity for programming tools researchers to contribute practical solutions to the productivity, performance,

December 2011 saw the kick-off of an ambitious research project called “CARP: Correct and Efficient Accelerator Program-ming”, which aims to boost the program-mability of accelerator hardware, such as graphics processing units (GPUs), by inno-vating in programming language design and implementation, as well as formal verification techniques. Funded by the European Commission’s Seventh Frame-work Programme (FP7), the consortium, which consists of four industrial partners (ARM and three SMEs) and four academic partners, seeks to provide a unified flow for developing correct and efficient accelerator software, thus increasing reliability and energy efficiency of computing systems.

HiPeac info 3116

in the spotlight

Project title:MEDIAN: (ManufacturablE and Dependable multIcore Architectures at Nanoscale)Chair of the action:Dr. Marco Ottavi Università degli Studi di Roma "Tor Vergata" (Italy)Partners: • The COST action involves 45

participants coming from 20 different countries.

Project website:http://www.median-project.euProject start date:1st December 2011Duration:48 months

This COST action is aimed at creating a European network of competence bringing together experts on all dependability aspects of future digital systems development, promoting collaboration between industry and research.

mediaN ProJect: maNufacturable aNd dePeNdable multicore arcHitectureS at NaNoScale

The motivation for this project stems from the reckoning that both technology and architectures are today at a turning point. At the technological level many ideas are being proposed to extend CMOS techno-logy as well as to find alternatives such as CNTFET, QCA, memristors, etc., and at the architectural level, the spin towards higher

and major underlying challenges between all levels of abstraction of gigascale systems (i.e., from technology to system level). Moreover a strong horizontal integration of WG1 through WG3 with the application areas will foster innovation driven by key applications.MEDIAN operates by supporting the establishment of scientific collaboration between its members. The main instru-ments provided are:• Short Term Scientific Missions: exchange

missions between participants, targeted especially to young researchers. The goal of MEDIAN is to award at least six STMSs per year

• Workshops: workshops are open to the entire scientific community and have the purpose of fostering research and collaboration on the topics touched by MEDIAN. The first MEDIAN Workshop will be on June 1st in Annecy (France).

• Training Schools: aimed at widening the knowledge of the Action activities. Those attending a Training School are typically – but not exclusively – young researchers from across Europe. The first training school is planned for Summer 2013.

Participation in MEDIAN is open through-out the duration of the project. Interested researchers and perspective participants can find more and updated information about the Action at our website: http://www.median-project.eu_________

frequencies and aggressive dynamic instruction scheduling is being replaced by the trend of including many simpler cores on a single die. These paradigm shifts will require a rethinking of design, manu facturing, testing, and validation of reliable next-generation systems. Manu-factura bility and dependability issues will be resolved efficiently only with a cross-layer approach that takes into account technology, circuit and architectural aspects, but also application scenarios. The project's final goal is to contribute to the constant advances in manufacturing yield and on field reliability by supporting fruitful collaboration and exchange of knowledge between the design and manu-facturing side and three different application scenarios: space, medical, and trans portation.MEDIAN is composed of six working groups.• WG1: Methodologies and techniques for

manufacturing reliable nanoscale devices

• WG2: System level design, on-line testing/fault tolerance

• WG3: Verification and Validation/Debug Methodologies

• WG4: Fault tolerance for space applications

• WG5: Fault tolerance for transportation systems

• WG6: Fault tolerance for medical devicesThe goal of MEDIAN is to create a strong interaction between all the areas, having a vertical interaction between WG1 through WG3 to have cross-fertilization of ideas

WorkGroup Connections.The MEDIAN Vision.

HiPeac info 31 17

in the spotlight

A Global overview of the PRESTO methodology.

Project titlePRESTO (ImProvements of industrial Real Time Embedded SysTems devel0pment process)Project coordinator:TELETEL, Greece Partners:• TELETEL S.A. • THALES Communications France • Rapita Systems Ltd. • VTT • Softeam • THALES Italy • MetaCase • INRIA • University of L’Aquila • MILTECH HELLAS S.A • PragmaDev • Prismtech • Sarokal Solutions Project website:http://www.presto-embedded.eu/Project start date:1st April 2011Duration:36 months

This ARTEMIS project aims at improving test-based embedded systems development and validation, while considering the constraints of industrial development processes

PreSto ProJect: foSteriNg aNalySiS oN iNduStrial embedded SyStemS develoPmeNt ProceSS

SCA, EAST-ADL, SDL and other potential standards, by formal modeling of func-tional/non functional properties to be used for timing analysis tools, and by car-rying out test trace generation and their exploitation.Similarly, improvements on hardware design flow include: hardware modeling using MARTE and its extensions such as those related to power conservation tech-niques, and comparison between initial timing analysis results and results obtained during simulation or execution of the application on the platform, at dif-ferent levels of granularity.Finally improvements on the analysis capabilities include: development of a fast platform prototyping tool based on MARTE or other existing hardware/software mod-eling languages, use of test traces as an entry point for performance analysis tools, and comparison of the results from simu-lation with execution on the real platform, to identify the dominant parameters of suitable platform modeling and enable design space exploration aspects. _________

benefit from these new capabilities, and to have the capability at early stages of the design to evaluate the impact of the use of these functionalities, in term of timings.

PRESTO addresses the improvement of test-based embedded systems develop-ment and validation, while considering the constraints of industrial development processes. The global idea of the PRESTO project is to provide a tool set, using inputs from the current Industrial Design pro-cesses, in particular: system requirements allocated to the hardware/software and execution traces from the software integration. This project is based on the integration of: (a) test traces exploitation (generated by test execution in the software integration phase induced by the industrial develop-ment process, to validate the requirements of the system) along with (b) platform models and (c) design space exploration techniques.The project aims to improve upon the soft-ware design flow: by carrying out software modeling using UML MARTE profile, fUML,

Evolutions in the industrial process devel-opments of real time and embedded systems have to face new challenges in their design process. By nature, embedded systems are constrained by the limited amount of resources available (Time, Power, Size). These constraints need to be taken into account in the engineering process. Allocations of application func-tions on execution platforms and the related consequences on resource usage need to be carefully addressed, as early as possible, during the design stages. During embedded software design the capability to tune hardware platform parameters must be provided. Embedded software designs have to provide the capability to tune new hardware component parame-ters. Software developments have to

HiPeac info 3118

PhD news

This work approaches the topic of com-piler optimisations directed to network applications. It shows an automated approach that can identify domain-spe-cific performance bottlenecks through workload characterisations based on deci-sion trees. For network infrastructure applications this shows that data organi-sation is the key performance bottleneck. We therefore propose and evaluate spe-cialised data transformations using real-world data sets obtaining speedups of up

to 2.62. Additionally, to address different network traffic scenarios, an adaptive software caching scheme is introduced, which in combination with a static analy-sis tool we developed, achieves optimal performance in all situations._________

By Damon FenacciUniversity of Edinburgh, ScotlandAdvisor: Prof. Björn Franke June 2012

By Juan Antonio Villar OrtizUniversidad de Castilla-La Mancha, SpainAdvisors: Prof. Dr. Francisco J. Alfaro-Cortés y Prof. Dr. José L. Sánchez-GarcíaApril 2012

comPiler-driveN data layout traNSformatioNS for Network aPPlicatioNS

HigH-radix combiNed SwitcHeS: formalizatioN aNd coNfiguratioN metHodology

The maximum radix of a single-chip switch is mainly determined by considering physical parameters such as the integra-tion scale and pin-count. One way to build high-radix switches (high-radix combined switches) consists in combining several low-radix single-chip switches. In this thesis, we propose a methodology for con-figuring the combined switches, and apply it to a particular case. By means of this methodology, we resolve the key design

aspects of combined switches: the most appropriate correspondence between external and internal ports, and the required bandwidth among the internal switches. More information is available at http://juanvillar.blogspot.com. _________

By Jesus Escudero SahuquilloUniversidad de Castilla-La Mancha, SpainAdvisors: Prof. Pedro Javier García and Prof. Francisco J. Quiles December 2011

towardS efficieNt aNd feaSible coNgeStioN maNagemeNt tecHNiQueS for HigH-PerformaNce iNtercoNNectioN NetworkS uSiNg diStributed routiNg

This thesis addresses the problem of con-gestion management (CM) in interconnec-tion networks with distributed routing, where none of the proposed CM tech-niques achieve complete efficiency and scalability. Our approach is to prevent Head-of-Line (HoL) blocking derived from congestion situations. In that sense we present several techniques, most of them based on dynamically isolating flows of packets contributing to congestion. We also combine them with injection-throt-

tling mechanisms (i.e. InfiniBand CM policy). In addition, we propose other tech-niques which offer, if extreme simplicity is mandatory, the best HoL-blocking preven-tion achievable with the minimum complexity._________

HiPeac info 31 19

PhD news

explo ration techniques for RASDF are pre-sented. In order to guarantee performance under dynamic inputs, a game-theoretic approach to controller synthesis is developed._________

By Yang YangEindhoven University of Technology, The NetherlandsAdvisors: Prof.Dr.Ir T. Basten, Prof.Dr. H. Corporaal, Dr.Ir. M.C.W. Geilen July 2012

exPloriNg reSource/PerformaNce trade-offS for StreamiNg aPPlicatioNS oN embedded multiProceSSorS

In this thesis, we introduce a resource-aware extension to the Synchronous Dataflow (SDF) model of computation, i.e., Resource-Aware Synchronous Dataflow (RASDF). RASDF can be used to explore resource/per-formance trade-offs for streaming applica-tions on embedded multiprocessors. Efficient trade-off analysis techniques, both in the time-domain and in the SDF-iteration-domain, are developed with support for resource sharing. Further, automatic bottleneck-driven design-space

welcome to tHe 8tH iNterNatioNal Summer ScHool oN advaNced comPuter arcHitecture aNd comPilatioN for HigH-PerformaNce aNd embedded SyStemS

Participants in the 2011 ACACES Summer School.

upcoming events

the 22nd international conference on field Programmable logic and applications (fPl 2012) 29-31 August, 2012, Oslo, Norway. http://www.fpl2012.org/

the 18th international european conference on Parallel and distributed computing (euro-Par 2011) 27-31 August, 2012, Rhodes Island, Greece. http://europar2012.cti.gr/

the 21st international conference on Parallel architectures and compilation techniques (Pact)19-23 September, 2012, Minneapolis, Minnesota, USA. http://www.pactconf.org/

the 30th ieee international conference on computer design (iccd 2012)30 September - 3 October, 2012 Montreal, Quebec, Canada. http://www.iccd-conf.com/

the 10th ieee/ifiP international conference on embedded and ubiquitous computing (euc 2012)3-5 October, 2012, Paphos, Cyprus. http://www.euc2012.cs.ucy.ac.cy/

international Symposium on System-on-chip (Soc 2012)11-12 October, 2012, Tampere, Finland. http://soc.cs.tut.fi/

conference on design and architectures for Signal and image Processing (daSiP 2012) 23-25 October, 2012, Karlsruhe, Germany. http://www.ecsi.org/dasip/

the 45th annual ieee/acm international Symposium on microarchitecture (micro-45)1-5 December, 2012, Vancouver, Canada. http://www.microsymposia.org/micro45/

the 16th design, automation and test in europe conference (date 2013)18-22 March, 2013, Grenoble, France. http://www.date-conference.com/

the international conference on compiler construction (cc 2013) 16-24 March, 2013, Rome, Italy. http://www.etaps.org/2013/cc13

tHe 8tH iNterNatioNal coNfereNce oN HigH PerformaNce aNd embedded arcHitectureS aNd comPilerS (HiPeac 2013),

21-23 JaNuary 2013, berliN, germaNy

info 31

hipeac info is a quarterly newsletter published by the hipeac network of excellence, funded by the 7th european framework programme (fp7) under contract no. ist-217068.website: http://www.hipeac.net.subscriptions: http://www.hipeac.net/newsletter

contributions If you are a HiPEAC member and would like to contribute to future HiPEAC newsletters, please visit http://www.hipeac.net/hipeacinfo

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