68 2000 IEEE International SO1 Conference, Oct. 2000

High Performance 0.1pm Partially Depleted SO1 CMOSFET W.K. Yeh*, Chiutsung Huang, T. F. Chen, S. M. Hsu, Jiann Liu, C. 13. Liri and F, T. Lioti

United Microelectronics Corp., Advance Device Department, Technology & Process Development Division, Science-Based Industrial Park, Hsin-Chu, Taiwan, R.O.C.

* Electrical Engineering Department, National University o f Kaohsiung, Kaohsiung, Taiwan, R.O.C.

I . Introduction Partially Depleted SO1 MOSFET (PD-SOI) has been found to

be an attractive device due to the advantages such as full dielectric isolation and reduced junction capacitarice which over bulk-Si device [ I ,2]. However, floating body effect happencd on PD-SO1 device resulting in threshold voltage reduction and noise overshoot [3]. Body contact structures has been proposed to improve the floating body effect [4]. This paper describe high performance 0. l p m generation SO1 technology, the SO1 MOSFE'I' with body contact structure (BC-SOI) was used to investigate the device characteristics as well as thermal effect in comparison with floating body SO1 MOSFET (FB-SOI) which without body contact. The dynamic-threshold voltage SO1 MOSFET (DTMOS) was also be investigated. 2. Experinients

PD-SO1 was fabricated on wafers with 150nm thick active layer and a 400nm thick buried oxide film with 0 . Ipm process. Comparison with conventional bulk-Si device process, modified shallow trench isolation (STI) and CoSi, technologies are used for SOI device fabrication. The structure of the S U M circuit on this PD-SO1 substrate is illustrated in Fig. I . After STI followed by channel implantation, dual gate CMOSFETs were fabricated with gate oxide grown by rapid thermal oxidation. Advanced lithography technology is adopted to define O.lpm poly-Si gate. Source/drain extension implantation was employed prior to SiN spacer formation. The n; and p' junctions were formed by arsenic and boron implantation in respectively. After CoSi, salicidation, full backend metallization was fulfilled. Figure 2 shows a cross- sectional SEM micrograph of 0. I pm SO1 MOSFET. It is apparent that good CoSi, was formed on poly-Si gate and S/D regions. In this work, the T-gate structure was used for BC-SO1 structure, as shown in Fig. 3 . For DTMOS which body is tied to the gate, the forward body to source bias, threshold voltage is lowered with the increase of gate bias as a result of body effect. Thus, a dynamic change of threshold voltage is achieved without the application of additional control circuitry [5]. In this work, FB-SOI, BC-Sol, and DTiMOS devices are investigated simultaneously. 3. Results (A) FB-SO1 versus BC-SO1

Figure 4 illustrates the ID-\', characteristics for SO1 MOSFET with and without body contact. For 0 . I p n FB-SOI, ID,sAT of jSOpAIpm and 23OpA/pm for n-FET and p-FET are achieved with loFF of 2nA/pm and 0.0 I nA/uni at V,, = I .2V in respectively. I t is apparent that the floating body effect due to impact ionization was happened especially at higher drain voltage (VDU 31 0.8V) and significant reduced as V,drops. For BC-Sol, the charge can be released through the body contact tcrminal; thus, the floating body effcct can be suppressed. However, in comparison with FB-SO], driving current (ION) and off statc leakage (IoFF) of SC-SO1 was lowcrcd dtic to higher thrcshold voltagc, as shown in Fig. 5. Figure 6 and 7 show the I O N versus Ior1: curve for SOI-MOSFETswith and without body contact structtirc. 'l'tlerc is no apparent difference on DC pcrforninncc with siiiiilar 19N-I0,i. curvc between FB-SO1 and

0-7803-6389-2/00$10.00 02000 IEEE. -~ -~

BC-SOI, but lorp scattering due to floating body effect was happened on FB-SO!. In cornparison with bulk-Si device, better AC performance can be obtained with SO1 device due to lower junction capacitance, as shown in Fig. 8. With same ring oscillator test stlucture (F.O=I, 151 stages), it is about 16-21% gate delay can be improved with devices on SO1 substrate.

Since I,,, of SO1 MOSFET will be increased as the chip temperature increases [GI. I,,, as a function of chip temperature was also investigated, as shown in Fig. 9. The l,,,was increased as the chip temperature increases for both BC-SO1 and FB-SO1 with similar curve at lower V,,, then lor, overshoot happen on FB-SO1 as V,, > 1.2V. There is no any dependence of I,,, overshoot take places on chip temperatures; thus, the floating body effect due to impact ionization was apparent at higher V,,. As similar to IBM's report [7], the temperature dependence on Io,, for FB-SO1 is less sensitive to chip temperature than that for bulk-Si and BC-SOI, as shown in Fig. 10. At room temperature, i t is apparent that larger I,,, caused by floating body effect happened on FB-SOI. As chip temperature increases (>70"C), the lo,, of bulk-Si increase apparently and overtake that of FB-SOL Thus, i t is assembly that the FB-SO1 circuits without body contact is more appropriate to be designed for the applications operating at higher temperatures. By the way, the temperature dependence on io,, for SO1 devices was enhanced with body contact structure (BC-Sol); thus, there is nu apparent difference on I,,, between BC-SO1 and FB-SO1 at higher temperatures. (8) DTMOS versus FB-SO1

Figure 1 1 illusti.ates the I,-V, characteristics for DTMOS and FB-SUI. In comparison with FB-SOI, 30-40% driving capability can be increased by D r M U S with same I,,, due to sharper subthreshold slope (from 76 -> 63 inV/dec.), as shown iii Fig. 12. Figure 13 and Table I compare these three types of SO1 MOSFET, it is apparent that rcverse short channel effect (RSCE) of BC-SO1 was lar'ge (-0.2V) and can be improved with DTMOS (XO. IV). For FB-SO1 device, VT-sKr was reduced due to floating body effect; thus, less RSCE can be obtained. For O.lpm DTMOS, I,,,,, of 800pNpm and 320pNpm for n-FET and p-FET are achieved with I,,, ofO.SnA/pni and IpNnm at V,, = l .2V respectively. With the same backend metallization technology, 35% - 40% gate delay can be improved with DTMOS; thus, DTMOS is very suitable to be designed for low voltagc applications. 4. Conc lus ion

This paper describe high performance 0.1 prn SO1 technology, the BC-SO1 was used to investigate the device characteristics as well as thermal effect in comparison with FB-SOI. There is no apparent differcnce on I,,, behveen BC-SO1 and FB-SO1 at higher temperatures. With body tie structurc, DTMOS can offer very good device performance and suitable to be designed for lower voltage applications. References [I1 F A r r a d r r r g h i L . r , i i l . I l ~ D h l , (119l),p515 121 S Ma& cc. ! , I , Syinp VLSl .Tech Dig.. (10001. p 154 131 Y -C TIEW c!. i d , Symp V I W Trch O i l .p 90, I901 ( 4 ) C H u u n g n d . l ' r o t c rd iogunSo l rdS i~ i c~~~ l In l r y .nc i iC i i cu , i . p l l ? . I W X

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2000 IEEE International SO1 Conference, Oct. 2000

Fig. I Cross Sectiori SEM of SRAM Fig. 2. Cross Section Fig. 3 . ?'-Gate on Sol. SEM of 0, lpm SO1 Structurc for Fig. 4. l,,-VD characteristic of SO1

MOSFEI' with and without body contact. MOSFET.

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Fig. 8 . Gafc delay vcrsiis the applied voltage for bulk and SO1 devices.

Fig. 6 . loN-Iom characteristics of nFET on SO1 with and without body contact.

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Fig. 9. nFET off leakage as function of V, with various chip temperature.

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Fig. 12. lD-VG charactcristic of SO1 MOSFE?' for DTMOS and f:B-SOI deviccs.

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Fig. 7. IoN-Io, characteristics of pFEl on SO1 with arid without body contact.

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Fig. IO. nFET off leakage versus chip tenipenture fur various MOSFETs.

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Fig. 13. lhrcshold roll-off for SO1 devices.