High Performance NMOS Active Zener and Rectifier Diodes

S. Finco#, A. P. Casimiro+, P. M. Santos+, P. Tavares # and M. I. Castro Simas+ #Instituto Tecnológico para a Informática – ITI, Rodovia D. Pedro I, km 143,6 - CEP 13089-500 SP, Brazil

Tel.: 55-19-37466055, Fax: 55-19-37466051, E-mail: saulo.finco@iti.br +Instituto de Telecomunicações IT - Instituto Superior Técnico – IST – 1049-001 Lisboa Codex Portugal

Tel.: 351-21-8418388/89, Fax: 351-21-8418472, E-mail: misimas@lx.it.pt

Abstract- NMOS based circuits to emulate diodes and Zener diodes are proposed, following the tendency to develop fully CMOS compatible solutions towards over-voltage protection and rectifier circuits, which are highly desirable to implement low cost smart power circuits and Microsystems for a wide range of applications. This work will present extensive charac-terisation, through experiments, on prototypes fabricated using three different standard, low cost, CMOS processes. Compara-tive analysis of the results supports prospects of implementing the basic blocks required by Power Integrated Circuits (PICs) and by Intelligent Power Devices, resorting only to NMOS switching cells.

I. INTRODUCTION

Recent advances in automobile and aerospace industries, medical and telecommunications portable equipment, among others, are shaping research on power integrated circuits, and on smart power in particular. Several approaches [1] are try-ing to circumvent sophistication towards the reduction of cost of these monolithic solutions, resorting to low cost technolo-gies.

A successful technological solution will not consist of merging power and high-density low voltage circuits exploit-ing the combination of two technological processes, leading to a higher mask count and price or to a compromise on the device properties when compared to the expectable perform-ance of separate processes. To take full advantage of initial investments, new processes of advanced technologies should be developed taking into account efficient high voltage de-vices together with high performance low voltage circuitries implementation, making use of new dedicated steps in order to avoid electro-migration and current distribution problems.

Power management innovation is leading products and technologies to converge to a common technology base [1], [2]. On the other hand, Communications, Computers, Con-sumer electronics and Cars are shaping progress and econ-omy patterns every aspect of daily life. Therefore, power management is becoming an important issue for designers of

The work reported here was developed jointly under a scientific cooperation action celebrated between CNPq – Brazil and ICCTI – Portugal and receives a grant from FEDER, under the project PRAXIS XXI/2/2.1/TIT/1655/95.

these products and so do power devices, which drive the four Cs. Design compromises regarding cost, size, thermal man-agement, noise and battery life are unavoidable. Thus, Power Integrated Circuits (PICs), namely smart power circuits and intelligent devices are in order as efficient solutions.

A tendency for technology migration of power devices into deeper-submicron fabrication processes is evident. Applying submicron technologies to power management semiconduc-tors lead to: improved on-resistance; improved oxide topog-raphies and metal step coverage; efficient current spreaders, that improve current uniformity; improved propagation delay and switching losses. Even using large areas, submicron technologies are still cost effective one. Trench structures illustrate the continued benefits of scaling to smaller physical dimensions.

Other approaches are attaining reliable and low cost solu-tions, by customizing new submicron processes in order to take full advantage of already matured standard CMOS tech-nologies [3], [4], [5]. Thus, Power Integrated Circuits and intelligent power devices have to be designed CMOS fully compatible.

In the following, fully CMOS compatible and High Volt-age NMOS (HVNMOS) based active “Zener” and “Rectifier” circuits are characterized both by simulation and by experi-ments on prototypes implemented using three different stan-dard, low cost, CMOS processes. High performance is achieved using proposed HVNMOS based emulation circuits. Accordingly, a unique and versatile HVNMOS elementary cell, aimed at implementing the referred functionality, will also be characterized below.

The same methodology was extended to all power control basic blocks required by PICs [6], to enable switching, con-trol, drive, protection and sensing functions implementation, dispensing with all the usually required devices (HVPMOS, TJBs, Zener and rectifier diodes), except for a floating HVNMOS. Design methodologies for these power control basic blocks, such as: NMOS level shifter, NMOS clipper, NMOS based charge-pump, NMOS based bootstrap and NMOS current generators, were discussed elsewhere [7], [8].

6580-7803-7116-X/01/$10.00 (C) 2001 IEEE

II. HVNMOS ELEMENTARY CELL

The elementary switching cell is a high-side HVNMOS transistor, capable of implementing required power conver-sion or amplification topologies, by means of appropriate associations of elementary transistors, either in a bridge con-figuration, or of two active devices in a half bridge configura-tion, or one active device plus a free-wheeling diode. The optimized HVNMOS elementary cell uses a Drain engineer-ing technique - Gate-Shift [9]. The GS-NMOS was developed and fabricated using two different processes of a low cost, standard CMOS, N-well technology. The characterization and performance discussion considering their counterparts was presented in a previous report [10].

Experimental results on HVNMOS prototypes showed that this approach is very effective on a wide range of low or me-dium power applications. Fig. 1 shows the cross section of the elementary switching cell, the implementation of which uses the lightly doped source and drain (LDSD or symmetric LDD) NMOS transistor concept [11] for obtaining a high-side transistor. When a low-side transistor is required, the Source structure can be the n+ implant of a conventional NMOS (asymmetric LDD), which will reduce device ON-resistance and Source side capacitances. GS-LDD devices fabricated using the Gate-Shift drain engineering technique, in both 2µm and 0.7µm standard CMOS technologies, showed very promising results, especially in terms of device blocking capabilities, while maintaining reasonable values for specific ON-resistance and VTH. Measured devices BVs were found in the range 45-67Volt, with specific ON-resistances below 15mΩcm2, for the 2µm technology, and BVs in the range 33-50Volt, with specific ON-resistances in the 2-5mΩcm2 range were found for the submicron technology, depending especially on LGS and effective channel lengths. This represents a significant improvement in devices overall performance when compared with both the classical LDD technique (LGS = 0 ) and, obviously, the standard 5Volt NMOS.

n+

N-well

n+

N-well

P-sub

D

G

SFOX

active areamask layer

LdrawnN-well

mask layerLGS

Fig. 1. Cross-section of the LDSD-NMOS, with representation of Gate-Shift

technique.

The LDSD-NMOS structural symmetry provides appropri-ate layout versatility. The elementary cell also intrinsically presents immunity to latch-up. Furthermore, it is self-isolated; thus, multiple power cells, as low-side and high-side drives, can be built in the same substrate. Although body ef-

fect and high gate capacitive effect are present in the elemen-tary cell, requiring special care in the design, experimental results proved the viability of the proposed elementary cell. The same concept can be extended to other types of isolated NMOS high voltage devices, such as LDMOS transistors, which will be considered later in this approach.

III. PICS POWER CONTROL BLOCKS

Power Control circuitries involve multiple switching cells, similar to that described above, and their drivers. Power de-vices with low ON-resistances and low switching losses call for efficient drive circuits, for both high-side and low-side switches. Usually, switch drivers require specific blocks [12], such as: high voltage level shifters, clippers, clampers, charge-pumps and capacitive bootstraps. These circuits are usually implemented using high voltage NMOS transistors, PMOS transistors, rectifier and Zener diodes.

In the approach presented in this paper, the main blocks re-ferred above are designed resorting only to NMOS transistors [7]. An important advantage of this LDSD-NMOS based elementary power switching cell is that it is highly suitable for implementation of semicustom arrays layouts, aimed at Smart Power ICs. These arrays, disposed in a matrix ar-rangement, can be fabricated in a standard, low cost, CMOS technology [7], [8], following the market tendency for CMOS.

PICs power control circuitry main blocks implementation resorting exclusively to a floating HVNMOS paves the way to low cost PICs and Microsystems using standard and easily accessible CMOS processes. Furthermore, pattern simplicity achieved for HVNMOS based PICs power control blocks enables mask configuration of pre-processed power arrays, following the market requirements towards fast prototyping [8]. Thus, reliability improvement together with qualification cycle time reduction can be attained.

IV. NMOS BASED RECTIFYING, LIMITING, CLAMPING AND REGULATING CIRCUITS

Rectifier and Zener diodes are required to implement recti-fying, limiting, clamping and regulating functions in PICs, namely in many Smart Power applications, such as over-voltage detection and/or protection and voltage regulation.

This approach presents specific NMOS based topologies to emulate diodes behavior, enabling unidirectional current for a diode under forward bias (Fig. 2 a)) or bi-directional current for a Zener diode (Fig. 2 b)) or an association of diodes, as shown in Fig. 2 c). These emulation circuits also eliminate diode typical problems, originated by the n+ and p+ diffu-sions available in the technology. Moreover, their characteris-tics are not affected either by process variations or layout geometry.

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These active circuits make use of two control blocks (Fig. 3 a)) to drive NMOS transistors: a low side, low volt-age, standard digital-analog control circuit; and an output LV/HV amplifier circuit designed to provide emulation of circuit voltages and currents. Fig. 3 b) shows a simplified representation of the control block.

a) b) c)

Fig. 2. Characteristics I(V) for: (a) a rectifier diode; (b) a Zener diode; and (c) a back-to-back association of a rectifier and a Zener diodes.

Fig. 3. Block diagram of the control circuit: (a) the standard digital-analog

control circuit and the output LV/HV amplifier circuit; and (b) simplified representation of the control circuit.

These diode emulation circuits resort to NMOS FET in-trinsic junctions. Therefore, reliable design should take into account bias conditions and technology physical limitations, such as current and voltage maximum rates, in order to avoid behavior degradation by excessive power dissipation. Fur-thermore, resistive and capacitive parasitic effects must also be appropriately characterized and modeled, for consideration in transient analysis and operation frequency range definition.

A. Diode Emulation

Many applications call for a simple rectifier diode, the be-havior of which is shown in Fig. 2 a). This topology dis-penses with any LV control. Instead, a Gate-Drain short-circuit is used for LDSD NMOS based circuits (Fig. 4 a)), and if a LDMOS is at hand to implement the ele-mentary cell, a Gate-Source short-circuit should be used in the case of LDMOS based circuits (Fig. 4 b)).

Fig. 4. a) LDSD NMOS based “diode” circuit; b) LDMOS based “diode” circuit

B. “Zener” Circuits

Fig. 5 shows an NMOS “Zener” circuit, composed of two LDSD n-channel MOSFETs and associated control circuitry,

that effectively emulates the behavior of a floating Zener di-ode (Fig. 2 b)).

Fig. 5. LDSD NMOS based “Zener” circuit

However, if the basic cell available is a LDMOS, the “Zener” circuit is the one shown in Fig. 6 and its control cir-cuit provides specific signals according to structure (e) re-quirements.

Fig. 6. LDMOS based “Zener” circuit

The control circuit is programmable through a reference signal at input In, acting in order to define the desired Zener voltage at Drain-Source terminals, vDS=VZ, by forcing ap-propriate vGS, thus controlling NMOS RON. When vDS is be-low VZ, a current flows in the “Zener” circuit for control bias and the control acts to increase vAK, (Figs. 5 and 6) in order to maintain a constant VZ at A-K terminals. When vDS increases, tending to values above VZ, the control acts to decrease NMOS RON, in order to maintain a constant VZ. The Zener diode behavior, I(V), shown in Fig. 2 b), is emulated at An-ode (A) and Cathode (K) terminals by these “Zener” circuits (Figs. 5 and 6), since NMOS safe operating areas are pre-served.

C. “Rectifier” Circuits

The Rectifier-Zener diodes back-to-back association behavior, shown in Fig. 2 c), can be emulated by a LDSD NMOS based circuit presented in Fig. 7 a) or a LDMOS based circuit (Fig. 7 b)). Both “Rectifier” circuits use an am-plifier G at the control circuit, the function of which is to provide the lowest possible NMOS RON, through an adequate Gate-Source voltage controlled by Anode-Cathode (A’-K’) voltage. Voltages applied to Gate, Source and Drain terminals of an NMOS structure ((e) in Fig. 7), configured as a diode, should be higher than ground voltage ((t) in Fig. 7). When forward biased, VA’ > VK’, the diode presents an exponential behavior with a threshold voltage VF. When reverse biased,

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the “diode” turns OFF and the current is neglectable until either breakdown or Zener voltages is attained.

Fig. 7. a) LDSD NMOS based “rectifier” circuit; b) LDMOS based “recti-

fier” circuit

A thorough theoretical analysis of these circuits, including stability, was carried out and presented elsewhere [7].

V. NMOS CIRCUITS PERFORMANCE ANALYSIS

In the following, performance analysis is carried out and trade-offs are discussed.

Simulation and experimental results obtained on proto-types, fabricated in three different CMOS processes are pre-sented. Experimental results were obtained for prototypes fabricated using two different digital, standard CMOS proc-esses (2µm [13] and .7µm [14]) and a 2µm High Voltage (HV) dedicated CMOS technology [15]. Experimental results obtained using the three referred processes are similar. The results presented in this paper were obtained with LDSD NMOS (RON=15.2mΩ.cm2) and LDMOS (RON=9mΩ.cm2) transistors fabricated in the HV dedicated process. Simulation results were obtained using Accusim, from Mentor Graphics with parameters provided by the foundries.

The test circuit, selected as an example to compare NMOS based circuits performance with that of discrete diodes, is presented in Fig. 8 and comprises three device aggregates. Each group includes three different functions: a rectifier di-ode, a Zener diode and a back-to-back association of Zener-rectifier diodes. The group at the left (1) is based on discrete devices, the group in the middle (2) uses LDSD based circuits and the group at the right (3) is implemented resorting to LDMOS based circuits.

HV is a high voltage (20-50 Volt amplitude) 10-100 kHz triangular-shaped signal. The voltage VK is applied to diodes Cathodes and to NMOS based circuits equivalent Cathodes.

The rectifier diode 1N4148 and the Zener diode 1N543, VZ = 5.1 V, were the discrete devices used for comparison purposes. Biasing is provided through a voltage divider.

Fig. 8. Test circuit for compared performance evaluation: (1) discrete de-

vices; (2) LDSD NMOS based emulation circuits; (3) LDMOS based emula-tion circuits.

A. Diode Emulation

For performance comparison , simulation and experimental results using LDSD NMOS (Fig. 8 (2)-η) and LDMOS (Fig. 8 (3)-ι) based “Diode” circuits are presented, in Fig. 9 and Fig. 10, respectively, together with results for discrete devices (Fig. 8 (1)-γ).

a) b)

Fig. 9. Discrete solution vs LDSD-NMOS “Diode” circuit: a) simulation; and b) experimental results.

a) b)

Fig. 10. Discrete solution vs LDMOS “Diode” circuit: a) simulation; and b) experimental results.

Rectifying diode functionality is preserved in the NMOS based “Diode” circuits. Signals η and ι are similar to that provided by a discrete diode, γ.

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B. “Zener” Circuits

“Zener” circuits control, used for simulation and experi-ments on prototypes, was designed in order to present low sensitivity to process parameters and temperature variations. The control voltage VREF is referred to the analog ground and can vary typically from 1 to 4 Volt for an analog circuit sup-ply voltage Vdda = 5 Volt. “Zener” voltage, VZ, is slightly dependent on Cathode voltage, VK, due mainly to the “Zener” diode LDSD body effect.

Programmable “Zener” circuit simulation results, for the test circuit of Fig. 8 are shown in Fig. 11 a) and b), for VK = 10 Volt and 30 Volt, respectively.

a) b)

Fig. 11. Programmable “Zener” circuit simulation results for: a) VK = 10 Volt; and b) VK = 30 Volt.

For performance comparison with that of discrete solutions (Fig. 8 (1)-δ), simulation and experimental results using LDSD NMOS (Fig. 8 (2)-ε) and LDMOS (Fig. 8 (3)-φ) based “Zener” circuits are presented in Fig. 12 and Fig. 13, respec-tively.

a) b)

Fig. 12. Discrete solution vs LDSD-NMOS “Zener” circuit: a) simulation; and b) experimental results.

a) b)

Fig. 13. Discrete solution vs LDMOS “Zener” circuit: a) simulation; and b) experimental results.

Zener functionality is preserved in the NMOS based “Zener” circuits. Signals ε and φ are similar to that obtained for a discrete Zener diode, δ.

C. “Rectifier” Circuits

For performance comparison with that of discrete solutions (Fig. 8 (1)-α), simulation and experimental results using LDSD NMOS (Fig. 8 (2)-β) and LDMOS (Fig. 8 (3)-χ) based “Rectifier” circuits are presented in Fig. 14 and Fig. 15, re-spectively.

Fig. 14. Discrete solution vs LDSD-NMOS “Rectifier” circuit: a) simulation; and b) experimental results.

a) b)

Fig. 15. Discrete solution vs LDMOS “Zener” circuit: a) simulation; and b) experimental results.

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Rectifier functionality is preserved when emulated by NMOS based “Rectifier” circuits. Signals β and χ are similar to the signal, α, obtained for a discrete Zener-diode back-to-back association.

These results lead to an interesting perspective towards low cost monolithic solutions.

The potentialities encountered for the LDSD-NMOS de-vice lead to the conclusion that it presents the ability required to implement the proposed concept, towards low cost smart power circuits, expanding its application range to new areas, automotive applications included, specially those requiring 45 V capability [16], [17].

V. CONCLUSIONS

A new design concept resorting to a unique NMOS iso-lated cell that can be implemented in most standard techno-logical processes was presented.

An elementary power switching cell using an LDSD tran-sistor was described. The basic circuits required by a typical power control block of a Smart Power IC were redesigned in order to obtain only NMOS based circuit implementations.

Moreover, the new concept can be applied to design pro-grammable gate arrays, in order to obtain off-the-shelf solu-tions at low unit production cost and reduced production cy-cle decrease.

Experimental results obtained on prototypes of drive cir-cuits required by the power control blocks of smart power ICs (level shifter interface, clipper, charge-pump, and bootstrap) were also shown. The results confirmed the viability of the approach.

The proposed methodology presents encouraging results for a wide range of low or medium power, high-density ap-plications, enabling the use of standard CMOS technology far beyond its usual limits. A power control block implemented in this way is highly suited for cost effective smart power ASICs.

ACKNOWLEDGMENT

The authors gratefully acknowledge the contributions of Prof. M. Lança to the final manuscript.

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