A 9.5-dB 50-GHz Matrix Distributed Amplifier in 0.18-µm CMOS

Jun-Chau Chien, Tai-Yuan Chen and Liang-Hung Lu

Graduate Institute of Electronics Engineering and Department of Electrical Engineering,

National Taiwan University, Taipei, Taiwan

Abstract

Implemented in a 0.18-µm CMOS process, a 2×4 matrix amplifier is presented in this paper. Due to the use of the second-tier gain cells in the distributed amplifier architecture, the proposed circuit exhibits a remarkable nominal gain of 9.5 dB with a 3-dB bandwidth of 50 GHz while maintaining input and output return losses better than 10 dB over the entire frequency band. A gain-bandwidth product of 150 GHz is demonstrated in this work.

I. Introduction

By incorporating the capacitance from the active devices into the input and output synthetic transmission lines, the distributed amplifiers are widely used to provide wideband signal amplification. With recent advances in deep-submicron technologies, CMOS distributed amplifiers with a bandwidth up to tens of gigahertz have been reported [1]-[4]. However, the gain of these amplifiers is typically limited by the inherently low transconductance of the active devices and the nature of additive gain mechanism. In order to take the advantage of multiplicative gain mechanism, a CMOS matrix amplifier is proposed to enhance the pass-band gain while maintaining the wideband characteristics of the distributed architectures.

II. Circuit Design

The circuit schematic of the fully integrated matrix amplifier with all on-chip components is shown in Fig. 1. A total of eight gain cells are arranged in the form of a 2×4 matrix [5]. The three synthetic transmission lines which are terminated with the characteristic impedances by on-chip resistors are used to connect the gain cells. Fig. 2 shows the small-signal equivalent circuits of the synthetic lines in the matrix amplifier.

In this design, high-impedance coplanar waveguide (CPW) sections with an unloaded characteristic impedance of 120 Ω are utilized to realize the synthetic lines. To minimize the line attenuation due to the conductor loss and possible penetration of EM fields through the lossy substrate, top metal layer in the 1P6M CMOS process is employed for the CPW structure. Based on the full-wave EM simulation, a quality factor better than 20 can be achieved for the CPW at frequencies up to 50 GHz. In consideration of impedance matching, the character- istic impedances of the periodically loaded input and output synthetic lines are 50 Ω. Note that the central line acts as the output for the first tier and the input for the second tier. In a conventional matrix amplifier [6], the central line is loaded with the output node of the first tier and the input node of the

second tier at the same point. To overcome the limitations caused by the severe frequency-dependent attenuation and reduced cut-off frequency due to the excess capacitance and conductance at these nodes, an interleaving loading technique is adopted for the central line by separating the loads from the first and the second tier. With a loaded characteristic imped- ance of 30 Ω for the central line, an equivalent attenuation and cut-off frequency as those of the input and output lines can be achieved, leading to an optimum gain-bandwidth product of the matrix amplifier.

Due to the superior characteristics in gain, stability and input-to-output isolation, cascode stages are used as the gain cells. The parameters of the common-source transistors are chosen for the required input capacitance with a maximum transconductance while the common-gate stages are designed for the required output capacitance with a maximum output resistance. In addition, CPW sections Lm and Lp are included in the gain cells as the inter-stage matching and gain-peaking inductance, respectively, to compensate for the gain roll-off of the transistors at the upper frequency bands.

III. Experimental Results

The proposed matrix amplifier is fabricated in a standard 0.18-µm CMOS process. On wafer-probing was used to characterize the performance of the fabricated circuit. Fig. 3 shows the measured S-parameter from 1 to 50 GHz. Consuming a dc power of 420 mW by the eight cascode gain cells, the matrix amplifier exhibits a peak gain of 11 dB at 38 GHz and a 3-dB bandwidth of 50 GHz. Within the entire frequency range, the nominal pass-band gain and gain ripple are 9.5 and ±1.5 dB, respectively, while the input and output return losses are better than 10 dB. The gain compression measurement is used to evaluate the linearity of the amplifier by sweeping the input power level at input frequency of 20-GHz, as shown in Fig. 4, indicating an output P1dB better than 7 dBm. The measured group delay, as shown in Fig. 5, is approximately 50 ps with a variation of 10 ps from 1 to 40 GHz. Fig. 6 shows the die photo of the fabricated circuit with chip area of 1.86×0.83 mm2 including the pad frame. Table I shows the performance summary of the matrix amplifier and a comparison of state-of-the-art CMOS distributed amplifiers.

IV. Conclusion

A matrix amplifier architecture is proposed to achieve high gain-bandwidth product for wideband applications. Using a 0.18-µm CMOS process, the fabricated circuit exhibits a 3-dB bandwidth of 50 GHz and a nominal gain of 9.5 dB, leading to a gain-bandwidth product of 150 GHz.

1-4244-0006-6/06/$20.00 (c) 2006 IEEE 2006 Symposium on VLSI Circuits Digest of Technical Papers

Acknowledgment

The authors would like to thank National Chip Implemen- tation Center (CIC) for chip fabrication and technical support.

References

[1] R.-C. Liu et al., “A 0.6-22-GHz broadband CMOS distributed amplifier,” Proc. IEEE RFIC Symp., pp. 103-106, Jun. 2003.

[2] R. E. Amaya et al., “A 27 GHz fully integrated CMOS distributed amplifier using coplanar waveguide,” Proc. IEEE RFIC Symp., pp. 193-196, Jun. 2004.

[3] H. Shigematsu et al., “40Gb/s CMOS distributed amplifier for fiber-optic communication systems,” IEEE ISSCC Dig. Tech. Papers, pp. 476-477, Feb. 2004.

[4] R.-C. Liu et al., “An 80GHz traveling-wave amplifier in a 90nm CMOS technology,” IEEE ISSCC Dig. Tech. Papers, pp. 154-155, Feb. 2005.

[5] T.-Y. Chen et al., “A 45.6-GHz matrix distributed amplifier in 0.18-µm CMOS,” IEEE Custom Integrated Circuits Conference, pp. 119-122, Sep. 2005.

[6] K.B. Niclas et al, “A 2-18 GHz low-noise/high-gain amplifier module,” IEEE Transactions on Microwave Theory and Techniques, vol. 37, no. 1, pp. 198-207, Jan. 1989.

Fig. 1. The schematic of the 2×4 matrix distributed amplifier. Fig. 2. The small-signal equivalent circuits of the synthetic lines.

Frequency (GHz)

S-pa

ram

eter

(dB

)

Frequency (GHz)

S-pa

ram

eter

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)

Input power (dBm)

Out

put p

ower

(dB

m)

Input frequency = 20-GHz

Input power (dBm)

Out

put p

ower

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m)

Input frequency = 20-GHz

Frequency (GHz)

Gro

up D

elay

(ps)

Fig. 3. The S-parameters of the matrix amplifier. Fig. 4. The gain compression characteristics. Fig. 5. Group delay of the matrix amplifier.

Table I Performance Summary of CMOS Distributed Amplifiers.

Fig. 6. The die photo of the fabricated circuit.

1-4244-0006-6/06/$20.00 (c) 2006 IEEE 2006 Symposium on VLSI Circuits Digest of Technical Papers