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CLOCK DISTIBUTION SCHEMES AND POWER DISTRIBUTION AT DIFFERENT LEVELS IN

VLSI DESIGN

Prof. Halesh M. R

Asst. Professor, ECE Dept.

JIT - Davanagere

ARKA Educational & Cultural Trust (Regd.)

Jain Institute of Technology, Davanagere(A Unit of Jain Group of Institutions, Bangalore)

Oral Presentation at National Conference on “Recent Trends in Communication and Computing”

(NCRTCC-2016)



OVERVIEW• Introduction to Power Distribution• Power Distribution at Different Level Of

Designi. Algorithm Level Reduction

ii. Architectural Level Techniques

iii. Gate Level Techniques

• Clock Distribution Schemes• Conclusion



CMOS digital systems are approaching to gigahertz frequency

range. It is the result of submicron technology [4]. The total power

dissipation consists of two components:

1. The Static power dissipation.

2. The Dynamic power dissipation

Power dissipation in 80C51 IC

INTRODUCTION TO POWER DISTRIBUTION:



Short circuit power is result when both p-transistor and n-transistor is on for short duration of time. Mathematically,

VVV tntpDD

Where α, is switching activity, C is capacitance and f is operating frequency.

fCP V 2

Switching energy

Power dissipation is given by

Dynamic power dissipation by switching of clock is given by: CCVP DLDDclk

f ..2



Layout Level

Transistor Level

Logic Level

RT Level

Behavior Level

System Level

Incr

easi

ng

Pow

er

Savi

ngs

10-20 X

2-5 X

20-50 %

Power Distribution at Different Level Of Design:

Here we see that as the level of design goes lower level to upper level as layout level to system level number of counted error increase means power saving possibilities are more at higher levels.



ALGORITHM LEVEL REDUCTION:

1. Power consumption at algorithm level related to properties of that

particular algorithm technique, So it should carefully select for lowering

the power consumption [6].

2. For lowering the power, algorithm should be such that it should

minimize the number of switching requirements.

3. That algorithm is more useful which have minimum number of

operation because it will require less hardware.

4. By increasing concurrency we can increase efficiency of that device.



ARCHITECTURAL LEVEL TECHNIQUES:

1. The basic building block at this level are registers, busses multipliers, memories, state machine etc. Each block performs high level function [7].

2. The architectural level is the design entry point for the large majority of digital designs and design decisions at this level can have dramatic impact on the power budget design.

3. Power is as the function of their operating frequency and number of bits of components.



1. Power And Performance Management: Power management is done by

different saving modes such as DOZE, NAP and SLEEP modes by

deactivating blocks at different levels, function levels [8].

2. Parallel and pipelined: This architecture is another aspect which is also

taken into consideration. In parallel architecture frequency is scaled down

by factor ‘n’, number of blocks.

In parallel architecture area required is more but operation is become faster.

In pipelining mode frequency remain same but voltage is scaled down.



Factors N-Parallel

Arch.

N-Pipeline

Arch.Capacitance N * Cref Cref

Voltage Vref / N Vref / N

Frequency fref / N fref

Dynamic Power Cref Vref2 fref / N2 Cref Vref

2 fref / N2

Chip Area N – times 10–20% Increase

Comparison Between Parallel And Pipelined Architectures:



GATE LEVEL TECHNIQUES:

1. Local Restructing

2. Signal gating

3. Logic Encoding

4. Bus Inverter Encoding

Bus Inverter Encoding



CLOCK SCHEMES:

For providing synchronization of the digital system one or more reference

clocks are used.

Fully synchronization is done by using common clock, By a single clock all

parts of digital system is clocked for different operations.

There are two types of clock schemes:

1. Single driver clock scheme and

2. Distributed buffers clock scheme.



i. Single buffer scheme: If the interconnect resistance of the buffer at the

clock source is small as compared to the buffer output resistance, it is

called as single driver clock scheme.

The single driver scheme has the advantage of avoiding the adjustment of

intermediate buffer delay as in distributed buffer schemes.

ii. Distributed buffer scheme: This is the most common and general

approach for equipotential clock distribution scheme. It leads to an

asymmetric structure.

In single driver scheme, short circuit power dissipation is more than

distributed buffer scheme due to the reason of small buffer used in

distributed buffer scheme.



There are two problems in clock generation:

1. Clock Skew: This is the variation in delay from clock source to clock

destination in different clocks.

2. Clock Jitter: It is defined as temporal variation of clock with respect to

reference edge. It is of two type long jitter and cycle to cycle jitter.



CONCLUSION:

a. Here we reviewed the different low power techniques at each level of

VLSI Design.

b. Different techniques have different tradeoffs. We use particular techniques

according to specification.

c. Here clock skew and clock jitter problem are also reviewed and these are

eliminated by using appropriate clock distribution schemes.



Distributed Buffer Scheme









REFERENCES

[1] J. Wang, S. Fang, W. Feng, “New Efficient Designs for XORand XNOR Functions on the Transistor Level”, IEEEJournal of Solid-State Circuits, 29(7), 1994, 780–786.

[2] R. Zimmermann, W. Fichtner, “Lowpower Logic Styles:CMOS Versus Passtransistor Logic”, IEEE Journal of Solid-State Circuits, 32 (7), 1997, 1079– 1089.

[3] Shams A. M., Darwish T. K. and Bayoumi M. A., “Performance analysis of low-power 1-bit CMOS full adder cells,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 10, No. 1, pp. 20–29, Feb. 2002.

[4] Radhakrishnan D., “Low-voltage lowpower CMOS full adder,” IEEE Proc. Circuits Devices Syst., Vol. 148, No. 1, pp. 19–24, Feb. 2001.

[5] Zhang M., Gu J. and Chang C. H., “A novel hybrid pass logic with static CMOS output drive full adder cell,” in Proc. IEEE Int. Symp. Circuits Syst., May 2003, pp. 317–320.



[6] Chang C.-H., Gu J. and Zhang M., “A review of 0.18-µm full adder performances for tree structured arithmetic circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 13, No. 6, pp. 686– 695, Jun. 2005.

[7] Goel S., Kumar A. and Bayoumi M. A., “Design of Robust, Energy Efficient Full Adders for Deep Submicrometer Design Using Hybrid- CMOS Logic Style," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 14, No. 12, pp. 1309– 1321, Feb. 2006.

[8] Giacomotto C. and Oklobdžija V.G., "LogicStyle Comparison for Ultra Low PowerApplications,"Techcon (SemiconductorResearch Corp.), Oct. 2005.

[9] "Predictive Technology Model”, Websitecurrently available online at www.eas.asu.edu/~ptm.

REFERENCES Continued…



THANK YOU

Any Queries…?

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