Novel Ultra-Low Power RRAM with Good Endurance and Retention C. H. Chenga,b, Albert Chinb, and F. S. Yeha

a E.E. Dept., Natl. Tsing Hua Univ.; b E.E. Dept., Natl. Chiao-Tung Univ., Hsinchu, Taiwan ROC albert_achin@hotmail.com

Abstract We report high performance RRAM of ultra-low 4 μW set

power (-3.5 μA at -1.1 V), 16 pW reset power (0.12 nA at 0.13 V), large extrapolated 10-year on/off retention window of 4×105 at 85oC, good 106 cycling endurance and fast 50 ns switching for the first time. These were achieved using novel covalent-bond-dielectric/metal-oxide and low cost electrodes.

Introduction The RRAM [1]-[6] and PCM provide a potential solution

for down scaling beyond MONOS non-volatile memory (NVM) [7], but the very high set/reset currents are the limits for low-power high-density operation. For array operation and vertical 3D stacking, the unipolar mode is preferred to bipolar one, but the poor endurance, small ratio of high- to low- resistance state (HRS/LRS), current compliance related large transistor and high forming power are other challenges. To address these issues, we report a novel ultra-low power RRAM with setting -3.5 μA and -1.1 V to LRS and resetting 0.12 nA and 0.13 V to HRS. The very low reset current and voltage allow using a diode operated at reverse bias. Excellent 106 cycling endurance is also reached with fast switching 50 ns time. Such record high performances were achieved using covalent-bond-dielectric/metal-oxide of GeOx/SrTiO3 (GeO/ STO), but unreachable for HfO2/STO all metal-oxides stack. This is further supported by measured negative temperature coefficient (TC) of GeO/STO rather than the positive TC in metal-oxide RRAM by metallic filament conduction [5]. Such negative TC is also known in highly defective Si and GaAs by hopping conduction [8]. This suggests the mechanism for LRS to be related to hopping via oxygen vacancies, since improved switching performance is obtained under oxygen-deficient process. The weakly linked hopping conduction, rather than metallic filament, also gives low reset power due to easily disconnect conduction pass. Such excellent performances are near the ideal NVM with very large 10-year retention window of 4×105 at 85oC, good 106 endurance, fast 50 ns switching, low 375 fJ switching energy, small 4F2 size, capable for vertical 3D stacking, potential scalable to 10th nm, simple process, useful for embedded and stand-alone function.

Experimental Procedure For backend integration, the Ni/GeO/STO/TaN device was

made on SiO2/Si substrate by PVD deposited 25 nm TaN, various thick STO and GeO, and 50 nm Ni top electrode. The patterned MIM device was measured by set/reset, cycling and retention at 85oC under the similar MONOS NVM tests [7].

Results and Discussion A. Set/Reset Characteristics:

Fig. 1 shows the swept I-V curves of Ni/STO/TaN RRAM. The very high 0.3 mA set current at -2 V is the basic limitation for conventional RRAM. The bipolar mode operation, with opposite polarity current for set and reset, needs a large size MOSFET for 1R1T operation rather than using a small diode. Fig. 2 shows the swept I-V of covalent-bond Ni/GeO/TaN RRAM. Small LRS current <1 nA at <0.5 V and negative reset voltage are measured and opposite to Ni/STO/TaN device. This may be related to electron injection created defects in covalent-bond GeO from lower work function TaN (4.6 eV) than top Ni (5.1 eV), rather than the metallic filament

in metal-oxide RRAM [5]. To further use the merits of large memory window STO and low current GeO, we formed the Ni/GeO/STO/TaN RRAM (Fig. 3). Very low self-compliance set current of -3.5 μA at -1.1 V (4 μW), reset 0.12 nA at 0.13 V (16 pW) and very large 5×105 HRS/LRS are reached. The very small reset current and voltage can be driven by a diode at reverse bias and behavior as a unipolar-like operation. Even larger 3×106 HRS/LRS is obtained at oxygen-deficient STO. In contrast, much poor HRS/LRS is measured in all metal- oxides Ni/HfO2/STO/TaN RRAM in Fig. 4. The set/reset voltage and current depend strongly on GeO thickness (Fig. 5); even 0 V reset, the pure unipolar mode, is obtained at thinner GeO. This unipolar-like RRAM is different to conventional unipolar mode that is also obtainable in the same device (Fig. 6), but suffered from high set current, poor endurance [5]-[6] high current compliance related large size transistor, and high forming power allied unpredictable resistance states. This new device has good set and reset voltage distribution in Fig. 7. Since the HRS/LRS is as high as 5×105, simple operation of cross-point array can be realized to reset all cells to HRS. The selected cells are set to LRS with small 0.2 V read voltage. B. Conduction Mechanism, Retention & Cycling:

To understand the record lowest power, we measured the temperature-dependent currents in Fig. 8. The very small HRS current is ruled by Schottky emission via high work-function Ni. The current at LRS follows the ohmic law, and slight current variation is related to carrier trapping/de-trapping. Fig. 9 is the temperature dependence and the LRS resistance vs. temperature is plotted in Fig. 10. A negative TC, the lower R at higher temperature, is measured up to 150oC and opposite to the positive TC in conventional metal-oxide RRAM [5]. The 0.35 eV activation energy is close to that of negative TC in highly defective Si ruled by hopping conduction [8]. This suggests LRS mechanism to be related by hopping via defects. The major defects may be oxygen vacancies due to the improved device performance at oxygen-deficient STO (Fig. 3). Such weakly linked hopping conduction can be easily broken by injected electrons over low work-function TaN:

Vo2+ + 2e- + O → Oo

* (1) This is quite different from the metallic filament in metal- oxide RRAM [5]. This also explains the record lowest reset power, the excellent 106 endurance at fast 50 ns cycling and ultra-low 375 fJ switching energy (-5 μA, -1.5 V & 50 ns) shown in Fig. 11, where even over stressed set/reset voltages are used. A large 10-year extrapolated memory window of 4×105 at 85oC is also reached (Fig. 12) that may be due to the 0.84 eV ΔEC in GeO/STO. Table 1 compares RRAM devices. This new device has 130~3×104X lower power than the best reported RRAM with the largest HRS/LRS window [1]-[6].

Conclusions We report ultra-low power RRAM with excellent 10-year

extrapolated 4×105 window at 85oC and 106 cycles at 50 ns. References

[1] H. Sim et al, IEDM Tech. Dig., 2005, pp. 777-780. [2] D. Lee et al, IEDM Tech. Dig., 2006, pp. 797-800. [3] N. Xu et al, Symp. on VLSI Tech., 2008, pp. 100-101. [4] D.-J. Seong et al, IEDM Tech. Dig., 2009, pp. 101-104. [5] U. Russo et al, IEDM Tech. Dig., 2007, pp. 775-778. [6] H.S. Yoon et al, Symp. on VLSI Tech., 2009, pp. 26-27. [7] H. S. Lin et al, IEDM Tech. Dig.,2008, pp. 843-846. [8] A. Chin et al, Appl. Phys. Lett., no. 5, pp. 653-455, 1996.

978-1-4244-7641-1/10/$26.00 ©2010 IEEE 2010 Symposium on VLSI Technology Digest of Technical Papers 85

-1.0 -0.5 0.0 0.5 1.010-13

10-11

10-9

10-7

10-5

10-3

10-1

Unipolar

0.0 0.5 1.0 1.5 2.0 2.5 3.010-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

Forming current

C

urre

nt (A)

Voltage (V)

Unipolar-Like

2

12

Self Compliance

Current Compliance= 1mA

Ni-GeO(8nm)/STO-TaN

A

bs.(I

) (A)

Voltage (V)

1

Fig. 2. Swept I-V curves of covalent-bond-dielectric Ni/GeO/TaN RRAM with different thickness of GeO.

Fig.1. Swept I-V curves of conventional Ni/STO/TaN RRAM. The arrows indicate the bias sweeping direction.

Fig. 11. Endurance of Ni/GeO/STO/TaN RRAM. The 50 ns is limited by equipment. Stable switching is obtained to 106 cycles.

Fig 5. Swept I-V curves dependent on GeO thickness. Pure unipolar transition (0 V reset) is reached in thinner GeO.

Fig. 8. I-V of (a) HRS and (b) LRS by fitting with Schottky emission and ohmicconduction mechanisms, respectively.

Fig.12. Retention of Ni/GeO/STO/TaN and Ni/GeO/TaN RRAM at 85oC.

Fig. 6. I-V curves of Ni/GeO/STO/TaN RRAM. Both new unipolar-like and conventional unipolar modes are obtained.

Fig. 9. Temperature dependent HRS and LRS of Ni/GeO/STO/TaN RRAM and showing negative temperature coefficient.

-1.0 -0.5 0.0 0.510-13

10-11

10-9

10-7

10-5

10-3

3x106

5x105

Forming- Free

Self Compliance

3

2VRESET(ISET, VSET)

GeO(8nm)/STO GeO(8nm)/STO

@ O-deficient

A

bs.(I

) (A)

Voltage (V)

1

Table 1. Comparison of device integrity data for various RRAM devices.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.010-13

10-11

10-9

10-7

10-5

10-3

On-Off ratio ~3 order Read out @-0.2V

4

3

2 Ni-STO(12nm)-TaN

Abs

.(I) (

A)

Voltage (V)

1

Fig. 7. VSET and VRESET distributions of new type RRAM devices.

Fig. 3. Swept I-V curves of forming-free stacked Ni/GeO/STO/TaN RRAM with both normal and oxygen-deficient STO.

-1.0 -0.5 0.0 0.510-13

10-11

10-9

10-7

10-5

10-3

Forming- Free

Self Compliance

HRS

GeO(5nm)/STO GeO(8nm)/STO

A

bs.(I

) (A)

Voltage (V)

5x105

0 25 50 75 100 125 150 175

10-11

10-9

10-7

10-5

5nm-GeO/STO 8nm-GeO/STO

Temperature (oC)

Read @-0.2V

LRS

A

bs. (

I) (A)

HRS

Fig. 4. Swept I-V curves of stacked all metal-oxides Ni/HfOx/STO/TaN RRAM. Very poor HRS/LRS is measured at 0.2 V.

-2 -1 0 1 2 3 410-13

10-11

10-9

10-7

10-5

10-3

4

3

2

A

bs. (

I) (A)

Ni-HfO(8nm)/STO(12nm)-TaN

Voltage (V)

1

0.3 0.0 -0.3 -0.6 -0.9 -1.20

20

40

60

80

100 5nm-GeO/STO 8nm-GeO/STO

VRESET

C

umul

ativ

e pr

obab

ility

(%)

Voltage (V)

VSET

-0.2 -0.4 -0.6 -0.8 -1.00.0

0.5

1.0

1.5

2.0

2.5

@25oC

(b)

5nm-GeO/STO 8nm-GeO/STO

Abs

.(I) (

A)

Voltage (V)

LRS (SET) X10-5

0.9 0.6 0.3-30

-28

-26

-24

-22

-20

5nm-GeO/STO 8nm-GeO/STO

(a)

HRS (RESET)

Schottky Emission

Slope=2.8

V1/2 (V)

Slope=2.5

ln

(I)

-1 0 1 2 3 410-13

10-11

10-9

10-7

10-5

10-3

4

3

2

GeO(5 nm) GeO(8 nm) GeO(12 nm)

Area= 11304 um2

A

bs.(I

) (A)

Ni-GeO-TaN

Voltage (V)

1

100 101 102 103 104 105 106 107 10810-13

10-11

10-9

10-7

10-5

8nm-GeO/STO 8nm-GeO

Time (sec)

Read @ -0.2V, 85oC

LRS

A

bs. (

I) (A)

HRS

Fig. 10. LRS resistance as a function of temperatures, energy band diagram and hopping conduction via GeO/STO.

25 30 35 40 45 5010

11

12

13

14

15T (oC)

ln(R

SET)

(Ω)

1/kT (K-1)

27100150

5.8 eV3.3 eV

0.84 eV

1.66 eV

ooo

oo

GeO

Dielectric Nb:STO [1] Cu-MoOx [2] ZnO [3] Al/PCMO [4] NiO [5] NiO/WOx [6] GeO/STO

T/B Electrode Pt/Pt Pt/Cu TiN/Pt Pt/W Au/n-Si W/Ru Ni/TaNISET @ VSET 10mA, 1V 100mA, 2V 3mA, 0.9V -1mA, -3V 0.6mA, 3.9V 20uA, 1.1V -3.5uA, -1.1V

IRESET@ VRESET -10mA, -3V -80mA,-1.5V -4mA, -1.2V 1uA, 3V 5mA, 1.4V 1mA, 0.5V 0.12nA, 0.13VOn/Off Ratio ~102 15x ~3x102 >102 ~ 2x102 ~103 >105

Retention 2x106, 125C 105, 85C 104 , 25C 105, 125C — — >105, 85CCycles, pulse 2x107,500us 106, 1us — 106, 1us — — 106, 50ns

PowerSET, RESET 10, 30mW 200, 120mW 2.7, 4.8mW 3mW, 3uW 2.3, 7mW 22uW, 0.5mW 4uW, 16pW

100 101 102 103 104 105 106 10710-13

10-11

10-9

10-7

10-5

10-3

Read @-0.2V

8nm-GeO/STO RRAM

Number of Switching Cycles

SET: -1.5V, 50nsRESET: +0.5V, 50ns

LRS

A

bs.(I

) (A)

HRS

978-1-4244-7641-1/10/$26.00 ©2010 IEEE 2010 Symposium on VLSI Technology Digest of Technical Papers 86