Ripple-Port Module-Integrated Inverter for Grid-Connected PV Applications

Souhib Harb, Mehran Mirjafari, Robert S. Balog Renewable Energy & Advanced Power Electronics Research Laboratory

Department of Electrical & Computer Engineering Texas A&M University

College Station, Texas 77843, USA souhib85@gmail.com, mmirjafari@neo.tamu.edu, robert.balog@ieee.org

Abstract – The single-phase inverter has inherent double-frequency power ripple, which if not mitigated internally appears at the input port and deteriorates the MPPT performance. Conventional dc link inverter topologies filter this significant double-frequency ripple by means of the bus capacitance, usually in the form of electrolytic capacitors which have well-known lifetime challenges. This paper presents a double-frequency ripple cancelation concept and experimental proof of concept. The proposed module-integrated inverter is based on the commonly used two-stage inverter. However, a third port is added for ripple cancelation purposes. Hence, a very small capacitance is needed, and, as a result, high reliability film capacitor can be used instead of the bulky, low reliability electrolytic ones.

I. INTRODUCTION Photovoltaic (PV) Module-Integrated Inverter (PV-MII)

has become the trend for grid-connected PV applications [1] due to its numerous advantages including: improved energy harvest; improved system efficiency; lower installation costs; Plug-N-Power operation; and enhanced flexibility and modularity [1-4]. However, mounting the power electronics directly to the PV module necessitates using highly reliable converters due to the thermal environment [5] and the need for a 25 year lifetime to match the PV module [1, 6, 7]. Inherent in a single-phase MII is double-frequency ripple that is usually filtered using bulky electrolytic capacitors [1]. It is well known that the electrolytic capacitor is the limiting component of the reliability of the MII [8].

Recently, a number of new inverter topologies that use a high reliable film capacitor for power decoupling purposes have been proposed [9-17]. These topologies are cost effective for film capacitors because only 10's of microfarads (instead of the 10,000uF or more for conventional topologies) of capacitance are needed. However, the control in most cases can become very complicated, and require many sensing signals. The latter increases cost, reduces power density, and can deteriorate reliability. In contrast, the control of the proposed ripple-port topology is very simple, and straightforward as it will be shown later in the paper. Although criterion for minimum

energy storage is established [18], the design tradeoffs to minimize the value of capacitance has not been fully explored.

This paper presents a double-frequency ripple cancelation technique, based on a ripple-port concept [18], and experimental validation. The proposed topology, suitable for use as a module-integrated inverter (MII), is based on the commonly used two-stage inverter with a third port is added, at the DC-link, for ripple cancelation purposes. Hence, a very small capacitance is needed, and, as a result, high reliability film capacitor can be used instead of the bulky, low reliability electrolytic ones [8, 19, 20].

II. RIPPLE-PORT MODULE-INTEGRATED INVERTER (RP-MII)

Figure 1 shows the block diagram of the ripple-port module-integrated inverter (RP-MII) in which double-frequency ripple cancelation is accomplished by adding a “ripple-port” on the DC-link of the multi-stage inverter. The proposed RP-MII significantly reduces the minimum required power decoupling capacitance, CD. Another advantage is that this ripple port concept can be used with any isolated DC/DC converter topology capable of boosting the input voltage and providing galvanic isolation for grid-connected applications.

Figure 1: Ripple-port module-integrated inverter (RP-MII).

978-1-4673-0803-8/12/$31.00 ©2012 IEEE 1115

III. RP-MII IMPLEMENTATION The input DC/DC stage can be implemented using any

DC/DC converter topology that is capable of boosting the voltage from the PV module and providing the needed galvanic isolation for safety purposes. To demonstrate the concept, the popular flyback converter is used in this paper [1, 9, 10, 13, 16]. The proposed MII can be implemented in two ways: integrated and auxiliary ripple-port winding. Both implementations are explored in this paper along with simulation results and the integrated RP-MII is experimentally verified. Although the separated ripple-port winding can be implemented in a way that further reduces the required decoupling capacitance, its impact on the reliability, compared to the integrated option, is very small. The detailed analysis is presented in section V.

A. Integrated Ripple-Port (Single Flyback Output) Figure 2 shows the implementation of the proposed RP-

MII with single output flyback converter. The ripple-port is integrated with the output port on the secondary winding of the flyback coupled inductor. Hence, the peak voltage of the decoupling capacitor is limited by the dc link. For a 235W inverter with a 200Vdc DC-link and depth of modulation (DoM) of 0.95 for the ripple-port DC/AC inverter, 36µF is needed. However, due to imperfect coupling between the transformer’s winding, a slightly larger decoupling capacitance is needed in practice.

Figure 2: Ripple-port MII, integrated design.

B. Separated Ripple-Port (Multiple Flyback Outputs): Figure 3 illustrates the integration of the ripple-port into

the flyback converter through a separated transformer winding. In this case, the decoupling capacitor peak voltage is not limited by the DC-link. Consequently, the capacitance can be minimized by using a higher voltage. For the same 235W RP-MII, but with a turns ration to provide 550Vdc at the input to the ripple-port, only 4.6µF is needed (5µF is used in the simulation). This extra degree of design freedom carries with it the tradeoffs of requiring extra components and the efficiency implications of power losses and transformer leakage energy.

Figure 3: Ripple-port MII, auxiliary winding.

IV. RIPPLE-PORT POWER PROCESSING Figure 1 illustrates the voltage polarity and current

direction in the ripple-port load/source (LD and CD). A small inductor is needed to prevent sudden changes in the capacitor’s voltage because of the switching effect. Assuming a unity power factor at the output (grid) side, the output power has both an average value and a component pulsating at twice the mains frequency as follows:

( )( )tPPtp

tIVtp

oPVPV

o

ωω

2cos)(sin)(

0

2000

+== (1)

The role of the ripple-port is to process the power at the DC-link, which implies that the effect of the output low pass filter (Lf - Cf filter) should be taken in consideration in order to achieve an accurate ripple cancelation at the input side. This can be accomplished by considering the power at the input of the output Lf - Cf filter. The voltage at the input side of the output Lf - Cf filter is calculated in (2), where just the fundamental component is considered.

( )

)(0)('0

sin)( '0

'0

tv

fCZfLZ

fCZtv

tVtv o

+=

+= θω

(2)

Where fCZ and

fLZ are the capacitor and inductor impedances, respectively. An ideal output LC filter will not alter the phase of the output voltage. However, in practice, both the inductor and the capacitor have series resistance, and thus, the amplitude and the phase of the output voltage will be affected, over a large range of frequency, due to lowering the Q factor of the LC filter. The impact of the LC filter on the amplitude is insignificant, and can be neglected. Consequently, the power that is processed by the output side H-bridge is given in (3).

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( )( )θω ++= tPPtp oPVPV 2cos)(0 (3)

On the other hand, the input power, extracted from the PV module, is controlled to be a constant level, PVP . Then, the ripple-port will be processing the difference between the input and the output power as given in (4).

)()( 0 tpPtp PVrip −= (4)

The power processed by the ripple-port is the total power processed by the decoupling capacitor, CD, and the inductor, LD, which is calculated as follows:

)()()()()()()( titvtitvtptptpDDDDDD CCLLCLrip +=+= (5)

However, the same current flows in both LD and CD, which it is given in (6). Then, )(tprip as function of LD, CD, and the peak capacitor voltage is given in (7).

( )φωω +== tCVdt

tdvCti ooDC

CDC D

D

Dcos

)()( (6)

( ) ( )( )φωωω

+−

= tCLCV

tp oDDooDC

ripD 2sin

21

)(22

(7)

Substituting (3) and (7) in (4), the required decoupling capacitance, CD, and the phase angle of the voltage across the decoupling capacitor is calculated as shown in (8) and (9).

( )DDooC

PVD CLV

PC

D

22 12

ωω −=

, (8)

and ( )( ) ( )( )φωθω +=+ tt 02sin02cos

θπφ +±=

4

(9)

Figure 4: Balanced power waveforms.

From (8), it is clear that the designer has to make a compromise between the decoupling capacitance and the peak voltage across its terminals; the latter will determine the stresses on the power switches, which, in turn, affect the efficiency and the cost of the inverter. Controlling the voltage across the decoupling capacitor according to (8) and (9) will result in a balance three-port system. Figure 4 shows power waveforms of the RP-MII, where the double-frequency ripple, at the input side, is eliminated.

V. RELIABILITY OF THE PROPOSED RP-MII The proposed topology aims to improve the reliability of

the MII by using film capacitors instead of electrolytic ones. Hence, the reliability improvement for both topologies is examined. However, from [8], it was found that the decoupling capacitor is the limiting component whether electrolytic or film is used. So, the failure rate of the film capacitor is found using (10) [21]:

EQCVbP πππλλ = (10)

λb is given in (11), which is function of the operating temperature (T (°C)) and voltage stress (S). These two factors are operating factors.

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛⎟⎠⎞

⎜⎝⎛ +

⎥⎥

⎦

⎤

⎢⎢

⎣

⎡+⎟

⎠⎞

⎜⎝⎛=

18

3982735.2exp1

5

4.000099.0 TS

bλ (11)

Thus, λb, πQ, and πE all operating-related factors, and will be the same for both configurations (integrated and separated options). Hence, they can be factored out, and λP is function of just the capacitance factor, πCV, which is for film capacitor is calculated by (12).

085.01.1 CCV =π (12)

Then, the failure rate of the decoupling capacitor is given (13).

KCVP πλ = (13)

where

EQbK ππλ=

Evaluating the failure rate for both configurations, with 36µF used in the first configurations Fig. 2, and two 5µF capacitors in the second configuration in Fig. 3, the capacitance factors are calculated in (14).

( ) KPCV 492.11492.1085.0361.11 =⇒== λπ

( ) ( ) KKPCV 522.2261.122261.1085.051.12 ==⇒== λπ (14)

0 8 10 3−× 0.016 0.024 0.032 0.04400−

200−

0

200

400

600

p0 t( )

pripple t( )

Ppv

t

P0 PPV

Prip

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Then, the conclusion is that the number of capacitors used has a stronger effect on the failure rate than the value of the capacitance itself. Moreover, the lifetime projection formula in (15) [22] does not depend on the capacitance value, consequently, both decoupling will have the same expected lifetime, providing the same operating conditions.

⎥⎥⎦

⎤

⎢⎢⎣

⎡

⎟⎟⎠

⎞⎜⎜⎝

⎛

⎟⎠

⎞⎜⎝

⎛

+

−

=

⎟⎟⎠

⎞⎜⎜⎝

⎛

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

5167.06087.2

1020

rVopV

rVopV

TrefT

L

L (15)

where L0 is the basic (test) lifetime, Vop is the operating voltage, Vref is the rated voltage, T is the operating temperature, and Tref is the test temperature.

As a result, from reliability point view, using film capacitor, regardless of its value, will improve the overall reliability of the inverter.

VI. SIMULATION RESULTS For the 235W system, the component values of the RP-

MII are listed in Table I. PSIM was used to verify the validity of the proposed RP-MII. Figure 5 shows that the input, output, and ripple power waveforms match the theoretical predictions in Figure 4. Figure 6 reveals that processing 238W results in less than a 1W ripple (0.42% power ripple) at the input. DC-link, output, and decoupling capacitor voltages are shown in Figure 7. Figure 8 shows the FFT waveform of the input power.

TABLE I: COMPONENTS lIST USED IN THE SIMULATION.

Component Value Component ValueVin 30 Vdc Lin 4mHV0 120 Vrms Lm 6µHfs1 50KHz Lf 1mHfs2 100KHz LD 100µH

n2:n1 10:1 Cin 50µFn3:n1 27:1 Cf 10µFR0 61Ω CD 40µF

Figure 5: Balance power waveforms.

Figure 6: Zoom in of the input power waveform showing attenuation of the double-frequency ripple.

Figure 7: DC-Link, output, and decoupling capacitor voltage.

Figure 8: FFT of the input power waveform.

VII. EXPERIMENTAL RESULTS The ripple-port concept was experimentally tested using

the new Solar_HV_DC_AC kit from Texas Instruments (TMDSHV1PHINVKIT) [23]. It is simply an IGBTs-based full bridge inverter followed by a low pass filter (LC-filter). Two boards were used to implement the output inverter and the ripple-port inverter as shown in Figure 9. Table II lists the values of the components used in the experiment test. Both boards were controlled by the PWM signals generated using a single TI Delfino microcontroller (TMS320F28335). Figure 10 shows the output and decoupling capacitor voltages and the resulting ac component of the input current. The depth of modulation (DoM) for the output H-Bridge was kept constant at 0.85. The depth of modulation of the ripple-port H-Bridge (DoMr) and the phase angle (φ) were

4952.00 4960.00 4968.00 4976.00Time (ms)

0.0

-200.00

200.00

400.00

Ppv P0 prip

4952.00 4960.00 4968.00 4976.00Time (ms)

238.30

238.40

238.50

238.60

238.70

238.80

238.90

Ppv

4952.00 4960.00 4968.00 4976.00Time (ms)

0.0

-100.00

-200.00

100.00

200.00

300.00

V0 VCd Vs

0.0 50.00 100.00 150.00 200.00Frequency (Hz)

1.00e-013M

1.00e-010M

1.00e-007M

1.00e-004M

Ppv

P0 PPV

Prip

Vdc

VCD V0

60Hz 120Hz

1118

manually tuned to minimize the double-frequency ripple at the input side. The waveform in Figure 10 shows that the ripple current is suppressed to less than 10% peak-to-peak, and this at DoMr = 0.848 and φ = 51.5°. Figure 11 shows the input current along with its experimentally measured FF which confirms that the 120Hz frequency has been suppressed to the same amplitude as the other low-order harmonics.

Figure 9: Ripple-port experiment set up.

TABLE II: EXPERIMENTAL COMPONENTS VALUES.

Component Value Component Value Vin 120Vdc Iin 500mA Lf 3.5mH Cf 1µF R0 70Ω LD 100µH CD 40µF Cin 40 µF

Figure 10: Experimental waveform: ac output voltage, ripple-port

decoupling capacitor voltage, and the input current ripple.

Figure 11: Input current (top trace), and the FFT experimental measurement (bottom trace).

To examine the efficacy of the ripple-port, the DoMr was reduced to 0.5, while the value of φ is kept the same as in the previous case. The results, shown in Figure 12, clearly show the double-frequency ripple at the input side. In this case, the input ripple was 476m peak-to-peak. Figure 13 shows the input current and its experimentally measured FFT, which is 30dB higher than what was achieved with manual tuning in Figure 11.

Figure 12: Output voltage, decoupling capacitor voltage, and the input current when ripple port is purposely mis-adjusted.

AC output side H-Bridge

Output side H-Bridge

Ripple-portLD &CD

MicrocontrollerBoard

Resistive Load

Input Voltage

φ

AC output voltage

Decoupling capacitor voltage

Input current ripple

AC output voltage

Decoupling capacitor voltage

Input Current ripple

1119

Figure 13: Input current (top trace), and the FFT for reduced DoMr.

VIII. CONCLUSION This paper proposes a new inverter topology that

implements the double-frequency ripple cancelation concept. The proposed module-integrated inverter (MII) is based on the commonly used two-stage inverter. A third port is added for ripple cancelation purposes; it simply attached to the DC-Link. This implies that the ripple-port could be added to many commercially available inverter topologies. A very small capacitance is required, where a high reliability film capacitor can be used instead of the bulky, low reliability electrolytic ones. Consequently, MII reliability is improved. Two configurations for implementing the proposed MII were examined by simulation, and the best was experimentally tested.

ACKNOWLEDGMENT The authors would like to thank Texas Instruments for

their in-kind support of this research.

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