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Performance Improvement of La2O3/ p-GaAs MOS Capacitor by using Si Pasivation Layer

Anindita Das, Sanatan Chattopadhyay Centre for Research in Nanoscience and Nanotechnology

Department of Electronic Science University of Calcutta

Kolkata, India an.indita@yahoo.com, scelc@caluniv.ac.in

Goutam Kumar Dalapati Institute of Materials Research and Engineering, Agency for Science, Technology and Research

(A*STAR) Singapore

dalapatig@imre.a-star.edu.sg

Abstract— The RF sputtered La2O3/ p-GaAs MOS capacitors with and without Si interface passivation layer (IPL) have been fabricated and characterized. It has been observed that the presence of (La2O3)1-x(SiO2)x at the interface improved the device characteristics in terms of oxide capacitance (~3.3 fF/μm2), frequency dispersion (~8%) and interface state density (~1.2×1012 cm-2 eV-1). The best device performance was obtained for Al/ La2O3/Si/p-GaAs samples annealed at 500oC.

Keywords- La2O3, GaAs, Si passivation, interface state density

I. INTRODUCTION With the advancement of semiconductor technology the device dimensions have been scaled down aggressively, so much so that the gate oxide thickness has come down to almost 1nm, i.e. a few atomic layers [1,2]. In such condition, electron tunneling effects through the dielectric lead to higher leakage current thereby posing serious challenge to device reliability. To circumvent this problem, alternative gate dielectric materials with higher dielectric constants are being considered to replace SiO2 to increase the equivalent oxide thickness (EOT). On the other hand, GaAs is emerging as a promising channel material for the futuristic high performance MOSFETs due to its lower effective mass and almost six times higher mobility compared to conventional Si [3]. Therefore a very high drive current and superior speed is expected to be achieved from GaAs-channel MOSFETs.

In the past ten years, significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. The deciding factors for selecting an appropriate gate dielectric is the band offsets at the interfaces with III-V substrate and with the metal gate. Now, it has been recognized that lanthanum oxide (La2O3) emerges as the leading candidate to replace SiO2 in advanced CMOS applications. It has several advantages over other oxide materials, such as high dielectric constant (~27), strongly insulating character with large band gap (~6 eV), large conduction band offset (~2.4 eV) with GaAs substrate and thermal stability [4].

The physical and chemical properties of the interface along with interfacial topography also play a crucial role in controlling the electrical characteristics of MOS devices [4, 5]. Both the dielectric and substrate/dielectric interface quality play a key role in the electrical performance of high mobility MOSFET devices [6]. Thus, it is challenging to make surface channel devices with GaAs as the channel material and La2O3 as gate dielectric. Fortunately, the chemical or physical deposition of high-k gate dielectrics of Al2O3, ZrO2, TiO2, and HfO2 on GaAs substrates with interface passivation layer (IPL) show promising results, which makes them viable as an insulator on this substrate [7, 8]. Despite some progress made, there is a continuous effort to improve the interface quality as well as gate dielectric quality to reduce the interface state density and frequency dispersion. The La2O3 is a very promising dielectric which has been studied mainly for Si- and Ge-based devices while there is considerably less work related to the properties of La2O3 deposited on GaAs substrates [9-11].

In the present work, we provide a systematic investigation of the dielectric quality of La2O3 and its interface properties with Si passivated p-GaAs as a function of post deposition annealing (PDA) conditions. The relevant process recipe for fabricating such devices is developed and simulated using SILVACO, a commercially available software package for process and device simulation. Following such process recipe, the La2O3 layer is deposited by employing RF sputter deposition technique. The electrical characterizations for studying the interface quality and quality of the deposited dielectric layer are performed by C-V and G-V measurements and diffusion of oxygen into the GaAs substrate. The distribution of interface state density is determined by simulating the C-V and G-V data.

II. PROCESS DESIGN AND MOS CAPACITOR FABRICATION

Prior to fabrication, the process recipe for MOS structures is simulated and optimized using SILVACO, a commercially available software package for process and device simulation.

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The key steps of the process recipe that has been followed in the current work are summarized in Fig. 1. Metal-oxide-semiconductor (MOS) capacitors were fabricated on Zn doped p-GaAs (100) with a carrier density of ~1×1016 cm-3. The wafers were degreased using isopropanol; the native oxides were removed by diluted 10% HCl etching for 3 min, and dipped in NH4OH for 5 min to remove elemental As. 12 nm thick La2O3 dielectric layer was deposited at room temperature by RF sputter deposition using La2O3 target and 80 W RF power in an Ar ambient at 3 mTorr working pressure. For some wafers, a thin layer of Si IPL was deposited by sputtering using Si target and 100 W RF power, prior to La2O3 deposition. Post deposition annealing (PDA) was carried out in N2 ambient at two different temperatures (400oC and 500oC) for 1 min by rapid thermal annealing (RTA). Thermally evaporated Al was used as the top gate electrode (area: 4×10-3 cm2). Low resistance ohmic back contact was made by using Ti/Pt/Au alloy on the back side of the wafers. The capacitance-voltage (C-V) characteristics were measured using an Agilent 4284A LCR meter.

Figure 1. Simulated process flow for the present sputter deposited La2O32/bulk-p-GaAs MOS structure.

III. RESULTS & DISCUSSION Fig. 2(a) shows the high-frequency (100 kHz) capacitance-voltage (C-V) characteristics of Al/La2O3/p-GaAs after PDA at 500oC and Al/La2O3/Si/p-GaAs MOS capacitors after post deposition annealing (PDA) at 400oC and 500oC. Improved C-V curve with saturated accumulation capacitance is observed for the La2O3/Si gate stack after PDA treatment compared to directly deposited La2O3 on p-GaAs, indicating better interface quality. The La2O3/Si gate stack capacitor shows higher accumulation capacitance (Cacc) of ~3.3 fF/μm2 compared to the directly deposited La2O3 capacitor (~1.5 fF/μm2) on p-GaAs. This indicates that the thin layer of Si on p-GaAs effectively decreases the formation of Ga and As oxides and suppresses the low-k interfacial layer growth, and leads to increase accumulation capacitance, which is similar to the

other high-k/Si/GaAs stacks [12-14]. For directly deposited La2O3 on p-GaAs the stretch-out ( C/ V) behavior of the C-V curves along the voltage axis indicates higher interface trap density (Dit) as shown in Fig. 2(b). It is observed that the Si passivation reduces the Dit and samples annealed at 500oC exhibit minimum stretch-out effect.

Figure. 2. (a) Experimental and simulated capacitance - voltage (C-V)

characteristics of the La2O3/p-GaAs gate stack with and without Si IPL; (b) experimental and simulated interface trap density distribution for the La2O3/p-

GaAs gate stack with and without Si IPL.

Fig.3 shows the frequency dispersion evaluated as Cox for devices with and without Si IPL as a function of PDA

temperature. MOS capacitors with Si IPL have shown much improved frequency dispersion (~11%) compared to the devices without IPL which exhibited frequency dispersion of almost 34%. This indicates that the Si IPL effectively passivates the GaAs surface. By increasing the PDA temperature, low frequency dispersion can be obtained. Samples annealed at 500oC exhibit minimum frequency dispersion (8%). This may be due to complete oxidation of the

Post deposition annealing (PDA) @ 400OC and 500OC

Zn-doped p-GaAs substrate (1x1016/c.c)

Surface cleaning

Removal of native oxides

Thin Si IPL deposition

La2O3 deposition at room temperature

Au electrode deposition by thermal evaporation

Low resistant back contact formation by TiPtAu alloy

Post deposition annealing (PDA) @ 400OC and 500OC

Zn-doped p-GaAs substrate (1x1016/c.c)

Surface cleaning

Removal of native oxides

Thin Si IPL deposition

La2O3 deposition at room temperature

Au electrode deposition by thermal evaporation

Low resistant back contact formation by TiPtAu alloy

0.8

1.5

2.3

3.0

-3 -2 -1 0 1 2 3

Gate voltage (V)C

apac

itanc

e (fF

/ μm

2 ) Without IPL-expWithout IPL-simAs Deposited-expAs deposited-simPDA 400-expPDA 400-SimPDA 500-expPDA 500-sim

(a)

1E+12

1E+13

1E+14

1E+15

0.4 0.6 0.8 1

Ec -Et (eV)

Dit

(cm

-2eV

-1)

Without IPL-expWithout IPL-simAs deposited-expAs deposited-simPDA 400-expPDA 400-simPDA 500-expPDA 500-sim

(b)

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1

10

100

1000

0 10 20 30 40 50 60 70

Depth (nm)

Inte

nsity

Without IPL

As deposited

PDA 400

PDA 500

Si IPL layer which reduces the charge trapping due to reduced thickness of highly trapped unoxidized Si layer [16].

W/O IPL ASD 400 5005101520253035

Freq

uenc

y di

sper

sion

(%)

Annealing temperature (OC)

Figure. 3 Frequency dispersion characteristics of La2O3/p-GaAs gate stack with and without Si IPL for different PDA temperature.

In order to understand the effect of GaAs substrate passivation using Si IPL, the diffusion of oxygen into the substrate at different PDA temperatures have been studied as shown in Fig. 4. Comparing the diffusion profiles for La2O3/ p-GaAs gate stack with and without Si IPL, it is observed that oxygen diffuses deeper into the GaAs substrate for samples without IPL. The effect of such diffusion has been noted in Fig. 3 where the frequency dispersion is higher for the samples without IPL. Moreover, annealing the samples with Si IPL reduces oxygen diffusion in comparison to the as- deposited samples with IPL, thereby reducing the frequency dispersion further.

Figure. 4 Diffusion of oxygen into the GaAs substrate of the La2O3/p-GaAs

gate stack with and without Si IPL at different PDA temperature.

IV. CONCLUSION It can be concluded that by using optimal PDA conditions of 500oC with Si IPL for La2O3/Si/p-GaAs gate stack, the

diffusion of oxygen reduces considerably and superior electrical characteristics in terms of low frequency dispersion (<8%) with higher oxide capacitances and lower interfacial state density (Dit) of ~1.2×1012 cm 2

eV 1 can be obtained which makes La2O3/Si gate stacks a potential candidate for GaAs based MOSFET devices.

ACKNOWLEDGEMENT Anindita Das would like to thank Department of Science & Technology (DST), India for providing the research (INSPIRE) fellowship

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