4
XL -RXIVREXMSREP 'SRJIVIRGI SR 'SQTYXIVW ERH (IZMGIW JSV 'SQQYRMGEXMSR '3()' )(1 -))) An Analytical Modeling of Interface Charge Induced Effects on Subthreshold Current and Subthreshold Swing of strained-Si (s-Si) on Silicon-Germinium-on- Insulator (SGOI) MOSFETs Mirgender Kumar, Sarvesh Dubey and S. Jit* Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, India *[email protected] Pramod Kumar Tiwari Department of Electronics and Communication Engineering National Institute of Technology Rourkela, India [email protected] Abstract—A surface potential based two-dimensional (2-D) analytical model for subthreshold current and subthreshold swing including the hot carrier induced interface charges effect of strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs is presented. The analytical model takes into account the effects of all device parameters along with Ge mole fraction in the relaxed Si 1-x Ge x layer, interface charge density and length of damaged region on subthreshold characteristics. For the validation of the proposed model, the model results are compared with numerical simulation results obtained from 2-D device simulator ATLAS by Silvaco. Keywords-Interface charges; subthreshold current; subthreshold swing; s-Si; SGOI I. INTRODUCTION Hot carrier degradation effect is becoming the major reliability concern in the present CMOS technology. These hot- carriers are resulted from the high electric fields in the channel near the drain junction, which subsequently are injected into the gate oxide and give rise to the pile-up of interface states and oxide charges on defect sites in the oxide. This pile-up of interface states severely degrades the short-channel effects by shifting the threshold voltage and decreasing the drive current efficiency of the device [1, 2]. Such hot carrier effects becomes more severe in strained channel MOSFETs due to high electron mobility and band-gap narrowing. Clearly, the reliability of performances of the short-channel strained-Si CMOS devices becomes significantly dependent on the interface state charges [3, 4]. Among all reported strained channel MOSFET structures, biaxial tensile strained-Si (s-Si) on Silicon- Germanium-on-Insulator (SGOI) MOSFETs are found to be of paramount importance for providing larger flexibility in controlling the uniformity of strain in the channel [5]. To control hot-carrier effects, Jin et al. [6] have incorporated the advantages of double material gate (DMG) structure in s-Si on SOI MOSFETs and also presented the 2-D channel potential and threshold voltage model for this device structure. However, no significant work is reported, to date, on the subthreshold current and subthreshold swing for an s-Si short-channel SGOI MOSFET incorporating hot-carrier degradation effects. It could be extremely important to take HCE induced effect on subthreshold current and swing, which are essential subthreshold scaling parameter. In this work, we have presented the modeling approach for subthreshold current and subthreshold swing of the s-Si on SGOI MOSFETs. The model includes the effects both type of the hot-carrier induced localized positive and negative interface charges and effect of the length of the damaged region caused by them. Moderately doped channel has been taken to avoid the degradation of carrier mobility. All the theoretical results are compared with the 2-D simulation results obtained by commercially available ATLAS TM [7] 2-D device simulator. II. DEVICE STRUCTURE A schematic cross sectional view of the device structure used for simulation of s-Si on SGOI MOSFET with localized charges is shown in Fig.1. A layer of silicon is assumed pseudomorphically grown on the relaxed Si 1-x Ge x layer, where x is the Ge mole fraction. It is assumed that the portion of length d L of the oxide, damaged by hot-carriers, and the undamaged region of length 1 L are laterally connected in a non-overlapping way. Further, the interface charge density in the damaged oxide region is assumed to be 2 cm f N . The symbols Si s t and SiGe t represent the thicknesses of the s-Si and Si 1-x Ge x layers respectively. Two different coordinate systems have been used in the 2-D structure of s-Si on SGOI MOSFET. The 0 = x axis runs along the body thickness direction whereas 0 and 0 = = y y axes are along the s- Si/SiO 2 and Si 1-x Ge x /buried oxide interfaces respectively. The introduction of strain in silicon channel causes changes in the device parameters like band structure, channel flat-band voltage, built-in voltage across the source–body and drain– body junctions. Therefore, the device simulator model library of ATLAS TM has been modified according to the effects of strain on Si band structure [8, 9].

[IEEE 2012 International Conference on Computers and Devices for Communication (CODEC) - Kolkata, India (2012.12.17-2012.12.19)] 2012 5th International Conference on Computers and

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Page 1: [IEEE 2012 International Conference on Computers and Devices for Communication (CODEC) - Kolkata, India (2012.12.17-2012.12.19)] 2012 5th International Conference on Computers and

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An Analytical Modeling of Interface Charge Induced Effects on Subthreshold Current and Subthreshold

Swing of strained-Si (s-Si) on Silicon-Germinium-on-Insulator (SGOI) MOSFETs

Mirgender Kumar, Sarvesh Dubey and S. Jit* Department of Electronics Engineering, Indian Institute of Technology (BHU),

Varanasi, India *[email protected]

Pramod Kumar Tiwari Department of Electronics and Communication Engineering

National Institute of Technology Rourkela, India

[email protected]

Abstract—A surface potential based two-dimensional (2-D) analytical model for subthreshold current and subthreshold swing including the hot carrier induced interface charges effect of strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs is presented. The analytical model takes into account the effects of all device parameters along with Ge mole fraction in the relaxed Si1-xGex layer, interface charge density and length of damaged region on subthreshold characteristics. For the validation of the proposed model, the model results are compared with numerical simulation results obtained from 2-D device simulator ATLAS by Silvaco.

Keywords-Interface charges; subthreshold current; subthreshold swing; s-Si; SGOI

I. INTRODUCTION Hot carrier degradation effect is becoming the major

reliability concern in the present CMOS technology. These hot-carriers are resulted from the high electric fields in the channel near the drain junction, which subsequently are injected into the gate oxide and give rise to the pile-up of interface states and oxide charges on defect sites in the oxide. This pile-up of interface states severely degrades the short-channel effects by shifting the threshold voltage and decreasing the drive current efficiency of the device [1, 2]. Such hot carrier effects becomes more severe in strained channel MOSFETs due to high electron mobility and band-gap narrowing. Clearly, the reliability of performances of the short-channel strained-Si CMOS devices becomes significantly dependent on the interface state charges [3, 4]. Among all reported strained channel MOSFET structures, biaxial tensile strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs are found to be of paramount importance for providing larger flexibility in controlling the uniformity of strain in the channel [5]. To control hot-carrier effects, Jin et al. [6] have incorporated the advantages of double material gate (DMG) structure in s-Si on SOI MOSFETs and also presented the 2-D channel potential and threshold voltage model for this device structure. However, no significant work is reported, to date, on the subthreshold current and subthreshold swing for an s-Si short-channel SGOI MOSFET incorporating hot-carrier degradation effects. It

could be extremely important to take HCE induced effect on subthreshold current and swing, which are essential subthreshold scaling parameter. In this work, we have presented the modeling approach for subthreshold current and subthreshold swing of the s-Si on SGOI MOSFETs. The model includes the effects both type of the hot-carrier induced localized positive and negative interface charges and effect of the length of the damaged region caused by them. Moderately doped channel has been taken to avoid the degradation of carrier mobility. All the theoretical results are compared with the 2-D simulation results obtained by commercially available ATLASTM [7] 2-D device simulator.

II. DEVICE STRUCTURE A schematic cross sectional view of the device structure

used for simulation of s-Si on SGOI MOSFET with localized charges is shown in Fig.1. A layer of silicon is assumed pseudomorphically grown on the relaxed Si1-xGex layer, where x is the Ge mole fraction. It is assumed that the portion of length dL of the oxide, damaged by hot-carriers, and the undamaged region of length 1L are laterally connected in a non-overlapping way. Further, the interface charge density in the damaged oxide region is assumed to be 2cm−

fN . The

symbols Sist − and SiGet represent the thicknesses of the s-Si and Si1-xGex layers respectively. Two different coordinate systems have been used in the 2-D structure of s-Si on SGOI MOSFET. The 0=x axis runs along the body thickness direction whereas 0and0 =′= yy axes are along the s-Si/SiO2 and Si1-xGex/buried oxide interfaces respectively. The introduction of strain in silicon channel causes changes in the device parameters like band structure, channel flat-band voltage, built-in voltage across the source–body and drain–body junctions. Therefore, the device simulator model library of ATLASTM has been modified according to the effects of strain on Si band structure [8, 9].

Page 2: [IEEE 2012 International Conference on Computers and Devices for Communication (CODEC) - Kolkata, India (2012.12.17-2012.12.19)] 2012 5th International Conference on Computers and

������������������������������XL�-RXIVREXMSREP�'SRJIVIRGI�SR�'SQTYXIVW�ERH�(IZMGIW�JSV�'SQQYRMGEXMSR��'3()' �������������������������������������������������������)(1

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Figure 1. Cross sectional view of s-Si on SGOI MOSFET with damaged region

III. ANALYTICAL MODEL

A. Surface Potentail Formulation The potential distribution across s-Si thin film and relaxed

Si1-xGex has been divided into four regions as shown in Fig. 1. The front (below the gate oxide) and back channel (above the buried oxide) potentials denoted by ),( yxiψ and ),( yxj ′ψ are obtained by solving the following respective 2D Poisson’s equations in the s-Si film of the device [10]:

( ) ( )SiGeSis

ajiji qNy

yxx

yx

,2

,2

2,

2 ,,

=∂

∂+

∂∂

εψψ

(1)

For Si1-xGex layer, y coordinate should be considered as y ′ . Subscripts denote the channel region as i stands for 1 and 2 whereas j stands for 3 and 4; q is the electronic charge; Sis−εand SiGeε are the dielectric constants of s-Si film and relaxed Si1-xGex layer respectively. Using the parabolic potential approximation, the channel potential in the s-Si and Si1-xGex layers can be approximated as [10]

221 )()()(),( yxCyxCxyx iisii ++= ψψ (2)

221 )()()(),( yxCyxCxyx jjbjj ′+′+=′ ψψ (3)

Here, for 2and1=i , 1sψ is the surface potential at the undamaged s-Si/SiO2 interface, 2sψ is the surface potential along damaged s-Si/SiO2 interface. Similarly, for 4and3=j ,

3bψ and 4bψ are the back-channel surface potentials at the Si1-xGex/buried oxide interface under undamaged and damaged regions respectively. The coefficients ( ) ( )4,32,1jiC in (2) & (3) are functions of x only and can be obtained by using the appropriate boundary conditions relating to potential and electric field continuity at different interfaces [9, 10].

Now, by substituting ),( yxiψ and ),( yxj ′ψ in (1) and then

putting 0=y and 0=′y in the resultant equations, we get

ibjisiisi xx

x

xγψβψα

ψ=+−

∂)()(

)(2

2

(4)

jsijbjjbj xxx

xγψβψα

ψ=+−

∂)()(

)(2

2

(5)

where, ( ) 221

22

SisSiGeSisSis

SisoxoxSiGeSisSiGe

tCCC

CCCCCC

−−−

−−

+

++== αα

( ) 2212

SisSiGeSis

bSiGe

tCC

CC

−− +

+== ββ

( )( ) 21

2

SisSiGeSisSis

subSisbGSSisSiGeox

Sis

a

tCCCVCCVCCCqN

−−−

−−

− +′−′+−=

εγ

( )( ) 22

2

SisSiGeSisSis

subSisbGSSisSiGeox

Sis

a

tCCC

VCCVCCCqN

−−−

−−

− +

′−′′+−=

εγ

( ) 24322

SiGeSiGeSisSis

SiGebbSisSisSiGe

tCCC

CCCCCC

+

++==

−−

−−αα

( ) 2432

SiGeSiGeSis

oxSis

tCC

CC

+

+==

−ββ

( )( ) 23

2

SiGeSiGeSisSiGe

GSSiGeoxsubSiGeSisb

SiGe

a

tCCCVCCVCCCqN

+′−′+−=

−ε

γ

( )( ) 24

2

SiGeSiGeSisSiGe

GSSiGeoxsubSisSiGeb

SiGe

a

tCCC

VCCVCCCqN

+

′′−′+−=

−ε

γ

where, GSV is the gate-to-source voltage, DSV is drain-to-

source voltage, bt is the buried oxide thickness, oxε is the

dielectric constant of the gate oxide and ft is the front gate

oxide thickness; GSV ′ , GSV ′′ and subV ′ , oxC , SisC − , SiGeC , bC can be calculated as in [11]. Rearranging the terms involved in (13) and (14) and neglecting higher order terms, we get the following second order differential equation for the front surface potential )(xsiψ as

isisi QxP

x

x=−

∂)(

)(2

ψ (6)

where,21

2121αα

ββαα+−=P ,

21

31121 αα

γβγα++=Q ,

21

41222 αα

γβγα++=Q

On solving (6) with the help of suitable boundary conditions, the final expression of surface potential can be written as

( ) ( ) 1111 expexp σλλψ −−+= xBxAs (7)

( )( ) ( )( ) 212122 expexp σλλψ −−−+−= LxBLxAs (8)

where, P=λ , PQ /11 =σ , pQ /22 =σ ( ) ( )( ) ( ) ( )( )

( )L

VLLVB DSdSisbi

λλσσλσ

sinh2cosh11exp 121,

1−−−−−−

= −,

Page 3: [IEEE 2012 International Conference on Computers and Devices for Communication (CODEC) - Kolkata, India (2012.12.17-2012.12.19)] 2012 5th International Conference on Computers and

������������������������������XL�-RXIVREXMSREP�'SRJIVIRGI�SR�'SQTYXIVW�ERH�(IZMGIW�JSV�'SQQYRMGEXMSR��'3()' �������������������������������������������������������)(1

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11,1 BVA Sisbi −+= − σ ( ) ( ) 2/exp 12112 σσλ −+= LAA , ( ) ( ) 2/exp 12112 σσλ −+−= LBB

The position ( )( )min,21x of the minimum surface potential for both negative and positive interface charges under the undamaged and damaged regions respectively can be determined by solving ( )

( )

0min,21

21 ==xx

s

dxdψ and be given as

( ) λ2ln 11min,1 ABx = and ( ) λ2ln 221min,2 ABLx += On substituting the values of the minima position into (7) and (8), the minimum surface potentials can be expressed

111min,1 2 σψ −= BAs (9)

( ) 2122min,2 cosh2 σλψ −= LBAs (10)

B. Subthreshold Current Fourmulation The subthreshold current is mainly dominated by the diffusion phenomenon and proportional to carrier concentration at the minimum channel potential position. By employing the thus obtained 2-D channel potential model and following the methodology as used in [12], the expression of subthreshold current can be written as follows:

=

−−

0min, )(

exp

SistT

is dy

V

yKI

ψ (12)

−−=T

ds

ae

inVV

NLnqD

K exp12

where, nD is the diffusion coefficient, eL is the effective channel length. Potential function )(min, yiψ can be found from (2) by substituting the position of minimum surface potential

( )( )min,21x . By integrating (12), we get the following expression for subthreshold current:

−−

= −

T

i

T

Sisi

f

Ts V

yV

tE

KVI

)(exp

)(exp minmin,min, ψψ (13)

( ) mmiSisif yytE /)()( min,min, ψψ −−= −

By substituting the value of )(min, mi yψ , )(min, Sisi t −−ψ in (13), we may get the separate expression of subthreshold currents for positive and negative interface charges. my is the minima position in vertical direction which can be calculated from the methodology used in [12].

C. Subthreshold Swing Fourmulation The subthreshold swing (S) can be stated as [13]

( )1

min, )(10ln

∂∂

=gs

iT V

yVS

ψ (14)

By substituting the derivative of )(min, yiψ with respect to

GSV in (14) for both positive and negative interface charges, we can obtain the simplified expression for subthreshold swing.

IV. RESULTS AND DISCUSSION In this section, we will discuss and compare the results, obtained from numerical simulation and the proposed analytical model for the hot carrier induced effect on subthreshold current and swing of s-Si on SGOI MOSFET. Fig. 2 shows the subthreshold current variation against VGS obtained from our model as well as from the simulation for different interface charge densities generated by both type of hot carriers at fix damaged region length. It is observed that for fixed values of VGS and VDS, the off-state leakage current (Ioff) is increased with the increase in positive interface charge density in comparison of fresh device (Nf=0) due to lowering in the source/body barrier height. However, Ioff is decreased with the increase in negative interface charge density because of increase in the source/body barrier height. Fig. 3 explains the subthreshold current variation with VGS for different damaged region lengths at fix positive as well as negative interface charge density. Clearly, the off-state leakage current (Ioff) is increased by increasing the damaged region length for the positive interface charges but reduces for the negative interface charges. Fig. 4 plots the subthreshold swing (S) variation with channel length for different interface charges keeping all other device parameters constant. It is found that S increases with the increment of positive interface charges and decreases for negative interface charges. Fig. 5 plots the subthreshold swing (S) variation with channel length for different damaged region lengths keeping other device parameters constant. It illustrates that S increases with the increase in positive interface charge induced damaged length. However, S decreases with the increase in negative interface charge damaged region length along with the similar effect of channel length on S like Fig. 4. The rate of variation of S in case of positive interface charges is found quite higher compared to the negative interface charge density.

Figure 2. Subthreshold current versus gate to source voltage at different Nf

Page 4: [IEEE 2012 International Conference on Computers and Devices for Communication (CODEC) - Kolkata, India (2012.12.17-2012.12.19)] 2012 5th International Conference on Computers and

������������������������������XL�-RXIVREXMSREP�'SRJIVIRGI�SR�'SQTYXIVW�ERH�(IZMGIW�JSV�'SQQYRMGEXMSR��'3()' �������������������������������������������������������)(1

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Figure 3. Subthreshold current versus gate to source voltage for different

damaged region length

Figure 4. Subthreshold swing versus channel length at different Nf

Figure 5. Subthreshold swing versus channel length for different damaged

region length

V. Conclusion

In this paper, a short-channel surface potential based model of subthreshold current and swing including hot carriers induced positive and negative interface charges has been derived for the s-Si on SGOI MOSFETs. The source/drain-channel barrier is found to be a function of interface charge density as well as of damaged region length. The subthreshold current and swing is observed to be decreased with the increase in the negative interface charge density and length of damaged region as well, however, increases with positive interface charge density and length of damaged region. The proposed model is verified by comparing the theoretical results with the simulation data obtained by using the commercially available ATLASTM device simulation software from Silvaco.

REFERENCES [1] E. G. Ioannidis, A. Tsormpatzoglou, D. H. Tassis et al, Effect of

Localized Interface Charge on the Threshold Voltage of Short-Channel Undoped Symmetrical Double-Gate MOSFETs, IEEE Trans. Electron Devices, vol. 58, no. 2, pp. 433-440 Feb 2011.

[2] T. Bentrica, F. Djeffal and A. H. Benhaya, Continous Analytic I-V Model for GS DG MOSFETs Including Hot Carrier Degadation Effects, Journal of semiconductors, Vol. 33, No. 1, 014001, 2012.

[3] P. S. Jack, J.-Y. Kuo, “On the Enhanced Impact Ionization in Uniaxial Strained p-MOSFETs,” IEEE Electron Dev. Lett, vol. 28, no. 7, pp. 649-52, 2007.

[4] D.Q. Kelly, S. Dey, D. Onsongo, S.K. Banerjee, Considerations for evaluating hot-electron reliability of strained Si n-channel MOSFETs, Microelectronics Reliability 45 (2005) 1033 1040.

[5] F. Gamiz, P. C. Cassinello, J. B. Roldan, and F. J. Molinos, Electron transport in strained Si inversion layers grown on SiGe-on-insulator substrates, J. Appl. Phys., vol. 92, no. 1, pp. 288–295, Jul. 2002.

[6] L. Jin , L. Hongxia, L. Bin, C. Lei., and Y. Bo, “Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs,” J. Semiconductors, vol. 31, no. 8, pp. 084008, 2010.

[7] ATLAS Users Manual, Silvaco International, santra clara, CA, 2008 [8] T. Numata, T. Mizuno, T. Tezuka, J. Koga, and S. Takagi, “Control of

threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices,” IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1780– 1786, Aug. 2005.

[9] J. S. Lim, S. E. Thompson, and J. G. Fossum, “Comparison of threshold voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs,” IEEE Electron Device Lett., vol. 25, no. 11, pp. 731–733, Nov. 2004.

[10] K. K. Young, “Short-channel effect in fully depleted SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399–402, Feb. 1989.

[11] V. Venkataraman, S. Naval and M. J. Kumar, Copmact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon-Germanium-on-Insulator Mosfets, IEEE Trans Electron Devices, vol. 54, pp. 554-562 ,2007.

[12] Sarvesh Dubey, Pramod Kumar Tiwari, and S. Jit, A Two-Dimensional Model for the Surface Potential andSubthreshold Current of Doped Double-Gate (DG) MOSFETs with a Vertical Gaussian-Like Doping Profile, Journal of Nanoelectronics and Optoelectronics, Vol. 5, 1–8, 2010.

[13] Sarvesh Dubey, Pramod Kumar Tiwari, and S. Jit, A two-dimensional model for the subthreshold swing of short-channel double-gate metal–oxide–semiconductor field effect transistors with a vertical Gaussian-like doping profile, J. Appl. Phys. 109, 054508 (2011).