PSO-based charge pump chip area minimization

Frederic Alicalapa, Jean Daniel Lan Sun Luk LE2P Lab,

University of La Reunion Saint Denis, Reunion (France)

frederic.alicalapa@univ-reunion.fr, lanson@univ-reunion.fr

Rahma Aloulou, Hassene Mnif, Mourad Loulou LETI Lab,

University of Sfax, Tunisia. hassene.mnif@ieee.org, aloulourahma@yahoo.fr,

mourad.loulou@ieee.org

Abstract— In this paper a solution of the well-known silicon area/performance dilemma and an energy harvesting circuit for wireless sensor nodes are presented. A PSO-based integrated circuit area optimization methodology is proposed. The study is performed on a charge pump circuit, using a 0.35µm Si-CMOS process. The PSO sizing strategy has been implemented using a Spice kernel and Matlab environment. The chip size has been reduced from 583µm² to 179µm² after the optimization process. Simulation results from the 0.35μm parameters are given. When driving a capacitive load of 50pF, the output-generated voltage is 4V from a 1.3V input voltage. The simulated pumping gain is 3.1.

I. INTRODUCTION IC size is one of the most important characteristics for the

chip economic impact. Furthermore smaller dies usually consume less energy and run faster. Thus, for circuit designers, chip area should be considered as premium real estate. Computer-aided design (CAD) tools and optimization algorithms can be combined to meet the circuit performances as in [1]. In this paper, we are mainly interested in exploring a circuit area reduction using a PSO stochastic optimization algorithm while generating the maximum output voltage of a charge pump (CP) circuit. The circuit under consideration, a CMOS CP, was introduced by J.T. Wu [2]. In addition, CP circuits can be used to extend battery lifetime of wireless sensor networks. Battery life extension or autonomous circuit operation are highly desirable. Alternative power sources could be considered in conjunction with reduction of power consumption. In this context of autonomous energy operation, a promising approach is the use of low energy scavenging circuit. Using energy extracted from the environment is really attractive. This energy can be extracted from low power sources (Passive human-powered systems, thermal, vibrations, solar ray, electromagnetic waves…) using CP circuits. In this context, CP circuits are important blocks. Indeed, CPs were introduced to generate high voltages from lower voltages [3, 4, 5]. The study is performed using 0.35µm CMOS process parameters, Spice kernel and the Matlab environment.

A review of the basic CP structures and their operation will be given in order to understand the charge pumping phenomena. Throughout this review, information will be given on CP circuits main parameters: number of stages,

coupling capacitors values, input voltage and supply voltage value and MOS transistors as switches. The PSO convex and regularized criterion will be described in section III and information on the algorithm and its implementation using Matlab software and a Spice kernel will be presented. Finally Spectre simulation results will be given for comparison in section IV.

II. CHARGE PUMP CIRCUITS A. Basic concept and operation

CPs are circuits that generate a voltage higher than the supply voltage. Historically, the first integrated CP topology was proposed by J.F. Dickson (see Fig. 1) using diode connected MOSFETs and capacitors implementation [3]. The chip area was approximately 600μm*240μm. Using a supply voltage (Vin) of 14V, and a 10 MΩ-10 pF load, the measured output voltage was in the range of 27.2V to 39.1V. Charges are transferred from stage to stage through the seven stages in this case. The charge transfer is done in one direction, from the left coupling capacitor (charge storage element) to the right output capacitor (Cload), through controlled switches [6].

Figure 1. Dickson charge pump structure.

Figure 2. NCP2 circuit.

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B. Integrated charge pump Most MOS CPs are based on the circuit proposed by

Dickson [3] (see Fig. 1). Dickson has discussed the CP operation in steady state when the output voltage is limited to a constant voltage. In steady state, the charge transferred from one capacitor to the next one just equals the charge transferred to the output [7]. For this structure, the output voltage is given by:

Vout = Vin + N Vclk −Vtn( )−Vtn (1)

Where Vin the input voltage, Vtn is the MOS threshold voltage, N is the number of stages and Vclk is the voltage amplitude of the clock signal.

In the literature, some drawbacks have been identified: the successive increase of the voltage on internal nodes causes an increase between the substrate and the sources of NMOS transistors and consequently an increase in the threshold voltage of each transistor, due to the body effect. This results in degradation in the output voltage as expressed by (1).

Thus, new circuit developments have been introduced in order to overcome the aforementioned limitation. Many solutions have envisaged such as the use of transistors with zero threshold voltage or the achievement of individual wells to separate the substrates of transistors N. Although the solutions already mentioned lead to good results, we find that additional costs are added and technological complexity of the process is encountered. To remedy this problem, instead of using the diodes to direct the flow of charges in pumping operation, dynamic charge transfer switches (CTS) with proper on/off cycles, have been used to realize the CPs and show better voltage pumping gain than the diodes. This structure called NCP2 by J.T. Wu [2] is illustrated in figure 2. This structure was also selected for the cancellation of the reverse charge sharing phenomena: which can be viewed as a backward control of the previous stage. Auxiliary-switch chain transistors MS1-MS3, which are connected in parallel to the main MOS-diode switch chain, are used to transfer loads unidirectionally, from one node to another circuit. The idea is to use the high voltage supply in the output node of stage (i+1) for controlling the gate voltage of transistor MSi in the stage (i) to cancel the voltage drop due to the threshold voltage of transistor MDi. The added inverters (MNi, MPi) are used to assure complete turn-off of the transistor MSi and prevent reverse transfer of charges. In fact, this smart voltage schemes, for the gate control of auxiliary-switch, are developed to close the reverse conduction path correctly.

Therefore the problem of body effect is avoided and the charge pump offers excellent performance. A comparison between the output voltages of the two 3-stages structures is given in figure 3 using the initial parameters summarized in table 1. Simulations are performed using 0.35 μm CMOS process parameters and Spectre simulator. Figure 3 shows that the NCP2 circuit gives an improvement of the gain with a factor of 1.55 in comparison with the Dickson structure. From this figure and the proper control of the CTS, it is obvious that the NCP2 structure leads to good results. However additional transistors are used leading to an increased silicon area. For this reason we are interested in the following paragraph in

reducing the circuit size of a NCP2 CP. Again from figure 3, another fundamental point is that, the 55% increase in the output voltage, is only due to the proper transistors control. Thus, these components should be carefully optimized so as to have the correct turn-on and turn-off time to maximize the output voltage.

Table 1. Initial charge pump sizing.

Wn (MDi) = W(MNi) = Wn 150 µm

W(MSi) = Wn / 2 75 µm

W(MPi) 5 µm

Cload 50 pF

Coupling capacitors (Ci) 100 pF

Clocks Frequency 10 MHz

Vclk = Vin 1.3 V

Figure 3. Ouput voltages comparison, 3-stages, Vin = 1.3V.

III. CHARGE PUMP OPTIMIZATION The IC size is mainly dependent on the capacitors value

and the transistors size. In order to decrease the chip area, we propose to use the Particle Swarm Optimization (PSO) techniques on a 3-stages charge pump (as to generate an output voltage in the range of 1V-4V). From the initial CP by J.T. Wu [2], the challenge is how to maximize the output voltage for a fixed input voltage and clock frequency. The coupling capacitors and the output capacitor values are fixed in order to reduce the number of parameters.

A. Particle Swarm Optimization PSO belongs to the broad class of stochastic optimization

algorithms. It was developed and first introduced by Kennedy and Eberhart [8]. It simulates the social behavior of a population (swarm) by local and global information exchange between each individual (particle) in order to minimize a goal. The particle is characterized by it’s coordinate X in an n-dimensional metric space. The ith particle is an n-dimensional vector: Xi = (xi1,xi2,…,xin)T, where xik represents a parameter to optimize in our circuit. The velocity of this particle is also an n-dimensional vector : Vi = (vi1,vi2,…,vin)T. The swarm evolution is governing by the following rules equations:

Vi(t+1) = w.Vi(t) + c1.r1 (Pi(t)-Xi(t)) + c2.r2 (Pg(t)-Xi(t)) (2)

Xi(t+1) = Xi(t) + Vi(t+1) (3)

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where i =1,2,… N, w is a parameter called the inertia weight, c1 and c2 are positive constants, referred to as cognitive and social parameters, respectively, and r1, r2 are random numbers, uniformly distributed on the interval (0,1). N is the size of the population and t = 1,2,…,Nt is the iteration number. Pi(t) is the best position at the iteration t of the algorithm of the ith particle (local). Pg(t) is the best position at the iteration t among all the particle in the swarm (global). The algorithm is stopped when the limit number of iteration Nt is reached or the precision for the criterion is satisfied.

B. CPs : device parameters selection and algorithm If we consider that the IC sized is governed by the physical

transistor dimensions, we can select the device parameter to optimize. From figure 2 and Table 1, we select the W_k and L_k for six different kinds of transistors (MDi, MSi, MNi, MPi, MDout, MD4). Thus we have 12 parameters in each particle, Xi=(W_MDi, L_MDi, W_MDout, L_MDout, W_MSi, L_MSi, W_MNi, L_MNi, W_MPi, L_MPi, W_MD4, L_MD4) to optimize with the PSO Algorithm.

Now we must define the criterion to minimize. For an efficient CP, we would like to have in the steady state the maximum output voltage (Vout) for a fixed input voltage (Vin), with the minimum power consumption. To minimize the chip area, we need to find the minimum dimensions for these transistors. We can translate theses constraints in a mathematical convex and regularized criterion:

2 222 2

1( ) (4)

1i out in i

out

in

J X P P XVV

α δ γ= − + +⎛ ⎞

+ ⎜ ⎟⎝ ⎠

The quantities α, δ and γ are constants that we must fix after some tests. They are the regularized parameters that enable us to make a tradeoff between our knowledge and a priori information about our device function.

We consider that the clock frequency is constant and equal to 10 MHz as in [2]. The output capacitor Cload is 50pF and the coupling capacitor (Ci) is 100 pF.

C. Algorithm implementation and Optimized sizes. The algorithm was implemented under Matlab’s platform

(see Fig. 4). We have developed an interface to create the appropriate netlist for a SPICE kernel and to translate the results of the simulation in vector data type. In order to calculate the criterion for a fixed parameters vector (Xi) at each iteration of the PSO algorithm, we need to calculate the circuit’s performances (Vin, Vout, Pin, Pout) with a transient simulation under SPICE’s kernel. We integrate over 100 clock’s period these signals to obtain the steady state values.

After 5000 iterations, we obtain the optimized transistors parameters presented in Table 2. Additionally, the chip size has been reduced from 582.8µm² to 179.1µm². We have 70% size reduction (only considering transistors area and neglecting metal paths area). The optimized circuit will be identified as NCP2optim.

Figure 4. Implemented PSO algorithm interfaced with SPICE kernel.

IV. SIMULATION RESULTS NCP2 circuit and NCP2optim circuit are now logically

compared using Spectre simulator (for future chip realization).

A. Output voltages comparison The first basic comparison can be performed on Vout

using Vin = 1.3V and Cload = 50pF. The performances of the circuits (see Fig. 5) are quite the same in the steady state, but we observe a delay (40 μs). In steady state, NCP2optim exhibits a greater output voltage.

Table 2 : Initial and optimized transistor dimensions.

Transistors name

Initial transistors

size

Transistor area

Optimized circuit

Optimized transistor

area

NMOS MDi

W_MDi 150µm 4*

52.5µm²

10.1µm 4* 37.9µm² L_MDi

0.35µm 3.75µm

NMOS MSi

W_MSi 75µm 4*

26.25µm²

6.88µm 4* 2.4µm² L_MSi

0.35µm 0.35µm

NMOS MNi

W_MNi 150µm 3*

52.5µm²

6.35µm 3* 2.2µm² L_MNi

0.35µm 1.45µm

PMOS MPi

W_MPi 5µm 3*

1.75µm²

3.5µm 3* 1.4µm² L_MPi

0.35µm 0.4µm

NMOS MD4

W_MD4 150µm 1*

52.5µm²

4.9µm 4.9µm² L_MD4

0.35µm 1.0µm

NMOS MDout

W_MDout 150µm 1*

52.5µm²

5.4µm 2.2µm² L_MDout

0.35µm 0.4µm

Total 582.8µm² 179.1µm²

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Figure 5. Ouput voltage comparison, 3-stages, Cload = 50pF, Vin = 1.3V.

B. Load value influence In some cases the load impedance could be purely

capacitive (Cload). This is an ideal case for which the output voltage remains constant after a small number of clock period. But generally a resistive load (Rload) should also be considered as the electronic driven circuits.

C. Cload output capacitor influence As Cload capacitor has a great impact on the chip area, its

value should be chosen carefully (in this study coupling capacitors have fixed values). As the value of the output capacitance increases, the value of the settle time increases and the output voltage is logically lowered as depicted in the following figure. These Spectre simulation results are given for a pure capacitive load (see Fig. 6).

Figure 6. Ouput voltage as a function of the output capacitor value (Cload),

3-stages, Vin = 1.3V

For the whole range, NCP2optim demonstrates a better output voltage pumping gain.

D. Rload output resistor influence We now should consider different resistive load values in

order to evaluate the driving capability of NCP2optim circuit. This will be performed with Cload = 50pF. The corresponding output voltages are also given. The output pumping voltage is lowered for large output current (see Fig. 7).

Figure 7. Average output current in steady state region, NCP2OPTIM

Additionally from simulation results, compared to NCP2, the NCP2optim average output current and voltage are quite the same for high resistor values. But for low values, NCP2 exhibits better performance (considering NCP2 , Cload = 50 pF and Rload = 10 kΩ, Iout=288 μA, Vout=2.8V).

V. CONCLUSIONS AND PROSPECTS We have shown that a simulation-based PSO optimization

algorithm can help us to decrease a circuit area under voltage constraint. This technique was applied to a CP circuit and the transistors sizing, while maximizing the output voltage. By using a regularized criterion the size reduction is 70% and we can slightly increase the performance of our initial pump charge: pumping gain is 3.1, considering an input voltage of 1.3V, a fixed clock frequency of 10 MHz and the same capacitor values. Although the overall performance was better, it should be noted that some exceptions appear (the value of the output current for low load resistive value). In order to broaden the size reduction procedure, researches should include coupling capacitors sizing, output current value and the clock characteristics in our multi-criterion.

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Analog circuit optimization system based on hybrid evolutionary algorithms, Integration, the VLSI Journal, Volume 42, Issue 2, February 2009, Pages 137-148, ISSN 0167-9260.

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[3] J. Dickson, “On-chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique.” IEEE Journal of Solid-State Circuits, Vol. 11, No. 6, pp. 374–378, June 1976.

[4] J. Tsujimoto, “Charge pump circuit having a boosted output signal,” U.S. Patent 4935644, June 1990.

[5] J. S. Witters, G. Groeseneken, and H. E. Maes, “Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits,” IEEE J. Solid-State Circuits, vol. 24, pp. 1372–1380, Oct. 1989.

[6] J.-T. Wu, Y.-H. Chang, and K.-L. Chang, “1.2 V CMOS switched-capacitor circuits,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech.Papers, Feb. 1996, pp. 388–389.

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