The “Buffering” Role of High-κ in Post Breakdown Degradation Immunity of Advanced Dual Layer

Dielectric Gate Stacks

N. Raghavan1, ♣, A. Padovani2, X. Wu3, K. Shubhakar3, M. Bosman4, L. Larcher2 and K.L. Pey3 1Division of Microelectronics, School of EEE, Nanyang Technological University (NTU), Singapore – 639 798.

2Dipartimento di Scienze e Metodi dell'Ingegneria, Università di Modena e Reggio Emilia, Italy. 3Singapore University of Technology and Design (SUTD), Singapore – 138 682.

4Institute of Materials Research and Engineering (IMRE), A*STAR, 3 Research Link, Singapore – 117 602. ♣Ph: (+65) 9862 1185, E-mail: naga0009@ntu.edu.sg

Abstract — Post breakdown (BD) reliability is an important area of study in ultra-thin gate dielectrics as it has significant implications on the performance degradation, lifetime, reliability margin and power dissipation of advanced sub-22 nm transistors and circuits. A prolonged phase of post-BD can ensure we can live with the circuit with moderate performance and error-free operation, even if the soft breakdown (SBD) events occur early. While analysis of post-BD is simple and straightforward for single layer SiO2 / SiON stacks, the number of possible scenarios of post-BD increases when analyzing high-κ – interfacial layer (HK-IL) based technology. This is because the sequence of BD (whether HK or IL fails first followed by the other one) and the competition between multiple SBD in one of these layers, dilative wear-out of a single SBD spot and the possibility of a successive localized BD above / below the HK/IL BD percolation spot (with or without metal filamentation) are all possible phenomena that can be classified as post-BD. The likelihood of occurrence of these various possibilities will determine the immunity of the stack to post-BD degradation. We will investigate each of these scenarios in detail in this work in order to provide a comprehensive assessment of post-BD reliability of state-of-the-art technology. Our analysis on a HK:IL = 25:12Ǻ stack supported by electrical, physical and modeling results provides clear evidence that circuit failure at operating conditions can only be due to multiple SBD events within the IL layer and that the HK is very robust and resilient to breakdown.

Keywords – Filamentation, Percolation, Post breakdown, Soft breakdown, Thermochemical maodel, Trap generation, Wear-out.

I. INTRODUCTION Breakdown in ultra-thin dielectrics is typically considered to

comprise two stages – (a) soft breakdown (SBD) and (b) post breakdown (post-BD) [1] – [6]. The phase of post-BD may in itself include various degradation mechanisms depending on the dielectric and gate material [7]. Some of these include digital and analog wear-out of the percolation path [8], metal filamentation (Ni, Ta-based gates) [9, 10], dielectric breakdown induced epitaxy (DBIE) [11] and migration of contact metal from the source / drain ends into the channel causing a short [12, 13]. Although SBD and post-BD are phenomena that have been extensively studied both from a statistical viewpoint [14] – [16] and electrical / physical analysis perspective [17] – [19]

for SiO2/SiON and HK-IL stacks, the key limitation is that in most cases, the algorithm used to accelerate the breakdown is unable to accurately capture the transient between the percolation event and the post-BD phase, where we observe the physical morphological changes in the dielectric at the BD spot. This is due to poor compliance control. More so, this is the case for HK-IL stacks, wherein most time dependent dielectric breakdown (TDDB) tests are initiated at test conditions that lead to the instantaneous breakdown of the second layer (HK/IL) (due to excessive localized ξ-field beyond the critical field value of the dielectric), once the first dielectric (IL/HK) exhibits a percolation event. As a result, most post-BD studies in the past were only able to assess the “wear-out” stage of the “fully percolated” stack, which is just one of the many possible scenarios that a HK-IL stack can encounter. Considering this incomplete picture of post-BD, our motivation in this study is to contribute to fill the gap in the post-BD understanding using careful electrical, statistical and modeling results that can more accurately study the defect generation kinetics causing breakdown.

The layout of this paper is as follows. In Section II, we first clarify the breakdown sequence in HK-IL stacks by presenting a statistical comparison of the TDDB data for HfSiON-SiOx and SiON stacks using the thermochemical model [20]. Up to now, the sequence of breakdown has remained a mystery with contradicting results and no unified understanding to leverage on. While some groups suggest HK to be the first to breakdown [21] – [23], others indicate IL to be the weakest link [24] – [30]. Without having a universal understanding on the breakdown sequence, it is difficult to proceed further in analyzing the post-BD phase of degradation. Once the breakdown sequence is deciphered, we illustrate and discuss the four possible scenarios that one may encounter for post-BD in HK-IL stacks in Section III. We will then present a detailed analysis of these four scenarios in Section IV using statistical, modeling and physical analysis results. Finally, we conclude our study highlighting the key findings and recommending topics for further in-depth scientific investigations. In our analysis, we emphasize on the need to model and simulate the degradation kinetics at nominal operating conditions of Vg = Vop = 1V.

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II. BREAKDOWN SEQUENCE FOR DUAL LAYER STACK For all electrical measurements, the devices tested have an

area of W × L = 1 × 0.13 µm2 with 25Ǻ HfSiON and 12Ǻ SiOx bi-layer stack. Fig. 1 shows the Weibull plot of the time to failure (TTF) for this stack at constant voltage stress, setting a very low compliance of Igl ~ 0.7μA, corresponding to a SBD percolation event (as verified by I-V sweeps after these tests).

Figure 1. Statistical plot of the TDDB failure time for the HK/IL stack with accelerated stress voltages and very low compliance capping of 0.5-0.7μA, enabling only one layer to break down. The stack tested is NiSi (FUSI) - HfSiON(25Ǻ) - SiOx(12Ǻ) - Si.

The above TTF data are used to derive the field-free activation energy (Ea) and field acceleration parameter (b) of the defect generation process for this BD event using the thermochemical model presented in Ref. [31]. Though various other models have been proposed to explain breakdown [32, 33], we believe the thermochemical description is the most suitable, given the physical analysis evidence of oxygen vacancies [34] in the percolated dielectric that requires Hf-O / Si-O bond breaking. The procedure for extracting the {Ea, b} parameters is briefly described below. Considering the standard expression for the rate of bond breaking (G), expressed as in Eqn. (1), where G0, kB and T are the proportionality factor, Boltzmann constant and temperature respectively, we take the logarithmic form to derive the effective field-lowered activation energy (Ea-EFF) in Eqn. (2). Assuming that G and mean TDDB lifetime (ηTDDB) are related by an inverse linear relationship (as verified by means of simulations) with a proportionality factor of 1, the final expression in Eqn. (2) may be used to calculate Ea-EFF from the measured TTF data distribution at different constant voltage stress conditions.

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lnTkGGlnTkE

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Using the above model, we plot the trend of Ea-EFF on ξ-field in Fig. 2. It is interesting to note that the extracted Ea-HK-IL (2.38eV) and bHK-IL (11.1eǺ) agree very well with the values derived from TTF experiments on a 16Å-thick SiON layer (Ea-

SiON = 2.69eV; bSiON =11.4eǺ ~ bHK-IL). The similarity in the {Ea, b} values for these two stacks indicates that the same

dielectric material must have been subjected to the formation of a percolation path. This suggests that the IL (SiOx) is the first layer to breakdown. Take note however that the findings here may be different depending on the underlying physical model considered for trap generation.

Figure 2. Extraction of the effective activation energy for defect generation from the TDDB test data for (a) pure-SiON (16Ǻ) and (b) HK/IL stack with 12Ǻ SiOx (based on data in Fig.1). The extracted Ea is much lower than ∼4 eV which is the standard activation barrier for Hf-based dielectric stacks [30, 35]. Moreover, the value of Ea is lower for IL as compared to SiON by about 0.3eV due to the slight sub-stoichiometry and the defective “trappy” nature of the IL induced during the fabrication process by the overlying HK layer [24].

Figure 3. Scatter plot of the ratio of trap generation rate in the IL and HK layers for various combinations of HK and IL thickness in the stack at Vg = Vop = 1V. For any arbitrary realistic thickness ratio (tHK : tIL), we observe TGRIL >> TGRHK. Even the minimum value for very thin bi-layer stacks is of two orders of magnitude suggesting that the general trend of faster defect evolution in IL is independent of the thickness combination at Vop = 1V.

We further verify the IL BD inference by considering the thermochemical trap generation rates (TGR) for the HK and IL layers (Eqn. 1). The TGR ratio (TGRIL/TGRHK) (Fig. 3) calculated for different HK:IL thickness combinations shows

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Figure 4. Possible evolution of trap configuration as obtained from simulations performed with a Kinetic Monte Carlo degradation/BD construct [35] at four consecutive stages – (a) initial time zero with defects predominantly in the HK (blue cylinder representing grain boundary), (b) after first SBD event in the dielectric stack (BD occurs in IL) and (c, d) subsequent continued stress and trap evolution spectroscopy at Vop = 1V for a very long stress of 1 × 106 and 3 × 106 sec respectively. Even with initially higher defect density in the HK, the first BD is still prone to occur in the IL layer, owing to the many orders higher TGR (weaker Si-O bonds). (e-h), (i – l) Corresponding oxygen stoichiometry (SiOx , x Є [0, 2]) 3D and 2D plots (plane cut across IL) for the four different stages of degradation. Multiple IL SBD spots are observed for long duration while the initial SBD spot shows some moderate degree of wear-out and dilation. The effect of multiple SBD spot evolution on circuit level leakage current is expected to be more dominant also because of the additional SBD spots generated in correspondence to the other GBs (not shown in the small area simulated here).

that TGRIL >> TGRHK due to the much larger activation energy of the high-κ materials (Ea-HK = 4.4eV [35, 36]). Figs. 4(a, b, e, f, i, j) illustrate the initial and final trap configurations and IL stoichiometry as obtained from the simulation of a SBD experiment (CVS at 3.3V; Igl = 0.7μA) performed with the Kinetic Monte Carlo degradation/BD model in [35]. The model is powerful as it describes consistently the electron charge-transport, the power dissipation, the local temperature increase and field- and temperature-induced defect generation process [35]. It is worth noting that most of the traps are generated in the IL layer in spite of considering a defective HK (grain boundary, GB) at the beginning of the degradation simulation, indicating again that the IL is the first layer to breakdown.

III. THE FOUR SCENARIOS OF HIGH-Κ POST BREADKDOWN Having ascertained the breakdown sequence using electrical

measurements and Monte Carlo modeling, it is clear that the post-BD phase can involve four possible scenarios and/or a combination of them. Fig. 5 illustrates these scenarios in detail

with yellow-red and green dots representing pre-SBD and post-SBD traps (oxygen vacancies). Scenario A, shown in Fig. 5(a), considers the lateral expansion and wear-out of the percolated region within the IL, which could be triggered by locally high current density and thermal effects that can accelerate defect generation by a positive feedback mechanism. Scenario B (Fig. 5(b)) refers to the likelihood that the HK which experiences higher voltage drop after IL percolation, breaks down completely bridging the gate to the substrate. This is the stage that most TDDB tests in literature report [14, 37, 38] due to either poor control or non-optimal choice of voltage stress and compliance capping. Another possibility is the uncorrelated nucleation of multiple SBD spots within the IL layer (Scenario C (i.e., Fig. 5(c))). It may be very likely that the nucleation spots for breakdown in the IL are strongly linked to the microstructure of the HK, i.e. the grain boundaries that are preferred regions for oxygen vacancy segregation and diffusion [39, 40]. Finally, Fig. 5(d) shows the last case that considers

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metal atom migration into the oxide along the percolated region, resulting in a hard breakdown (HBD) event. In the next section, we shall analyze in detail the feasibility of each of these scenarios using electrical / physical / modeling / simulation tools as a support.

IV. IN-DEPTH ANALYSIS OF POST BREAKDOWN SCENARIOS

A. Dilation of Interfacial Layer Percolation Path

Long duration stress tests after SBD in SiON point to a critical electric field (ξCRIT ~ 12.5 - 13 MV/cm) needed to observe wear-out of the percolation path by dilation and additional oxygen vacancy defect generation in a practical measurement time frame of 105-106 sec, as shown by Fig. 6(b). This in turn points to a critical voltage (VCRIT) [41] for the percolation path to dilate, as plotted in Fig. 6(a). The concept of ξCRIT relates to the need for a certain current density and localized temperature for creating sufficient O-vacancy defect concentration inducing a self-sustained positive feedback to dilate the SBD spot [35].

Figure 5. Illustration of the four possible scenarios for post breakdown degradation in the HK/IL stack – Case (A) - lateral dilation and wear-out of IL percolation path, Case (B) - subsequent localized BD of HK above the IL percolation region, Case (C) - multiple uncorrelated BD spots across the IL layer and Case (D) - metal migration and filamentation from gate. The yellow-red and green circles represent the pre and post-TDDB stage traps. The orange shaded intrusion in (D) refers to the metal migrating down into the oxide.

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Figure 6. (a) Trend of the minimum and maximum critical voltage (VCRIT) needed in ultra-thin SiON to cause notable “wear-out” in a reasonable frame of time ~ 105-106 sec. The value of VCRIT decreases linearly with oxide thickness. The above measurements were carried out on a single layer SiON, but they can be applied to the case of IL (SiOx) SBD with reasonable accuracy. (b) Corresponding critical field (ξCRIT) for the wear-out to be triggered. As expected, the value of ξCRIT remains approximately independent of the oxide thickness, implying that the wear-out is a field-driven phenomenon.

When the linear trend of VCRIT – tOX (Fig. 6(a)) is extrapolated to ~ 12Ǻ, which is the IL thickness in this device, we get a value for VCRIT(IL) ~ 1.25 – 1.65V. In order to observe an analog wear-out in the percolated IL region, the overall applied Vg ~ 2.84 – 3.75V, calculated using the Gauss law [42] by taking into account the voltage drop across the HK and IL (assuming κIL = 6 before SBD and κIL = 9 after percolation due to higher sub-stoichiometry). This is much higher than the nominal operating voltage of Vop = 1 – 1.1V and far beyond the stress level that the stack can sustain over prolonged time. In order to further support this conclusion, we show some current traces in the HK-IL stack after IL SBD in Fig. 7. Note that even when Vg is increased to 1.75 – 2.75V, we do not observe any clear analog leakage current increase trends corresponding to a percolative wear-out. At Vg ~ 3V, the HK layer experiences sufficient stress to suffer a subsequent localized BD, above the percolated IL region.

Figure 7. (a) to (e) RTN fluctuations in the HK-IL stack after one-layer IL BD. For all Vg up to 3V, we only observe digital leakage, as the voltage drop across the percolated IL is only about 44%·Vg < VCRIT. For Vg ~ 3V, the intact HK layer is prone to TDDB and no analog evolution of BD in the IL layer is observed at this stage. The presence of a dual layer stack prevents evolution of the percolated IL region (after one-layer BD) into the analog regime, as the HK serves as a good voltage “buffer”.

From the Monte Carlo model reproducing the defect evolution under typical operating voltage of Vop = 1V, stressing at ξ < ξCRIT leads to very minimal (slow) dilation and oxygen depletion of the percolated IL region created by the SBD event even after 3 × 106 sec, as simulated for the HfSiON-SiOx stack in Figs. 4 (d, h, l). Note that this model considers the increase in κIL due to higher oxygen depletion in the IL layer after SBD. At Vop = 1V, the ξ-field in IL tends to be much lower than ξCRIT, which ensures very good robustness of the IL SBD path to any further degradation. Only digital

(A) (B)

(C) (D)

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random telegraph noise (RTN) fluctuations are observed during measurement (Fig. 7). B. Subsequent Localized Breakdown of High-κ

Subsequent to IL SBD, there is a small increase in the voltage drop across the HK layer VHK (from 0.45•Vox to 0.56•Vox) that is induced by the SiOx sub-stoichiometry increase (κIL changes from 6 → 9 as the IL BD spot is not fully depleted of oxygen → no Si-rich filament is formed at this stage [34, 43]). This marginal increase in voltage does not support any significant increase of TGR in HK, when compared to the significantly higher intrinsic TGR in the IL (Fig. 3). This is confirmed by post-BD simulations in Fig. 4(c, g, k, d, h, l), which show that almost all traps are generated within the IL layer, whereas very few defects are created in the HK layer, which is not subject to any notable degradation. For this reason, it is difficult to observe any BD in the second layer i.e., HK, unless it is intentionally subjected to very high accelerated stress, as in Fig. 7(e). We have previously derived the same conclusion by means of a comprehensive HK-IL cumulative damage and Kinetic Monte Carlo defect kinetics model in [30]. Such accelerated test results support the conclusion that the formation of a percolation path in the HK takes an extremely long time, i.e. many orders of magnitude more than 3 × 108 sec (10 years).

C. Multiple Soft Breakdown within Interfacial Layer

Based on the illustration in Fig. 5(c), we can have multiple uncorrelated IL SBD spots nucleating all around the device during the wear-out stage at Vop = 1V. This is clearly shown in Fig. 4(d, l): two new spots are created in the small IL volume surrounding the GB. More spots are created with the assistance of multiple GBs present in the HK film (not shown for brevity). Modeling the statistics of multiple (uncorrelated) IL SBD events occurring in the post-BD degradation is very important from a circuit reliability perspective.

Figure 8. Weibull plot showing the measured distribution of percolation leakage at Vop = 1V after the IL SBD event. The leakage current (BD hardness) shows a large variation of about two orders of magnitude due to the different stochastic number of defects and their random configuration during the percolation process.

Considering the Weibull parameters for the time-to-first-IL SBD after area scaling from single transistor to circuit level taking 109 transistors (β = 0.85, η = 9.49 × 105 sec at Vop =

1V) and also the scale and shape parameters for leakage current distribution after IL SBD (Fig. 8) → (βI = 0.869, ηI = 28.1 nA at Vop = 1V, assumed Weibull here), we make use of multiple BD statistics [44] and Monte Carlo simulations [45] to evaluate the time needed for reaching the standard circuit failure criteria of Igl ~ 10μA. The results of the statistical simulation of percolated current increase with time are plotted in Fig. 9 for 200 similar trials. Our analysis here reveals that around 70 – 360 new BD spots are created within a 3-10 year time frame (this number could be larger in the presence of multiple grain boundaries), which causes the cumulative percolation leakage to reach the above circuit failure criteria.

Figure 9. Monte Carlo simulated evolution of percolation current due to multiple IL SBD spots (8 BD events simulated for sample size 200 considering computational constraints) across a circuit consisting of 109 transistors. The simulation considers the experimental distribution of percolation current (varying BD hardness) of the IL SBD spots and also considers the statistics of time needed for multiple BD events. It is evident that circuit compliance of 10μA may be easily attained within a 10-year time span for this post-BD mode. For illustration, three selected traces of current evolution are also highlighted with solid lines in the above “cockroach” plot.

D. Metal Migration and Filamentation

With the replacement of polysilicon with metal / silicide based gate electrodes, migration of the metal into the BD spot has been frequently observed for high current compliances (Igl > 20-100μA) [9, 10]. This is attributed to the high localized temperature of approximately 700-800K in the percolated region that can accelerate the diffusion of the metal atoms [7, 46]. In the context of the dual layer stack scenario depicted in Fig. 5(d), it is to be ascertained whether the BD hardness of IL SBD is sufficient enough to provide the driving force for metal atom migration.

Physical analysis using high resolution transmission electron microscopy (HRTEM) and energy dispersive X-ray spectroscopy (EDS) on TaN-gated HK/IL stacks for different compliances was previously carried out [9]. We identified the location of the BD spot along the channel by measuring the ratio of source and drain currents [47]. Fig. 10 shows the TEM

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micrographs for four compliances Igl = {2, 5, 8, 10}μA. For SBD events with very low Igl (i.e. only the IL breaks), no metal migration is observed. Only for higher Igl values, where the BD spot has formed throughout the whole HK/IL stack during the BD transient, we detect significant Ta diffusion into the oxide all the way punching through the substrate. This has been confirmed further by EDS analysis (Fig. 11) on the sample in Fig. 10(c). In the BD spot region (denoted by the green line ‘3’ in the legend of Fig. 11), significant Ta peaks show up.

Figure 10. HRTEM micrographs of four TaN-based HK-IL stack devices along with the corresponding high angle annular dark field (HAADF) image for percolation to various pre-set compliance levels ranging from (a) Igl ~ 2µA, via (b, top right) 5µA and (c, bottom left) 8µA up to (d) Igl ~ 10µA [9]. Metallic filaments at the BD spot (electrically determined) are observed only for increased breakdown hardness of Igl ~ {8, 10}µA.

Figure 11. EDS spectra taken at various locations in and around the breakdown spot for the sample in Fig. 10(c), stressed to a compliance of Igl ~ 8µA. From the green trace, large Ta signals are detected in the dielectric, confirming that the bright shady contrast in the HAADF inset is representative of Ta-migration from the gate.

Using the dual-stage TDDB methodology advocated previously in [48], we have identified for small-area devices (~0.1μm2) that BD can be arrested to a single layer percolation in a HK/IL stack only for Igl < 1-2 μA. This compliance is in line with our TEM evidence in Fig. 10(a, b) where it is not feasible to observe metal migration. Although the cases of Igl = 2μA and 8μA are very close in compliance value, I-V measurements show that the corresponding percolated currents at Vop = 1V differ by as much as two orders for these two cases [48]. Therefore, this significantly higher current density and associated local temperature (joule heating) could cause the metal filamentation to take place after complete HK/IL stack BD during accelerated stressing. As for the practical scenario of IL-only BD, we can conclude that it is not feasible for metal filamentation to occur. In other words, HBD is an unlikely event in the circuit for nominal operating conditions. Note that the above analysis focuses on TaN-based technology only, but we expect similar results to hold for TiN as well. The case of Ni may be an exception given its very high diffusivity [49]. Since it is no longer used for gate material, we do not analyze it in-depth here. Future work should focus on developing analytical models that can estimate the time needed for metal filament to nucleate at Vop = 1V, considering the material properties (diffusion coefficient, activation energy) of different gate electrode materials for intrusion into the oxide.

From the analysis presented in this section, we infer that the most plausible mechanism for circuit failure at Vop = 1V is the multiple SBD events within the IL layer (Scenario C) along with very minimal dilation of the IL SBD path (Scenario A) after long operation time. The other mechanisms of subsequent HK BD (Scenario B) and metal filamentation (Scenario D) can be confidently discarded, at least for Hf-based gate dielectric stacks as the ones considered in this work.

With a future outlook towards zero-IL stacks, this study may have to be reassessed as the HK is the only layer in that case and its interface with silicon could be very defective causing the dynamics of breakdown to change. Moreover, a single layer HK undergoing SBD may be more prone to faster dilation as the “buffering” action would no longer be present.

V. CONCLUSION This study presents important results for future reliability

investigations on HK-IL stacks. Using a combination of physical and modeling approaches, we have compared the various post-BD scenarios rejecting the ones that are highly unlikely. The key concern to ensure adequate front-end reliability in circuits with HK-IL stack transistors should be to reduce the trap generation rate in the IL so that the time to first SBD and successive SBD events is postponed. This also depends very much on the HK microstructure, as IL SBDs tend to be localized around the GBs, as Monte Carlo simulations have shown. A lot more material engineering is required to improve the reliability of the HK-IL stack. We can conclude that the HK layer serves as an effective “buffer” that prevents the percolation path in the IL from expanding further. For nominal operating conditions, we are always safely confined to the SBD regime in HK-IL stacks because a part of

(a)

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the voltage load is taken by up the intact HK with very high bond energy. Future statistical studies on HK stack should focus more on quantifying the lifetime of the circuit by considering the multiple IL SBD scenario and not the dual layer complete HK-IL breakdown. The dynamics of leakage current evolution and defect kinetics subsequent to IL SBD should also be examined in greater detail by means of novel characterization techniques.

ACKNOWLEDGMENT The authors would like to thank the Singapore University of Technology and Design (SUTD) for fully funding this research work under the start-up Grant No. SRG ASPE 2010 004.

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