Abstract—A 0.7 V 400 nW fourth-order active-passive ΔΣ modulator with one active stage is presented in this paper using standard CMOS 65 nm technology. The modulator achieves 84 dB SNR and 80.3 dB SNDR in a signal bandwidth of 500 Hz with a sampling frequency of 256 kHz. The input-feedforward architecture is used to improve the voltage swing before the comparator of the traditional passive modulators, which enables simpler comparator design with no preamplifier as well as cascading three successive power-efficient passive filters. The first active stage is used to reduce the comparator’s noise and offset and to minimize the capacitive area. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.

I. INTRODUCTION Low power consumption is the major design criteria for medical implant devices. The analog-to-digital converters (ADCs) are the key building blocks of such devices, e.g. cardiac pacemaker. Delta-sigma modulation is a well-known and powerful ADC technique for its high resolution in low-speed applications (e.g., medical application).

Passive integrator, as an alternative to the power-hungry active (OTA-based) integrator, is a significant approach in the design of low-power and low-voltage delta-sigma (ΔΣ) modulators for reducing the analog power consumption [1]-[5]. Due to lack of dc gain inside the passive filter (or integrator), the modulator is sensitive to noise coupling, thereby affecting the signal-to-noise ratio (SNR). Passive modulators in [1] and [2] employ switched-capacitor (SC) gain-boost filter to compensate for gain. But, achieving high gain requires unrealistically large capacitive area as well as large sensitivity to parasitic capacitances. In [3] no dc gain is used in the second-order loop filter. Instead, a three-stage preamplifier is exploited before the comparator to compensate for the gain, which is a power consuming solution.

Due to no gain, the signal experiences a large attenuation inside the passive filter, making the comparator design a challenging task. The comparator non-idealities including noise, dc offset, and hysteresis directly limit the modulator resolution [4], [5]. The third-order modulator in [4] makes use of the passive filter in the first and third stages and an active Gm-C filter in the second stage in order to compensate for the loop gain and to mitigate the comparator’s offset and noise.

We utilize a low-power amplifier in the first integrator that can suppress the comparator non-idealities. Moreover, the kT/C noise from the succeeding passive stages is attenuated due to the gain of the first stage, resulting in significant reduction of the capacitive area.

The input feedforward architecture has an extra path from the input of the modulator to the quantizer [6]-[9]. This small architectural modification eliminates the signal component inside the loop filter; therefore the filter only processes the quantization noise [9]. This distinct feature of the feedforward modulator structure encourages cascading of three power-efficient passive filters, despite the large attenuation. Moreover, the voltage swing at the quantizer input is the sum of the input signal and the suppressed quantization noise (processed by the filter), which eases the comparator design without requiring any preamp circuit. Significant power reduction can be achieved due to (i) the reduced clock frequency by using higher-order and power-efficient SC filter, (ii) the removal of the power consuming preamp of the traditional feedback passive modulators [1]-[4], and (iii) the relaxed amplifier’s performance requirements in the full feedforward modulator structure [6], [7].

The rest of the paper is organized as follows. Section II discusses the issues and challenges associated with the design of passive modulators using traditional feedback structure. Section III describes both the architecture-level and circuit-level design of the proposed modulator, followed by the simulation results in Section IV. Finally, Section V concludes the work.

II. PASSIVE MODULATOR DESIGN WITH CIFB TOPOLOGY

In this section we take a closer look at the issues and challenges with the design of passive modulators implemented by cascade-of-integrators feedback (CIFB) topology.

A. System-Level Design Consider the linear model of the second-order passive ΔΣ

modulator architecture with a two-pole lowpass filter and a 1-bit quantizer shown in Fig. 1. To determine the signal and noise transfer functions (STF and NTF), a linear model is used for the quantizer. It is a gain stage, G, followed by additive white quantization noise. The gain factor G in a conventional active modulator is estimated as unity [10] if the integrators swing is maintained close to the reference voltage. In a passive

Ali Fazli Yeknami and Atila Alvandpour Division of Electronic Devices, Department of Electrical Engineering, Linköping University

SE-581 83 Linköping, Sweden, Email: ali@isy.liu.se

A 0.7-V 400-nW Fourth-Order Active-Passive Modulator with One Active Stage

1

Proceedings of 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

Y++

-

+

-

X

a2

+

passive

+G

E(z)

ρ = 64a2 = 0.3ρ = 64

passive

11

z1z

11

z1z

Fig. 1. The linearized model of the 2nd-order passive ΔΣ modulator using feedback (CIFB) topology.

Ф2Ф1

Ф2

Vin Vout

Ф1

VREF cmi

Ф2

Ф1

t - τ t t + τ t + 2τ

CS

C

Fig. 2. Basic passive filter in a single-ended form with two-phase clock.

modulator the signal swing at the quantizer input is much weaker than the reference level, due to the successive attenuation by the passive filters [2], [3]. Therefore, the G is non-unity. This gain is lumped into the comparator input, according to Fig. 1, and is a function of passive filter’s pole location [3]. An estimate of this gain is given by [2], [4] in which the overall loop gain is approximated as unity at half clock frequency fs/2. For an overall loop filter transfer function of HT, the estimated G is calculated as 1/|HT(fs/2)|. On the other hand, since the modulator is a nonlinear system, an accurate value of the gain can be only obtained by nonlinear simulation model [11].

For a simple passive filter shown in Fig. 2, the ideal transfer function can be given as:

1

1

z1

z)z(Vin)z(Vout)z(H (1)

where ρ = C/Cs. The low-frequency gain is unity and the -3 dB bandwidth can be obtained as

12f

f sdB3 (2)

where fs is the sampling clock frequency. Taking fs = 500 kHz, Cs = 2 pF, determined from thermal noise requirement, and C = 128 pF, placing the -3 dB bandwidth around 1 kHz, the NTF and STF of the second-order passive modulator (Fig. 1) can be approximated as:

2

2

2 z41.1z38.21

z41.1z77.236.1 GHGH3.01

1)z(NTF

2

2

2

2

z41.1z38.21

z02.0

GHGH3.01

GH)z(STF (3)

Fig. 3 depicts the magnitude of the NTF and STF. As expected, the passive modulator suffers from the limited in-band quantization-noise suppression due to no gain, resulting in low SNR. Unlike the conventional active ΔΣ ADCs which has unity-gain STF at low frequencies, some signal attenuation

Fig. 3. The NTF and STF magnitudes of a second-order passive modulator with ρ = 64.

Y+X- + + +

N1 N2 Nq

-Quantizer

G+

NCom

H1 H2

Fig. 4. Noise sources in a single-loop second-order passive modulator.

is obtained in the passive modulator. As clearly seen, this attenuation (or loss) is about -3.52 dB at dc. This is the fundamental problem of the passive filters and the major performance limiting factor in the passive modulators due to the large signal attenuation, which leads to an extremely low voltage swing at the quantizer input. For instance, for the second-order passive modulator in [3], the integrators output swing is in the order of 10 mVrms and 100 μVrms, respectively, for a full scale (FS) input, which the comparator has to detect it. A highly sensitive comparator is then required to distinguish the signal from the noise coupled inside the loop. Therefore, the comparator in this design employs a three-stage preamp circuit to compensate for the loop gain, dissipating a large amount of power. Other passive modulators have been designed using CIFB topology [1], [2], which rely only on the second-order loop filter. Cascading more than two passive filters is impractical because the large signal suppression would enforce the need for multi-stage power-consuming preamp circuit prior to the comparator.

B. Performance Limiting Factors As mentioned before, the lack of gain and significant signal

suppression inside the passive loop filter make the design of high-resolution comparator a critical and challenging task. To revisit other issues concerning the comparator design, we consider the linear model of a 2nd-order single-loop modulator, shown in Fig. 4, in which all the noise sources are specified. The baseband output signal can be written as:

21

q

21Com

12

1 HGHN

HHN

HNNXY (4)

where H1 and H2 are the integrators transfer functions, N1 and

2

YX

-

DAC

11

z1z

a1 a2 a3 a4

11

z1z

11

z1z

c4

c3

c2

c1

+ +11

z1z

-k

Fig. 5. Block diagram of the single-loop fourth-order full feedforward active-passive modulator with one active integrator in the first stage. N2 are their input-referred noise, respectively, while NCom and Nq represent the comparator input referred noise and quantization noise. Since both filters have no dc gain, only quantization noise obtains some lowpass filtering, due to the loop gain G provided by the quantizer. On the other hand, for a certain SNR the thermal noise (kT/C noise) of the passive filters can be always mitigated by scaling up the capacitors size. But, NCom is the only noise term that is not subject to any attenuation at low frequencies simply because H1 and H2 have no gain. NCom consists of thermal noise, of preamp, and the low frequency 1/f noise. To reduce noise, the passive modulator in [2] utilizes a preamp with input devices whose W/L ratio is 200μm/1.2μm, imposing about 0.5 pF at the comparator input. Moreover, in the passive delta-sigma ADCs due to no gain in stages preceding the comparator, the offset of the overall ADC is defined by that of the comparator [4].

To alleviate the non-idealities of the comparator, several solutions have been tried in the past [4], [5] where at least one active stage is used to suppress the input-referred noise and the dc offset. To summarize, due to a very small signal swing at the quantizer input of the passive ADCs using CIFB topology, the comparator design is a crucial and difficult task, limiting the design scaling to higher-order modulator. In this work, we propose a 4th-order modulator that employs three successive passive filters by means of cascade-of-integrators feedforward (CIFF) topology, resulting in voltage swing improvement at the comparator input. As a result, the comparator design becomes simpler and no power-consuming preamp is involved.

III. 4TH–ORDER ACTIVE-PASSIVE MODULATOR

A. Architectural Design Full feedforward architecture has become popular in recent

years for low-power and low-voltage modulator design [6]-[9], [12]. We take advantage of this architecture to improve the voltage swing at the quantizer input, a drawback of the passive modulators using traditional CIFB topology. As a result, the

TABLE I

MODULATOR COEFFICIENTS

comparator design becomes simpler and no preamp stage is required prior to comparator. Modulator Topology

Fig. 5 shows the block diagram of the single-loop fourth-order modulator topology with 1-bit quantizer. An active integrator is used in the first stage, while three SC passive filters are employed in the following stages. The passive filters are described using transfer function given by (1). The feedforward branches are summed at the input node of the quantizer. The optimal coefficients of the designed modulator are calculated from the behavioral simulation and are summarized in Table I. The NTF can be calculated as

64.4z19.15z97.5z91.7z

69.4z42.13z76.11z03.2z)z(NTF234

234 (5)

The magnitude plot of the NTF is shown in Fig. 6.

Behavioral simulation indicates that the signal amplitude at the quantizer input is 40 mV for a FS input, much lower than the reference voltage, 0.5 V in this design. Since the delta-sigma ADC is a nonlinear block, the equivalent gain of the quantizer can be directly calculated from the simulation.

A local resonator feedback loop with a gain coefficient of k is used to move a pair of the NTF zeros to the edge of the signal band. In this way, some SNR improvement can be achieved.

Filter coefficients

Feedforward coefficients

Resonator coefficient

a1 = 0.2 c1 = 2 k = 1/64 a2 = 1 c2 = 3 a3 = 1 c3 = 2 a4 = 1 c4 = 5

3

Fig. 6. The NTF magnitude of the designed 4th-order modulator.

Integrator Output Swings

A behavioral simulation with -1.94 dBFS input signal is performed to show the integrators output swing and the summed voltage level at the quantizer input. The reference voltage is set to 0.5 V. As can be seen from Fig. 7, the largest swing is observed at the first integrator output, but it is still within 60% of the reference voltage. The reduced swing enables the OTA, which is a critical and power consuming block, to have relaxed slew-rate requirement, hence low-power consumption. The output swing at the succeeding passive integrators is decreased continually. As the loop filter in a full feedforward topology ideally only processes the quantization noise [9], the continuous attenuation would not harm the input signal. In contrast to the traditional CIFB topology, the feedforward topology has a signal path from the modulator input to the quantizer. Therefore, the voltage level at the quantizer input (see Fig. 7) is still large enough for the comparator to detect it without requiring preamp circuit. More details of circuit design are explained in the following section.

B. Circuit-Level Design This section describes the overall modulator circuit and its

building blocks. The low-voltage amplifier used in this design was presented before in [13].

Passive Filter Design

The passive filter used as an integrator in the second, third and fourth stages is shown in Fig. 2. The larger ρ places the filter pole to a lower frequency, according to (2). On the other hand, the overall loop gain is distributed among the first active pole sector as well as the quantizer gain.

The parameter ρ = C/Cs in general is selected such that the -3 dB bandwidth of the integrators, based on (2), to be placed near the edge of signal bandwidth. The simulation demonstrates that the signal swing at the quantizer input is almost constant for ρ ≥ 32 (Fig. 8).

On the other hand, the parameter ρ can be also obtained from the SNDR simulation, which reflects both the quantization noise and the distortion. The simulation result shown in Fig. 9 indicates an optimal ρ of 64.

Fig. 7. Integrators output swing with a 187.5 Hz -1.94 dBFS input signal. Comp represents the comparator input signal, and Inti (i = 1-4) represents the ith integrator output.

Fig. 8. The quantizer input swing with a 187.5 Hz -1.94 dBFS input.

Fig. 9. Modulator SNDR across ρ with a 187.5 Hz -1.94 dBFS input.

Local Resonator

The purpose of the local resonator feedback loop used in the designed modulator is to move a pair of the NTF zeros to the edge of the signal band, improving the in-band noise shaping. It creates a simple negative feedback loop with a gain coefficient k of 1/64. The resonator is simple to realize (two switches and one small capacitor) with SC implementation.

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inn

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Cf3

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cm cm

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cm

Cf3

Cf2

Cf1

Cf0Ф1 Ф2

cm

Ф1

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Cb

Ф1

Ф2

Cb

Fig. 10. Schematic of the presented fourth-order active-passive modulator.

Fig. 11. Simulated output spectrum with/without local resonator with a 187.5-Hz -1.94 dBFS input signal. Fig. 11 shows the simulated output spectrum with/without local resonator. A 5 dB SNDR improvement has been achieved in this way at the expense of a small area penalty.

Single-bit Quantizer

The 1-bit quantizer in this design is composed of a dynamic regenerative comparator followed by a SR latch [14]. The existing passive ADCs [1]-[4] make use of traditional CIFB architecture, which primarily suffer from the extreme signal suppression. This makes the design of the comparator a challenging task. The use of preamp stages prior to the comparator circuit, as a power consuming solution, is essential for detecting the very weak signal. This design does not use any preamp circuit, leading to a significant power saving. 35% of the total power in [1] is from its preamp power. The simple reason is that the selected CIFF modulator structure relaxes the signal swing requirement at the quantizer input, as

TABLE II

CAPACITANCE VALUES IN PF

compared to the traditional CIFB structure. As the signal before the comparator in the designed modulator is the sum of the input signal, the first active integrator and the attenuated signals from the succeeding passive integrators, it is still much stronger than that of a modulator implemented by CIFB structure (see Fig. 7). We then utilize a simple and power-efficient quantizer circuit presented in [14] without preamp.

Complete Modulator Circuit

The overall modulator circuit is shown in Fig. 10. It has four integrators with an active one in the first stage and three simple passive ones in the following stages. A dynamic comparator and a latch are used as a quantizer. The common-mode voltage is set to the middle of the power supply, i.e. 0.35-V. The reference voltage is set to 0.5 V, which is defined as VREFP of 0.6 V and VERFN of 0.1 V. The capacitor values are summarized in Table II. The capacitor value of the first integrator (i.e., CS1) and the signal feedforward path (i.e., Cf0) are selected to fulfill the kT/C

Sampling capacitors

Integrating capacitors

Feedforward capacitors

Resonator coefficient

Cf0 = 1 Cb = 0.25 CS1 = 1 C1 = 5 Cf1 = 2

CS2 = 0.25 C2 = 16 Cf2 = 3 CS3 = 0.25 C3 = 16 Cf3 = 2 CS4 = 0.25 C4 = 16 Cf4 = 5

5

noise requirement of the modulator with a safe margin [10]. The other modulator sampling and feedforward capacitors (i.e., CSi and Cfi for i = 2,3,4) are chosen to satisfy the modulator coefficients in Table I. The first integrating capacitors (i.e., C1) is chosen to realize coefficient a1 = 0.2, while the rest of the integrating capacitors (i.e., Ci for i = 2,3,4) are chosen from the passive filter requirement, discussed in section III-A. Moreover, the resonator capacitor is calculated as 0.25 pF in order to realize resonator gain coefficient 1/64.

IV. SIMULATION RESULT The proposed modulator is designed in 65 nm CMOS

technology and is simulated with a 256 kHz clock frequency. Table III summarizes the simulation results. The modulator achieves 84 dB and 80.3 dB peak SNR and peak SNDR, respectively, from a 0.7 V supply voltage. The simulated output spectrum of the designed modulator with a 187.5 Hz and -1.94 dBFS input signal is shown in Fig. 12. Fig. 13 shows SNDR with respect to the oversampling ratio (OSR).

V. CONCLUSIONS An ultra-low-power 0.7 V fourth-order active-passive

modulator is designed in a 65 nm CMOS process. The issues and challenges with the design of the traditional passive modulators are discussed. Input-feedforward modulator architecture is used to improve the voltage swing before the quantizer, which makes the comparator design simple and power efficient. An active integrator is utilized in the first stage, which attenuates the comparator’s offset and noise and also reduces the capacitors size of the following passive integrators significantly. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.

Fig. 12. Simulated output spectrum of the designed modulator with a 187.5-Hz -1.94 dBFS input.

REFERENCES [1] A. Fazli Yeknami and A. Alvandpour, “A 0.5-V 250-nW 65-dB SNDR

Passive Modulator for Medical Implant Devices,” IEEE Int. Symposium on Circuits and Systems (ISCAS), May 2013, pp. 1-4.

[2] F. Chen and B. Leung, “A 0.25-mW Low-Pass Passive Sigma-Delta Modulator with Built-In Mixer for a 10-MHz IF Input,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 774-782, June 1997.

Fig. 13. Simulated SNDR versus OSR.

TABLE III

SIMULATED PERFORMANCE RESULTS [3] F. Chen, B. Bakkaloglu, and S. Ramaswamy, “Design and Analysis of a

CMOS Passive ΣΔ ADC for Low Power RF Transceivers,” J. of Analog Integr Circ Sig Process, Vol. 59, Issue 2, pp. 129-141, 2009.

[4] R. Yousry, E. Hegazi, and H. F. Ragai, “A 3rd-Order 9-Bit 10-MHz CMOS ΔΣ Modulator with One Active Stage,” IEEE Trans. on Circuits Syst. I, vol. 55, no. 9, pp. 2469-2482, Oct. 2008.

[5] A. Das et al., “A 4th-order 86dB CT ΔΣ ADC with Two Amplifiers in 90nm CMOS,” ISSCC Digest of Technical Papers, vol. 1, pp. 496-612, Feb. 2005.

[6] J. Roh, S. Byun, Y. Choi, H. Roh, Y. G. Kim, and J. K. Kwon, “A 0.9-V 60-μW 1-bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 361-370, Feb. 2008.

[7] J. Zhang et al., “A 0.6-V 82-dB 28.6-μW Continuous-Time Audio Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 46, no. 10, pp. 2326–2335, Oct. 2011.

[8] J. Wang, T. Matsuoka, K. Taniguchi, “A 0.5 V Feedforward Delta-Sigma Modulator with Inverter-Based Integrator,” in Proceedings of ESSCIRC, 2009, pp. 328-331.

[9] L. Yao, M. Steyaert and W. Sansen, "A 1-V, 1-MS/s,88-dB Sigma-Delta Modulator in 0.13-μm Digital CMOS Technology", Digest of Technical Papers of Symposia on VLSI Technology and Circuits (VLSI), Kyoto, Japan, pp. 180 - 183, June 2005.

[10] S. Rabii and Bruce A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. Kluwer Academic Publishers, 2002.

[11] S. Norsworthy, R. Schreier and G. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. IEEE press 1997.

[12] F. Michel and M.S.J. Steyaert, “A 250 mV 7.5 μW SNDR SC Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 2326-2335, Mar. 2012.

[13] A. Fazli Yeknami and A. Alvandpour, “A 0.7-V 600-nW 87-dB SNDR DT-ΔΣ Modulator with Partly Body-Driven and Switched Op-amps for Biopotential Signal Acquisition,” Proceedings of IEEE Biomedical Circuits and Systems Conference (BioCAS), Nov. 2012, pp. 336-339.

[14] A. Fazli Yeknami and A. Alvandpour, “A 2.1 μW 76 dB SNDR DT ΔΣ Modulator for Medical Implant Devices,” Proceedings of IEEE Norchip Conference, Nov. 2012, pp. 1-4.

Technology 65 nm CMOS Supply Voltage 256 kHz 1.024 MHz

Clock Frequency 0.7 V Signal Bandwidth 500 Hz

Input range 0.5 Vpp Peak SNR 84 dB 92.8 dB

Peak SNDR 80.3 dB 86 dB Power 400 nW 650 nW

6