A PVT-Variation Tolerant Fully Integrated 60 GHz Transceiver for IEEE 802.11ad

Takayuki Tsukizawa1, Atsushi Yoshimoto2, Hiroshi Komori2, Kenji Miyanaga1, Ryo Kitamura1, Yohei Morishita1, Masatake Irie2, Yoichi Nagaso2, Takeaki Watanabe2, Koji Takinami1, and Noriaki Saito1

1 Panasonic Corp., Yokohama, Japan, 2 Panasonic Corp., Nagaokakyo, Japan tsukizawa.takayuki@jp.panasonic.com

Abstract

A PVT tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad is presented. By introducing a newly proposed self-sensing LDO, the transceiver adjusts bias currents and the LDO output voltage for the PA to minimize the output power variation while relaxing the hot carrier injection (HCI) degradation. The measurement shows excellent robustness against PVT variations, demonstrating only 5 dB output power variation over -20 °C to 85 °C across process corners.

Introduction The 60 GHz short range wireless system, such as IEEE

802.11ad, has gained significant attention as an enabler for wireless high-definition video links and multi-Gb/s data transfer. While recent works have demonstrated a capability of realizing 60 GHz transceivers in cost effective CMOS technology [1-3], the sustainability of performance over PVT variations remains a difficult challenge. This is especially critical for mobile terminals since the transceiver must be integrated in a miniaturized RF module as illustrated in Fig. 1 under severe thermal constraints.

This paper addresses the performance degradation of the transceiver, in particular the output power variation during packet transmission in which periodic calibration is difficult due to short non-transmit intervals. Fabricated in 90 nm CMOS technology, the proposed transceiver achieves excellent robustness against PVT variations while satisfying requirements for the IEEE 802.11ad standard.

Architecture and Calibration Concept

The overall architecture of the proposed transceiver is shown in Fig. 1. It is based on the chipset presented in [3] with additional features mainly in the TX path. It consists of a four-stage PA, a quadrature modulator (QMOD) and variable gain amplifiers (VGAs). The TX output power varies with PVT variations, which is compensated by a combination of (1) the APC feedback loop including gain adjustment of the VGA as well as a local amplifier (LOAMP), (2) the process and temperature self-sensing LDO and (3) the gain-up VGA that compensates for the output power reduction at high temperature after APC.

Unlike conventional Wi-Fi transmitters, the output power reduction at high temperature and slow process corner is compensated by not only controlling the bias current but also increasing the supply voltage. This is effective to recover the reduced amplifier gain where ft/fmax is limited with respect to the operation frequency of 60 GHz. However, special care must be taken because of a reliability issue due to the HCI degradation. In the proposed TX system, the supply voltage is made higher only when the TX output power is reduced due to high temperature or slow process corner. The total gain of the TX path is adjusted by the APC which controls the gain of the VGA and the LOAMP. The LOAMP gain control is introduced to overcome the gain reduction of the QMOD at the worst case

condition while minimizing the current consumption of the LO chain at the typical condition.

Fig. 2 illustrates the operation of the proposed system. Each packet consists of the short training field (STF), the channel estimation field (CEF) followed by the header and the data. The transmitted packets are separated by 3 μs minimum gaps. Since the AGC of the receiver needs to converge within 1.24 μs of the STF, the TX APC must be completed before packet transmission. At turn-on of the TX, the APC adjusts the TX output power to the desired level by increasing the gain of the VGA and the LOAMP, which takes less than 250 μs. During packet transmission, the junction temperature goes higher, resulting in the reduction of the PA output. The situation becomes even tougher for video streaming where dense packets are continually transmitted for long time. In the proposed TX, the LDO output voltage and the VGA gain are automatically adjusted to compensate for the TX output power variation.

Circuit Design

Fig. 3(a) shows the schematic of the self-sensing LDO. It utilizes two reference currents IBGR (from the band gap regulator) and IPTAT (proportional to absolute temperature). The zero temperature coefficient bias point (VZTC) is generated by IBGR and the diode-connected nMOS to supply a reference current INMVT to compensate for the process variation. On the other hand, IHTUP is generated by IBGR and IPTAT for the output power adjustment mainly above 10 °C. Combining these reference currents, the LDO supply voltage of 1.8 V is regulated down to the range of 1.14 V to 1.38 V, depending on the operating conditions as shown in Fig. 3(b). Fig. 4(a) and (b) shows the schematic and the output voltage waveforms of the PA respectively. The transformer at the PA output serves as an ESD protection. The DC voltage is supplied by VLDO from the self-sensing LDO. The bias current for each stage is mirrored by IPTAT. The PA output is extracted through a 10 dB coupler followed by the envelope detector, whose output is split for the AC path and the DC path. The DC path is followed by the resistive feedback amplifier to expand its dynamic range and fed back to the ADC. The AC path is connected to the receiver for DC offset and IQ-imbalance calibration. The self-sensing LDO adjusts VLDO to achieve higher gain while minimizing the HCI degradation. The accelerated voltage-stress test revealed that the instantaneous maximum voltage should be less than 1.78 V for the 1.4 V overdrive transistor available from 90nm CMOS technology. The nominal supply voltage is set to 1.2 V which is increased to 1.32 V at 85 °C. This leads to 2 dB improvement in the output power as compared to the conventional constant supply voltage. Note that the conventional design violates the HCI limit at -20 °C, which requires that the supply voltage should be further lowered causing additional decrease of the output power at high temperature. The VGA has the gain range from 3 dB to 15 dB with a 4-bit digital control for the APC. The VGA

978-1-4799-3328-0/14/$31.00 ©2014 IEEE 2014 Symposium on VLSI Circuits Digest of Technical Papers

bias circuit is designed such that it increases the current from 27 °C to 85 °C, providing 3 dB gain compensation to improve the total TX gain variation.

Measurement Results A prototype was fabricated in 90 nm CMOS including process corner samples. Fig. 5(a) shows the measured input to output characteristics at CH2 (60.48 GHz). The APC adjusts the TX output to +2 dBm at -20 dBm input across three process corners. The measured EVM with MCS 9 (π/2-QPSK modulation, 2502.5 Mb/s at PHY rate) burst mode is less than -19.6 dB, which satisfies the specification of -15 dB. Fig. 5(b) compares the temperature variations after APC. The output power variation over -20 °C to 85 °C at ambient temperature is only 5 dB, and the power reduction at 85 °C improves by 8.1 dB compared to the previous design [3]. Fig. 5(c) shows the measured NF of the RX, achieving less than 9 dB. Fig. 6 shows the die photo which occupies the active area of 5.7 mm2. Table I and II are the performance summary and the performance

comparison respectively.

References [1] S. Emami, et al., “A 60GHz CMOS Phased-Array Transceiver

Pair for Multi-Gb/s Wireless Communications,” ISSCC Dig. Tech Papers, pp. 164-165, Feb. 2011.

[2] K. Okada, et al., “A Full 4-Channel 6.3Gb/s 60GHz Direct-Conversion Transceiver with Low-Power Analog and Digital Baseband Circuitry,” ISSCC Dig. Tech. Papers, pp. 218-219, Feb. 2012.

[3] T. Tsukizawa, et al., “A Fully Integrated 60GHz CMOS Transceiver Chipset Based on WiGig/IEEE802.11ad with Built-In Self Calibration for Mobile Applications,” ISSCC Dig. Tech. Papers, pp.230-231, Feb. 2013.

[4] D. Dawn, et al., “60-GHz Integrated Transmitter Development in 90-nm CMOS,” IEEE Trans Microwave Theory and Techniques, vol. 57, no. 10, pp.2354-2367, Oct. 2009.

[5] Hittite, “HMC6000LP711E data sheet,” [Online]. Available: http://www.hittite.com/content/documents/data_sheet/hmc6000lp711e.pdf.

Fig. 2 Operation of proposed TX system.

Fig. 1 Block diagram of 60 GHz transceiver for IEEE 802.11ad.

Fig. 4. (a) Schematic of PA, (b) output voltage waveform.

Fig. 3 Schematic of process and temperature self-sensing LDO.

Fig. 5 Measured (a) TX input to output characteristics, (b) temperature variation and (c) process and temperature variations of RX noise figure.

PMU

TX

RX

LO

RF ctrl.Process variation Typ.Temperature [˚C] 27Current

consumption [mW]TX 361 RX 260

TX output power [dBm] *1 1.9 TX EVM at MCS9 [dB] *1 -19.6

Psat [dBm] 5.7 Noise figure [dB] *2 6.3

RX Gain [dB] *2 54.7 IP1dB [dB] *2 -61.5

*1 after adjusting 2dBm at 27ºC, *2 -78dBm input settings

*3 at 80ºC, *4 estimated from measurement result

This work [4] [5]

Process 90nmCMOS

65nmCMOS

SiGeBiCMOS

Temperature variationof output power at 85ºC

Typ. -2.6dB -4.5dB *3 -9.0dB *4Fast -3.1dB - -Slow -2.3dB - -

Table I Performance summary at CH2.

Table II Performance comparison of 60GHz transmitter.Fig. 6 Die photo.

Bottom view Top view

(a)

(b)Proposed(Adaptive Vdd & IPTAT)Conventional(Constant Vdd & IBGR)

1.2V

2dBm -2dBm5dBm-20ºC +27ºC +85ºC

1.2V1.32V

1.17V

2dBm 0dBm4dBm-20ºC +27ºC +85ºC

HCI Limit HCI Limit

-40-20 0 20 40 60 80100

1.4

1.3

1.2

1.1

Temperature [ºC]

V LD

O[V

] SlowTyp.Fast

Sim. Meas.(a)

(b)

(a) (b) (c)

SlowTyp.Fast

1007550250-250

5

10

15

Temperature [ºC]

Noi

se fi

gure

[dB

]

ConventionalThis work

1007550250-25-20

-15

-10

-5

0

5

10

Temperature [ºC]Out

put p

ower

var

iatio

n [d

B]

5dB

8.1dB

SlowTyp.Fast

0-10-20-30-40-20

-15

-10

-5

0

5

10

Input power [dBm]

TX o

utpu

t pow

er [d

Bm

]

EVM:-19.6dB

2014 Symposium on VLSI Circuits Digest of Technical Papers