The Effect of CF4 Plasma on the Device Parameters and Reliability Properties of 0 . 1 8 p MOSFETs

Robin C.J. WanglY2, J.R. Shih', L.H. Chu', Kelvin Y.Y. Doong',2, L.S. Wang', P.C. Wei', D.S. Su', C.T. Yang', C.C. Chiu',David Su', Y.K. Peng', John T. Yue' and Joseph YM. Lee2

Taiwan Semiconductor Manufacturing Company. Hsin-Chu, Taiwan, ROC *Institute of Electronic Engineering, National Tsing-Hua Univ., Hsin-Chu, Taiwan, ROC

Phone: 886-3-5780221 Ext: 5797. Fax: 886-943-890379. Email: jjwange@tsmc.com.tw

1

Abstract As the device geometry continued to be scaled

toward deep sub-micron, high dose ion implantation was essential in the source/drain engineering for semiconductor device fabrication. However, carbonized photoresist residuals became a critical issue in photoresist stripping step of high dose ion implantation process. In order to remove photoresist residuals effectively and completely, a fluorine-based gas such as CF4 was widely used in photoresist ashing applications. A non-optimized CF4 ashing recipe would cause fluorine penetration into the gate oxide and affect device parameters. In this work, ashing recipes with different CF4 plasma processing times were used in the source/drain photoresist stripping process to evaluate its influence. Results of this experiment showed that longer CF4 plasma processing time gave rise to more gate oxide thickness, higher threshold voltage, negative shift of flatband voltage, good immunity to hot carrier injection (HCI) stress and improved negative bias threshold instability (NBTI). And oxide integrity degradation in charge-to-breakdown (ad) was observed.

Introduction Independent of whether fluorine was come from

implantation or diffusion process, additional fluorine in gate oxide had been reported to have many significant effects. Some benefits to device reliability were known including superior hot-carrier immunity [ 11-[4], better dielectric integrity [5][7] and improved NBTI [9]. A negative effect was fluorine enhanced boron diffusion in oxide, which led to threshold voltage shifts and degraded dielectric quality [6][8]. Changes in oxide thickness and flatband voltage had also been previously reported [l]. Although many hypotheses had been proposed, the mechanism focusing on the behavior of fluorine in oxide had not been completely investigated. This work explored fluorine effect on device parameters as well as the reliability in CF4 plasma ashing process. The objective was to characterize the impact of CF4 plasma so as to optimize the CF4-based ashing process.

Experiment The test wafers were made by 0 . 1 8 ~ dual gate

oxide technology with the features of shallow trench isolation and Co-silicide process. During the source/drain engineering, there were three ion implantation layers (N+/P+/ESD) that might produce photoresist residuals,

which required enhanced CF4 plasma ashing to strip the resulting residuals. The test patterns used in this study were described in Table.1. Those were n/ and p/ MOSFETs with thick (for U0 devices) and thin (for core devices) gate oxide. In this work, three kinds of ashing recipes were used as Table.2 showed. Each step was performed by using Inductively Coupled Plasma (ICP) type asher. These wafers were processed through FEOL and BEOL. They were analyzed by HP4284 and HP4145. In addition, Charge-to-breakdown (Qad), HCI effect and NBTI were also examined.

Results and Discussions I . Changed oxide thickness with different CF4

Figure. 1 illustrated that different CF4 processing times change the thickness for both 65 A and 38 A gate oxides. Treatment under CF4 processing time 60sec resulted in increases of - 1.5 A and - 0.4 A, respectively, for thick and thin gate oxides. The thickness of the thicker oxide increased more than that of the thinner one. This additional thickness could be a result of an actual increase in oxide thickness or a change in the dielectric constant of the oxide. Wright's report indicated that the increase was actually caused by a real increase in oxide thickness. This increase was contributed by fluorine replaced oxygen in the dielectric and displaced oxygen toward the interface to react with Si[l]. Our result was also consistent with this hypothesis since the increase amount of additional oxide thickness was proportional to the original oxide thickness.

processing times:

II . Shifted threshold voltage with different CF4 processing times: Figure.2 showed the relative threshold voltage shifts

of various MOSFETs (thick and thin gate oxide, N/ and P/) &er CF4 ashing. It was observed that the shift of the NMOS was larger than that of the PMOS. Also, the shift of the thicker oxide was larger than that of the thinner oxide. From the viewpoint of 60 sec CF4 processing times, the NMOS with thick oxide had larger threshold voltage shifts (14mV) than the others (1-8mV). Lower capacitance induced by the additional oxide growth was primarily responsible for the higher shifts of threshold voltage. Fluorine induced boron penetration caused PMOS to have smaller shifts than NMOS since boron diffused into the channel lowering the threshold voltage. Thin gate oxide in PMOS also enhanced boron

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penetration due to its weaker capability for blocking fluorine diffusion.

Ill. Shifted flatband voltage with different CF4

A result of relative flatband voltage shift versus different different CF4 processing times was shown in Fig.3. The long CF4 processing time was found to decrease the flatband voltage. This mechanism could result from the dangling bonds induced by fluorine on silicon acting as hole traps in fluorine-enriched oxide [ 11. The PMOS with thick gate oxide had more flatband shifts (-0.4V) than the other ones (0 - -0.12V) because the former contributed more positive traps, which were proportional to the oxide thickness.

processing times:

IV. Degraded oxide integrity with longer CF4

Many studies reported that the presence of fluorine was beneficial to oxide integrity [5 ] . However, excessive or inappropriate fluorine-related process will lead to degradation of the oxide [6]. Our observation illustrated that CF4-based plasma process tended to degrade the oxide and finger type polysilicon gate test structure (polysilicon gate edge intensive GO1 test structure) showed more severe degradation than bulk type as Fig.4 -Fig.7 showed. Qbd was found to degrade by 20 - 30% and the degradation were found to be proportional to CF4 processing time as well. Even though Si-F bonds were more stable than Si-0 bonds, excessive fluorine might acted as a “defect source within dielectric” to trigger oxide breakdown. Moreover, finger type test structure had more polysilicon gate edge exposed to the CF4 plasma environment than bulk type, thus providing more paths for fluorine penetration.

processing time:

V . Improved immunity to HCI with longer CF4

Hot carrier stress was performed to evaluate the HCI immunity of experimental MOSFETs in fluorine-enriched environment. As Fig.8 showed, NMOS with longer CF4 processing time had lower time-dependant drain current degradation in the linear region (b). To further examine the behavior of CF4 plasma processed MOS, the interface trap density before and ailer HCI stress was extracted from their gated-diode characteristics. After hot carrier stress on NMOS with thin gate oxide, the sample with 60 sec CF4 processing time was found to have -25% relatively less interface trap density than non-CF4 processed one as Fig. 9 showed. This was attributed to the stronger bonding energy of Si-F (5.73eV) compared to that of the Si-H bond (3.18eV). More CF4 processing time would create more robust Si-F bonds at the interface of Si/Si02 against the damage fiom hot electron [3].

processing time:

VI. Better performance of NBTI with longer CF4 processing time:

In threshold instability experiment, the PMOS threshold voltage will increase under high temperature (15OOC) and high gate voltage stress. The fluorine introduced by CF4 plasma improved the stability of the

interface. Fig. 10 indicated that longer CF4 plasma processing time has better capability against NBTI stress and showed lower time-dependant threshold voltage degradation.

Conclusions CF4 ashing in high dose implant processes had been

found to result in increases of oxide growth, shifts of threshold and changes of flatband voltage. In terms of reliability concerns, MOS treated with longer CF4 processing time showed more immunity to HCI and NBTI stress, but oxide integrity degraded. Although longer CF4 processing time formed more stable Si-F bonds, the penetration of excessive fluorine might create defects and traps. This effect was more pronounced in finger type polysilicon gate test structure because more routes were provided through polysilicon gate edge. In conclusion, longer CF4 plasma processing time was advantageous for photoresist ashing, HCI and NBTI. But its impact on oxide quality needed to be examined and evaluated further for an optimization of integration scheme.

Acknowledgements The authors would like to thank M.J. Chen, W.L.

Song, P.J. Liao, Y.H. Chiu and C.Y. KO for their supports and valuable discussions.

Reference [l] P. Wright et al., “The effect of fluorine in silicon dioxide gate dielectrics,” IEEE Trans. Electron Devices, vol. 36, pp. 879-889, May 1989. [2] E. da Silva et al., “Dramatic improvement of hot-carrier-induced interface degradation in MOS structures containing F or C1 in SiOz ,” IEEE Electron Device Lett., vol. 9, pp. 38-40, Jan. 1988. [3] T. Ma, “Metal-oxide-semiconductor gate oxide reliability and the role of fluorine,” J. Vac. Sci. Technol. A, vol. 10, no. 4, pp. 469471, 1992. [4] P. Wright et al., “Hot-electron immunity of SiOz dielectrics with fluorine incorporation,” IEEE Electron Device Lett., vol. 10, pp.

[5] P. Chowdhq et al., “Improvement of ultrathin gate oxide and oxpitride integrity using fluorine implantation technique,” Appl. Phys. Lett., vol. 70, no. 1, pp. 37-39, 1997. [6] L.S. Wang et al., “Characterization of CF4 Plasma Induced Damage During Dry Asbing and Residue Removal Process,” P2ID, pp.29-32, 2001. [7] C.C. Chen et al., ‘‘Improved Plasma Charging Immunity In Ultra-% Gate Oxide with Fluorhe and Nitrogen Implantation,” PZID,

[SI Y. Shioya et al., ‘Zffect of fluorine in chemical-vapor-deposited tungsten silicon film on electrical breakdown of Si02 film,” J. Appl.

[9] T.B. Hook et al., “The Effect of fluorine on ParameQics and Reliability in a 0 . 1 8 ~ 3.5/6.8nm Dual Gate Oxide CMOS Technology”, IEEE Electron Device., vol48, pp.1346,2001

347-348, Aug. 1989.

pp.121-124,2000.

Phy., V O ~ 61, pp.5102-5109, 1987.

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O d d e thickness

Transistor Capatiance Polysilicon gate

Bulktype I Finger type

Table3 Ash recipes of different CF4 plasma processing times.

99 9

995 99

95 8 9 0 - 8 8 0 -

t z : : f 20

70

$ ;:I

ThlCk P-wel l N M O S -+CF4 Os --%CF4 30s - +CF4 6 0 s

-

-

+Thin N M O S ++Thin P M O S +Thick N M O S -?Thick P M O S

n i c k

(65A) Thin (38A)

a-=-=--

NMOS P-well

PMOS N-well Area:1000000pm2, Area:l 0083750pm2,

NMOS P-wII Length:400OV m Length:72250OU m PMOS N-well

I O F 4 0s CF4 30. CF4 00s

CF, cond i t i on (sec)

0 5

01

Fig 1. Oxide thickness with different MOSFEiTs and CF4 processing times.

- Recipe CF4 Osec CF4 30sec CF4 6Osec

Condition 0 2 forming gas only, no CF4

Normal ashing, CF4 flow 30sec Enhanced ashina. CF4 flow 60sec

'. '..

ss 98

- 85 bp so

I CF, 0. CF4 30. CF4 6 0 s

-0.5 I C F 4 condition (sec)

Thick N -well PM O S - - - C C F 4 Os - -+CF4 30s - d C F 4 6 O s -

Fig 3. Relative flatband voltage shifts with different MOSFETs and CF4 processing times.

U eo f ::: f 2:

-

Fig 4. Cumulative Qbd distribution of bulk type polysilicon gate P-well capacitor in thick gate oxide and with different CF4 processing times.

0 01s

oolo - - 0 = 9

0005

; g 0000

-Thin N M O S A

c Th inPMOS -Thick NMOS - -FF- Thick PMOS

-

_ _ - - - - ' -

99.9 ,

0.2

5 0.1

1 0 0 - 0

D m = -0.2

5 x . 1

-hick N-wel l PMOS 0 CF4 Os c CF4305 A C F 4 6 0 5

+Thin NMOS - -+Thin P M O S

-Thick N M O S - -- -ThlckPMOS

ot.; -9-

- - I.,.:- -- _._

1.. . -

\._. - L...

0.: 1 , , , , , , , , , , , , , , _ , , , , , , ,,,,, , , , , , ,

0.1 1 10 100 1000

Charge to breakdown (Clcm')

0.1

Fig 6. Cumulative Qbd distribution of finger type polysilicon gate N-well capacitor in thick gate oxide and with different CF4 processing times.

P - w e l l N M O S CF4 Os CF4 30s CF4 60s

::: 0 1 100

Charge to breakdown (Clcm')

00

Fig 7. Cumulative QM distribution of fmger type polysilicon gate P-well capacitor in thick gate oxide and with different CF4 processing times.

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100

0 T h i n N M O S C F 4 Os 0 Thin N M O S C F 4 30s 1 A Thin N M O S C F 4 60s

F i E g B a E

10 100 1000 , 0 0 0 0 0 01

0

stres* 1,ms (.e=)

Fig 8. b degradation as a function of time in thin gate oxide NMOS under hot electron stress with different CF4 processing times.

CF4 0% Cf. 30, CF4 60%

C F 4 condition (sec)

-30 1

Fig 9. Relative percentage change of interface trap density before and after hot electron stress of thin gate oxide NMOS with different CF4 processing times.

0 T h i c k P M O S C F 4 Os c ThlCk P M O S C F 4 30s A Thick P M O S C F 4 00s

1000 10000 100000 1oc

Stress time (sec) 000

Fig 10. Threshold voltage shifts as a function of time in thick gate oxide PMOS under NBTI stress with different CF4 processing times.

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