ISSCC94 / SESSION 16 I TECHNOLOGY DIRECTIONS: MEMORY, PACKAGING / PAPER FA 16.2 --- --

FA 16.2 A 256kb Nonvolatile Ferroelectric Memory at 3V and 100ns

Tatsumi Sumi, Nobuyukr Moriwaki, George Nakane, Tetsuji Nakakuma, Yuji Judai, Yasuhiro Uemoto, Yoshihisa Nagano, Shin- ichiro Hayashi, Masamichi Azuma, Eiji Fujii, Shin-ich Katsu, Tatsuo Otsuki, Larry McMillanl, Carlos Paz de Araujol, Gota Kano

Matsushita Electronics Corp., Kyoto, Japan ’Symetrix Corp., Colorado Springs, CO

One ofthe most important features for ferroelectric material is fast write a t low voltage. This feature is used in this 256kb nonvolatile memory that operates at 3V power supply with reaawrite time of 100ns. Active current is 3mA a t 200x1s cycle time a t 3Vfor battery operation. The cell consists of 1 transistor and 1 capacitor per bit (1TlC) permitting a high level of integration. For low-voltage low-power operation, use is made of a preset reference-cell circuit, wordline boost circuits with a ferroelectric boosting capacitor and a divided-cell plate circuit.

Ferroelectric nonvolatile memory (FeRAM) is expected to be very useful not only for memory devices but also as a nonvola- tile memory on microcontroller chips. A 2-transistor and 2- capacitor per bit (2T2C) cell has been reported operating beyond 3V [l]. The lTlC cell is preferable for a system-on-chip or a highly-integrated FeRAM. A key factor for success in the lTlC cell is the design of a reference cell configuration espe- cially for low-voltage and low-power operation. Figure 1 shows the reference cell circuit used in the present memory. The reference cell has a transistor to preset a ferroelectric capaci- tor. The read timing diagram is shown in Figure 2. The difference voltage between 2 electrodes of the reference ferro- electric capacitor is kept OV by setting RBP logic “H” and a global cell plate (GCP) “ L until the wordline (WL) and the reference cell wordline (RWL) go to logic “H”. Bitline pairs are precharged to OV. When WL, RWL, GCP and local cell plate (LCP) go to the high state, charge transfers from the ferroelec- tric capacitors to the bitlines, producing a difference in bitline voltage. The charge from the reference cell is designed to be half way between those from the memory cells with logic “H“ and ”L” by adjusting the area of reference cell capacitor as shown in Figure 3, AVH=AVL. In a conventional reference cell configuration without preset transistor, if a memory cell has logic “H”, the voltage of the reference cell capacitor is a t point “ A after sensing [2]. After that, the cell plate goes from logic “H” to “1,” leaving built-in potential of about -0.7V on the electrode of the reference cell, point “B” which becomes an initial operating point for the next read cycle. When the memory cell has logic “ L , the voltage of the reference cell capacitor becomes a point “0” after sensing which results in no disturbance of the initial operating point for the next read. Because of the change of initial operation points corresponding to the memory cell logic datum, the reference cell can not be optimized and especially impairs low voltage operation, AVL’IcAVL. On the other hand in the case of this work shown in F i p r e 1, since the reference cell capacitor is preset to OV prior to read, operating margin a t low voltage is improved.

Furthermore since GCP is logic “H” when RBP goes “H, logic “ L is automatically written to the reference cell capacitors in the first write sequence of memory cells, eliminating writing of logic “ L to the reference cells. The reference cell is read many more times than a normal memory cell, but fatigue is avoided because of nondestructive read [31.

Wordlines are boosted to improve low-voltage operation Tak- ing advant.age of the high dielectric constant of the ferroelec- tric capacitor, the area of the capacitor is reduced to 1/10 of a usual gate oxide capacitance, 770pm2 for 20pF. 4.0V and 2.6V are obtained for wordline voltage a t Vdd=3.0V and Vdd=2.0V respectively.

One difference between FeRAM and DRAM is pulsing the cell plate to polarize the ferroelectric capacitor. In a FeRAM even if a wordline becomes active, connecting memory cells to bitlines, datain thecellscannotbereadifthecell plates arenot pulsed. Therefore, the cell plates can run parallel to bitlines, one or several of which are activated for access to improve power consumption [4]. The cell plate has larger area than that ofa usual interconnection because it is one of the two electrodes of a capacitor, resulting in large parasitic capacitance between the cell plate and the substrate. Pulsing the cell plate, then, increases current consumption. To solve this problem, a di- vided cell plate configuration, comprising a global cell plate line and local cell plate lines, is employed (Figure 4). A LCP is connected to 8 memory cells that are read and written simul- taneously. Since the LCPis selected and connected to the GCP through a pass transistor whose gate is connected to the worldline, no other decoder to select the LCP is necessary. The dividedeell-plate configuration reduces parasitic capacitance to U4.4, from 35pF to SpF, compared to conventional circuits. Consequently, current consumption is reduced by 0.4mA a t a cycle time of 20011s at 3V (Figure 5). The increase in chip size is 3%.

Figure 6 shows minimum operating voltage after destructive read and re-write stress of 3V. The 256kb FeRAM has almost no fatigue after lo1* read andlor write cycles. The ferroelectric capacitors are formed with a spin-on-coat method using a proprietary ferroelectric material known as Y1 [51.

Figure 7 shows a chip micrograph. The cell array consists of 4 blocks, each of which has 64kb (1024x64). ROW decoders and word drivers are between 2 blocks, and column decoders and sense amplifiers locate a t the right side of the array. Row address buffers, row predecoders and the wordline boost cir- cuits are on the left side of the chip. YO buffers, clock genera- tors and column address buffers are on the right side. Table l summarizes technology and performance of the memory.

Acknowledgments

The authors thank H. Iwasa and H. Esaki for support and encouragement, and Ramtron International Corp. for partial fabrication of the circuits.

References

[I] Womack, R., et al., -A 16kb Ferroelectric Nonvolatile Memory with a Bit Parallel Architecture”, ISSCC Digest ofTechnica1 Papers, pp. 242- 243, Feb., 1989.

[21 US Patent 4873664, S. S. Eaton, Jr., ‘Self Restoring Ferroelectric Memory“, Oct., 1989.

[31 Moazzami, R., et al., ”A Ferroelectric DRAM Cell for High Density NVRAMs”, Symposium on VLSI Technology Digest of Technical Pa- pers, pp. 15-16. Jun.. 1990.

[41 Eaton, S. S., et al. “A Ferroelectric Nonvolatile Memory”, ISSCC Digest of Technical Papers, pp. 130-131, Feb., 1988.

[51 Mihara, T., et al., Nikkei Electronics, pp. 94-100, no. 581, May 5, 1993.

ISSCC94 I FRIDAY, FEBRUARY 18,1994 I SEA CLIFF /12:15 AM

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Figure I: The STD substrate, (1) dielectric base, (2) silicon wells for sensor manufacture, (3) silicon columns from sides of substrate.

L

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I /3

Figure 2 Stagesof STDmanufacture: (1) siliconregions, (2) glass ceramic regions, (3) silicon wells for sensor manufacture.

02 t

B=O. 1 3 T

Figure 4: MST voltage-current characteristics for B=O and B=0.13T.

I=1 .OmA

I / I=0.5mA

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Figure 5: Magnetic sensitivity M vs emitter current IE for different values of the current I.

Figure 3: MSTphysicalmodel: C1, C2, collector regions; E -emitter region; jE, emitter current density; IC1, IC2, collector currents; E, internal Hall- field; I, major carrier current (Hall-detector current); Bz, normal component of magnetic field; d, Hall detector thickness; B, base leads.

Figure 6 Multitrac magnetic head, front: (1) magneto-sensitive sensor, (2) emitter leads, (3) collector leads.