Implementing FFT with Different Radix on FPGAs and Software Platform 陳羿安蔡進義

Implementing FFT with Different Radix on FPGAs and Software Platform

陳羿安蔡進義Programming Methodology Lab

IECS, Feng Chia University

RC Project Report

2

OutlineOutline

• Introduction

• Fourier transform and tensor product notation

• Design methodology

• Implementation

• Conclusion and future work

Implementing FFT with Different Radix on FPGA and Software Platform

3

IntroductionIntroduction

• To implement Cooley-Tukey FFT algorithm based on radix-2 and radix-4 for 4-point

• From software to hardware

• Transfer multistage interconnection to single stage interconnection network

• Verilog HDL and Quartus II


4

Fourier Transform and Tensor Product Notation Fourier Transform and Tensor Product Notation

• Fourier transform is used to analyze frequency component for continuous signal

• In order to compute in computer and use discrete signal, the DFT replace fourier transform

• The definition of DFT is as below:

1,,2,1,0,)()(1

0

2

NkenxkXN

nN

nkj


5


)1(

)1(

)0(

)1(

)1(

)0(

)1()1()1(0

1)1(10

0)1(00

Nx

x

x

NX

X

X

NNN

N

N

The matrix of the definition of DFT

)3(

)2(

)1(

)0(

1

1

1

1111

)3(

)2(

)1(

)0(

963

642

321

4

x

x

x

x

X

X

X

X

DFT


6


• Tensor product

• Stride permutation

33233222

13031202

01213020

11011000

32

10

32

10

yxyxyxyx

yxyxyxyx

yxyxyxyx

yxyxyxyx

yy

yy

xx

xx

5

3

1

4

2

0

5

4

3

2

1

0

62

5

4

3

2

1

0

x

x

x

x

x

x

x

x

x

x

x

x

L

y

y

y

y

y

y


7

Tensor Product FormulationTensor Product Formulation

• Cooley-Tukey FFT tensor product formulas• DIT

• FIT

n

i

n

i

iiniinn RTIIFIF1

2

2

222222)]])([([ 11

n

i

ini

in

ininn IFITIRF1

222

2

2222)]])([([ 1

)1(

1


8

The relationship between DIT and DIFThe relationship between DIT and DIF

• DIT

• DIF

xxy

1

1

0

01

11

11

xxy

11

11

11

0

01

transpose


9

Design MethodologyDesign Methodology

• Framework

• Data representation

• FFT representation on multistage interconnection network

• Transfer to single stage interconnection network


10

FrameworkFramework

Permutation

Processing Unit

Twiddle Factorcontrol

InputReal

InputImage

OutputReal OutputImage


11

Data RepresentationData Representation

7 6 5 4 3 2 1 0

sign integer fraction

+7.9375 <= data <= -7.9375

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Data1 Data2

Result

Result[14]=Data1[7]+Data2[7]


12

Data RepresentationData Representation

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Result

7 6 5 4 3 2 1 0

Data1 Data2

Result[7]=Result[7]+Data1[7]+Data2[7]


13

Multistage Interconnection NetworkMultistage Interconnection Network

twd0

twd1

twd2

twd3

twd0

twd1

twd2

twd3

X[0]

X[2]

X[1]

X[3]

Y[0]

Y[1]

Y[2]

Y[3]

00

10

01

11

Bit-reversal

00

01

10

11

Radix-2


14


Multistage Interconnection NetworkMultistage Interconnection Network

Radix-4

twd0

twd1

twd2

twd3

X[0]

X[1]

X[2]

X[3]

Y[0]

Y[1]

Y[2]

Y[3]

ii

ii

11

1111

11

1111

15

Single Interconnection NetworkSingle Interconnection Network

Radix-2

twd0

twd1

twd2

twd3

twd0

twd1

twd2

twd3

X[0]

X[2]

X[1]

X[3]

Y[0]

Y[1]

Y[2]

Y[3]

1 2 3


16

Software ImplementationSoftware Implementation

n

i

n

i

iiniinn RTIIFIF1

2

2

222222)]])([([ 11

for i=1 to n for i1=0 to 2n-i-1 for i2=0 to 2i-1-1 B0=X[i1*2i+i2]*D[i2*2n-1*0] B1=X[i1*2i+2i-1+i2]*D[i2*2n-1*1] Y[i1*2i+i2]=B0+B1

Y[i1*2i+2i-1+i2]=B0-B1

end end Swap(X,Y)end

1

21

222

iin

iji eee

Input basis:Output basis:


D

D

F2

j=0

j=1

j=0

j=1

17

Hardware ImplementationHardware Implementation

• Experimental Environment– Processor: AMD Athlon 1.11GHz– Memory: 256 MB RAM– OS: Win XP– Compiler: Quartus II– HDL: Verilog


18

Hardware ImplementationHardware Implementation

• Finite State Machine

Ready

End

Three

Two

One

start

operation 1

next stage

operation 2

operation 3

end

Implementing FFT with Different Radix on FPGA and Software Platformtwd0

twd1

twd2

twd3

twd0

twd1

twd2

twd3

1 2 3

19

SimulationSimulation

input Real binary Image binary

0.75 00001100 00000000

0.5 00001000 00000000

0.25 00000100 00000000

0.0625 00000001 00000000


decimal Real binary Image binary

1.5625 00011001 00000000

0.5-0.4375i 00001000 10000111

0.4375 00000111 00000000

0.5+0.4375i 00001000 00000111

20

VerificationVerification

0625.0

25.0

5.0

75.0

11

1111

11

1111

4375.05.0

4375.0

4375.05.0

5625.1

ii

ii

i

iY

DFT4

decimal Real binary Image binary

1.5625 00011001 00000000

0.5-0.4375i 00001000 10000111

0.4375 00000111 000000000.5+0.4375i 00001000 00000111

FFT


21

Conclusion and Future WorkConclusion and Future Work

• We make use of tensor product and interconnection network to design and implement Cooley-Tukey FFT

• We choose point-4 as our problem size and implement it based on radix-2 and radix-4

• We attempt to increase the problem size• We hope the algorithm is not only Cooley-Tukey

FFT algorithm


Documents

Implementing FFT with Different Radix on FPGAs and Software Platform 陳羿安 蔡進義

Implementing FFT with Different Radix on FPGAs and Software Platform 陳羿安蔡進義