Intégration de composants de puissance LDMOS compatibles …theses.insa-lyon.fr/publication/2010ISAL0119/these.pdf · 2016-01-11 · claquage (la jonction la plus sensible au fort

THESE

Présentée devant

L’INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON

Pour obtenir le grade de

DOCTEUR

ECOLE DOCTORALE : Electronique, Electrotechnique, Automatique Par

Mohamed ABOU EL ATTA EBRAHIM

Intégration de composants de puissance LDMOS compatibles BiCMOS pour les systèmes intelligents;

couplages substrat

Soutenance : le 17 Décembre 2010 devant la Commission d’Examen

Rapporteurs : José MILLAN Professeur IMB, Barcelone, Espagne

Jean-Louis SANCHEZ Directeur de recherche CNRS, LAAS, Toulouse, France

Examinateurs: Catherine BRU Directrice de Recherche CNRS, INSA de Lyon, France

Francis CALMON Maître de conférences, HDR, INSA de Lyon, France

Abdel-Halim ZEKRY Professeur, Universite d'Ain Shams, Egypte

Directeur de thèse: Christian GONTRAND Professeur, INSA de Lyon, France

Invité : Jean-Pierre CHANTE Professeur, INSA de Lyon, France

A THESIS

Submitted to

NATIONAL INSTITUTE OF APPLIED SCIENCE OF LYON

For the degree of

DOCTOR

Graduate School: Electronic, Electrotechnique and Automatism (EEA)

By

Mohamed ABOU EL ATTA EBRAHIM

Designing Smart Power Integrated Circuits with LDMOS devices compatible standard BiCMOS

technology; Substrate coupling

Should be Defended on the 15 December 2010, Lyon

Referees: José MILLAN Professor, IMB, Barcelona, Spain

Jean-Louis SANCHEZ Research Director, CNRS, LAAS, Toulouse, France

Examiners: Catherine BRU Research Director, CNRS, INSA de Lyon, France

Francis CALMON Assistant Professor, HDR, INSA de Lyon, France

Abdel-Halim ZEKRY Professor, Ain Shams University, Egypt

Director of the thesis: Christian GONTRAND Professor, INSA de Lyon, France

Invited : Jean-Pierre CHANTE Professor, INSA de Lyon, France

INSA Direction de la Recherche - Ecoles Doctorales

SIGLE ECOLE DOCTORALE NOM ET COORDONNEES DU RESPONSABLE

CHIMIE

LYONCHIMIE DE http://sakura.cpe.fr/ED206

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ScSo

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Résumé du mémoire de thèse

I

Intégration de composants de puissance LDMOS compatibles BiCMOS pour les systèmes intégrés

Intelligents; couplages substrat

Les circuits intégrés de puissance intelligente (CIs) qui intégrent à la fois des dispositifs de puissance à faibles pertes et des circuits de contrôle/commande, ont attiré beaucoup d'attention dans une grande variété d'applications. Ces CIs permettent d’ améliorer la fiabilité, réduire le volume et le poids, et d'accroître l'efficacité d'un système. Des efforts considérables ont été mis dans le développement des dispositifs de puissance intelligentes pour l'électronique de l'automobile, des appareils périphériques, et des équipements portables tels que les téléphones cellulaires, les caméras, etc.

La technologie « Smart PIC » devrait avoir un impact sur tous les domaines dans lesquels des dispositifs semi-conducteurs de puissance discrets sont actuellement utilisés. Elle est censée créer des applications basées sur les nouvelles fonctionnalités de contrôle/commande intelligents. Sur la figure 1, les applications de dispositifs de puissance sont présentées en fonction de la fréquence de fonctionnement.

Figure 1: Les applications de circuits de puissance intégrés intelligentes

Une bonne compréhension de la physique du transport et des modèles physiques utilisés

pour l'analyse des semiconducteurs de puissance est indispensable pour obtenir des résultats de simulation précis et pour étudier les structures nouvelles. Une meilleure étude des dispositifs haute tension (HT) et une compréhension claire des effets spéciaux sont alors nécessaires. Une étude approfondie des effets physiques qui ont lieu dans les dispositifs HT fait alors l'objet d'analyse dans le chapitre 2. L'effet de la courbure de jonction sur la tension de claquage est également expliqué et le traitement analytique du principe de réduction du champ en surface (RESURF) principe est appliqué.


II

Le concept RESURF donne le meilleur compromis entre la tension de claquage et l' « ON-résistance » des dispositifs latéraux. La technique offre la possibilité de former des dispositifs haute tension latérale en utilisant une technologie intrinsèque à basse tension.

La structure RESURF est réalisée par une diode latérale P+/N-epi et une P-sub/ N-epi

verticale, comme le montre la figure 2a. Le concept repose sur la réduction du champ électrique latéral de la P+/N-epi diode, ce qui représente le point faible de la structure pour le claquage (la jonction la plus sensible au fort champ électrique) permettant donc des tensions supérieures à appliquer.

Avec la présence de la diode verticale P-sub/N-epi et l'interaction de sa région de charge

d'espace avec la région de charge d'espace latérale, la largeur de désertion latérale Xlateff s’étale sur une plus grande distance par rapport au cas où la diode verticale n’existe pas. Par conséquent, le champ électrique latéral à la P+/N-jonction epi Elateff devient beaucoup plus faible, permettant donc des tensions plus fortes à appliquer (voir figure 2b).

(a) (b)

Figure 2: (a) Le partage de la charge d'espace résultant lorsque les deux diodes sont fusionnées, et (b) La réduction du champ électrique en raison de moindre valeur Nepieff

Les transistors MOS à double diffusion latérale (LDMOSFETs) sont devenus les

dispositifs préférés pour combiner à la fois les applications à haute tension et celles de puissance dites intelligentes. Les LDMOSFETs avec les processus VLSI ont rendu la perspective de circuits intégrés de puissance intelligente de devenir réalité. Dans le chapitre 3, une structure générale de RESURF-LDMOS est conçue à partir des simulations numériques TCAD 2D et 3D pour vérifier le concept de RESURF.

La coupe transversale de LDMOS RESURF est illustrée sur la figure 3. Dans cette

structure, la longueur effective du canal LCH est déterminé par la différence dans les diffusions latérale du P-body et la région N+-source (transistor latéral MOS double-diffusion). Ainsi, le dopage dans le canal est distribué latéralement le long de la longueur du canal de la N+-source jusqu’au point K, point qui est appelé le drain intrinsèque (la jonction métallurgique entre le P-body et les régions N-épitaxie). La longueur du canal LDMOS ne dépend que du processus (la profondeur de jonction verticale et la concentration de dopage) et non du dessin de masque du dispositif.


III

Les paramètres clés du processus/dispositif sont optimisés pour obtenir le meilleur

compromis entre RON,SP et BV. Réduire RON,SP, tout en maintenant une même tension de claquage BV a été le problème principal des composants de puissance intelligents. En appliquant le concept de la réduction du champ électrique en surface (RESURF), un meilleur compromis, entre les paramètres de performance, est atteint. La concentration épitaxiale (Nepi,opt) optimale est la concentration qui permet d’atteindre une tension de claquage maximale de la structure et donne le meilleur compromis entre cette tension de claquage et l' ON-résistance. Cela se produit en appliquant le principe RESURF pour le meilleur des cas (pour le cas optimal). La concentration épitaxiale Nepi optimale ne dépend que de l'épaisseur de la couche épitaxiale Tepi, comme le montre la figure 4.

1.0E+14

2.1E+15

4.1E+15

6.1E+15

8.1E+15

1.0E+16

1.2E+16

1.4E+16

1.6E+16

1.8E+16

0 1 2 3 4 5 6 7 8 9 10

Tepi(µm)

Nep

i,opt

(cm

-3) Nepi>Nepi,opt

Breakdown occurs at P-body/N-epi junction

Nepi<Nepi,opt

Punch-through Breakdown occurs at N+/N-epi junction

Figure 4: Nepi,opt. en fonction de Tepi

La tension de claquage (BV) et l' ON-résistance spécifique (RON,SP) de la structure LDMOS

sont présentées sur la figure 5a pour différentes concentrations de dopage épitaxial Nepi. La tension de claquage augmente en augmentant la concentration de dopage épitaxial jusqu'à Nepi = 6,0E+15 cm-3, puis elle diminue avec l'augmentation de la concentration de dopage. Ce résultat reflète bien le principe RESURF qui suggère que la tension de claquage maximale est obtenue à Nepi,opt (voir figure 4). La distribution du champ électrique est donnée sur la figure 5.b, pour trois valeurs différentes de Nepi. Pour Nepi = 2,0E+16 cm-3, (un champ électrique

Figure 3: Coupe schématique de la LDMOS RESURF


IV

élevé est observé au bord de la grille et seulement un faible champ électrique se trouve au bord du drain). Pour l'autre cas extrême, lorsque Nepi = 1,0E+14 cm-3, on peut remarquer que la pente de l'évolution du champ électrique change de signe ce qui signifie que le type de dopage de la région de dérive est modifiée. Ainsi, la jonction P-body / N-epi n'est plus critique. Pour Nepi = 6,0E+15 cm-3, le champ électrique est uniformément réparti le long de la région de dérive.

50

100

150

200

250

300

350

400

450

1.0E+14

5.0E+14

1.0E+15

5.0E+15

6.0E+15

8.0E+15

1.0E+16

1.2E+16

1.5E+16

2.0E+16

Nepi (cm-3)

BV

(V)

0.00

0.05

0.10

0.15

0.20

0.25

RO

N,S

P (Ω

.cm

2 )

Breakdown voltage

The specific ON-resistance

(a) (b) Figure 5: (a) BV and RON,SP , and (b) distribution du champ électrique pour différentes Nepi

Pour l'objectif général des structures 2D et 3D de l'RESURF-LDMOS décrites dans le

chapitre 3, les résultats montrent un excellent compromis RON,SP/BV de 9,5mΩ.cm2 / 400V. Le courant maximal de drain obtenu en simulation est de 1,8 mA/µm à une tension de grille de 5V. En outre, la variation de VK en fonctions de la tension de drain et la tension de la grille est déduite. Pour expliquer l'intérêt de point K, l'architecture du dispositif doit être prise en compte. De plus, il a été démontré que le dispositif MOS intrinsèque se comporte comme un MOSFET basse tension, et que le potentiel de point K reste faible même si VDS et VGS sont élevées. Clairement, cette tension en liaison avec celle appliquée à la grille donne le régime de fonctionnement du transistor MOS intrinsèque.

De plus, la corrélation entre les variations de capacités et de la tension de drain intrinsèque

VK est démontrée dans la dernière partie du chapitre 3. Ces capacités sont exprimées comme

suit: GS

GGS dV

dQC = ,

GD

GGD dV

dQC = , où, QG représente la charge de grille. Dans la structure simulée,

la source et le corps (body) sont connectées, ce qui est souvent l’usage. La figure 6.a montre la variation de CGS en fonction de VGS. À tension de drain très faible, cette dépendance est similaire à celle obtenue pour un transistor MOS à faible tension et à basse fréquence (quasi-statique). On peut facilement remarquer que le passage de l'appauvrissement de la couche d'inversion se produit autour de VGS = 0,75 V, qui est la valeur de la tension de seuil. Contrairement au cas d'un transistor MOS classique, ces dispositifs présentent des variations tout à fait différentes de la capacité CGD.


V

(a) (b)

Figure 6 : (a) CGS dependence sur VGS, et (b) CGD dependence sur VGS La conception et l'optimisation des LDMOSFETs utilisant la technologie BiCMOS 0,35

μm semblable à celle fournie par ST Microelectronics font l'objet du chapitre 4. (Une légère modification est apportée aux LDMOSFETs par rapport à la technologie de base). Deux masques supplémentaires sont utilisés pour le corps et pour la formation des régions de dérive en ajoutant un faible budget thermique et sans recours à des implantations de haute inclinaison. La tension de claquage du nLDMOS proposé ne dépend pas de l'épaisseur de la couche épitaxiale comme dans les LDMOS RESURF classiques du chapitre précédent et le dispositif proposé est donc intégrable avec le CMOS basse tension avec des couches épitaxiales superficilles.

La coupe schématique du nLDMOS proposé est illustrée à la figure 7.a. L'impact de

l'épaisseur de la région de dérive est illustré à la figure 7.b. On remarque que la tension de claquage n’est que légèrement changée, ce qui confirme que le claquage n'est pas une fonction de l'épaisseur de dérive. La tension de claquage dépend uniquement des propriétés de la jonction métallurgique Pwell / N-enterrée. Ce résultat est contraire au cas des LDMOSFETs RESURF classiques, qui ont des tensions de claquage dépendant de l'épaisseur de la région de dérive. Cette dépendance limite l'intégration de ces dispositifs avec les circuits CMOS basse tension qui utilisent des epi-couches minces comme dans la technologie BiCMOS.

80

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84

0.6 1.1 1.6 2.1

TDrif t (µm)

BV (V

)

0E+00

1E-03

2E-03

3E-03

4E-03

RON

,SP (

Ω.c

m2 )

Breakdown voltage


(a) (b)

Figure 7 : (a) La coupe schématique du nLDMOS proposé , et (b) BV et RON,SP pour les différents TDrift

La coupe schématique du pLDMOS proposé est montrée sur la figure 8.a. L'impact de l'épaisseur de la région de dérive est illustré à la figure 8.b. Il est évident que la tension de claquage et la résistance spécifique dépendent fortement de l'épaisseur. La tension de claquage obéit au principe RESURF et atteint sa valeur maximale à l'épaisseur qui donne la dose optimale de dérive.


VI

Yes No

Yes No

Zone I Rdep

Zone II Rdr

JFET pinch-off

Zone I It=Ib+Iacc

Zone II Rdr

Zone II It=Ib

Zone III Rdr

Nonaccumulated case

Accumulated case

Zone I It=Ib+Iacc

-140

-130

-120

-110

-100

-90

-800.65 0.75 1.30 2.00 2.50

TDrif t (µm)

BV

(V)

5.0E-4

1.0E-3

1.5E-3

2.0E-3

2.5E-3

3.0E-3

RO

N,S

P (Ω

.cm

2 )

Breakdown voltageThe specific ON-resistance

(a) (b)

Figure 8 : (a) La coupe schématique de la pLDMOS proposé , et (b) BV et RON,SP pour les différents TDrift

Les dispositifs LDMOS développés sont optimisés grâce à des outils avancés de TCAD. L'ON- résistance spécifique (RON,SP) et la tension de claquage à l'état bloqué (BV) des dispositifs proposés sont de 1,5 mΩ.cm2 et 62V, respectivement pour l'nLDMOS et de 3,0 mΩ.cm2 et 160V, respectivement pour le pLDMOS . Ainsi, Les composants peuvent généralement être utilisés pour une tension d'alimentation de 42V, valeur adaptée aux applications futures de l'automobile. Les simulations TCAD numériques sont utilisées pour obtenir les caractéristiques DC et AC des dispositifs proposés. Le courant maximal de drain obtenue en simulation à la tension de grille absolue de 3,3V est de 0,42 mA/μm pour le nLDMOS et 0,135 mA/μm pour le pLDMOS.

La modélisation des structures latérales entrent en jeu lorsqu’elles sont intégrées dans les

technologies standards. Des progrès remarquables dans le domaine de la modélisation ont permis des approximations géométriques de la zone de drift (approche régionale), qui semble être l'approche la plus prometteuse. Le modèle analytique de la partie MOS intrinsèque et la zone de drift est l'objet du chapitre 5. Dans la première partie de ce chapitre une approche pour la modélisation physique de la partie MOS intrinsèque et la région de dérive est présentée. Les effets de la saturation de vitesse, la réduction de la mobilité, et la concentration d'impuretés non uniforme dans le canal sont considérés. Les charges des dispositifs sont calculés et intégrées pour offrir des expressions analytiques des courants. Le diagramme de la méthode de modélisation dans la région de dérive, présentant des différents cas, est illustré à la figure 9:

Figure 9: Modélisation graphique des flux

VGS-VFBdr >VK

VGS-VFBdr >VK1


VII

La deuxième partie du chapitre présente l’implantation du modèle analytique en utilisant les programmes MATLAB et MAPLE. Les approximations électriques qui doivent être prises en compte pour établir le modèle statique sont également expliquées. A l'aide du modèle d'analyse proposé, un modèle SPICE est développé. Les paramètres du modèle sont extraits en utilisant les outils d'extraction de ICCAP et ISEExtract. Le schéma du modèle du sous-circuit du LDMOS proposé est illustré à la figure 10.

Intrinsic MOS

G

S

KRDrift VDD

Figure 10: Un modèle approximatif analytique statique de LDMOS

Nous utilisons le modèle MOS SPICE niveau 3 pour implémenter les MOSFETs basse

tension et la partie MOS intrinsèque du LDMOS. Les outils ICCAP et ISExtract permettent l’extraction des paramètres du modèle SPICE en utilisant les résultats de(s) simulation(s) TCAD comme une entrée à ces outils (comme des données mesurées). Le modèle SPICE utilisé est simple, avec un petit nombre de paramètres par rapport aux modèles BSIM. Ses paramètres sont faciles à extraire en utilisant les outils d'extraction. Les caractéristiques ID -VDS et ID -VGS sont utilisées pour extraire les paramètres du modèle, avec la source liée à la masse. La comparaison des simulations TCAD et de la simulation du modèle SPICE est indiquée sur les figures 11, pour les deux cas de nLDMOS et pLDMOS. A température ambiante, la précision est supérieure à 95% pour toute la gamme de tensions étudiées.

(a) (b)

Figure 11 : Comparaison de la simulation TCAD (courbes noires continues) et le modèle de simulation SPICE (courbes pointillées rouges)

Un circuit d'interface pour convertir le niveau logique bas 0/3,3 V au niveau de haute

tension 0/42 V, adapté pour les applications futures de l'automobile, est présenté figure 12.a. Nous devons vérifier que la tension aux bornes de chaque transistor doit être plus petite que sa tension de claquage. M9 et M10 constituent un inverseur cLDMOS. Les transistors M3 à M8, constituant le circuit de décalage de niveau, amène le potentiel VG de M9 à (VDDH-VDDL) / VDDH et VG de M10 à 0/VDDL. M1 et M2 est un inverseur CMOS. En simulation, une tension d'entrée carré de fréquence 20 MHz, temps de montée et de descente de 2 ns, tension crête de


VIII

3,3 V, est appliquée sur la grille de l'inverseur CMOS (M1 et M2). Les signaux d’entrée et de sortie sont présentés sur la figure 12b.

(a) (b)

Figure 12 : (a) Le circuit schématique du circuit d'interface, et (b) Chronogrammes Dans le chapitre 6, deux technologies sont proposées pour implémenter les circuits

intégrés SMART POWER. Le premier est l'intégration planar en utilisant la technique d’isolation par tranchée profonde (DTI), et le deuxième est l’intégration par empilement 3D en utilisant les vias TSV. Par consequent, le chapitre est divisé en deux parties; dans chaque partie, nous étudions l'impact des perturbations du substrat causées par les signaux HT sur les performances des dispositifs MOS basse tension.

Dans la première partie, un mécanisme d'isolement est suggéré, utilisant une tranchée

profonde remplie par du dioxyde de silicium et du silicium polycristallin non dopé. Le silicium polycristallin se dépose de manière presque parfaite, c'est-à-dire les remplissages à la fois du haut et du bas sont à 100%. En utilisant cette technique d'isolation, le rapport d’injection collectée α est réduit par un facteur compris entre 3 et 8,5, et les variations dynamiques des courants et des tensions des circuits CMOS dues à un signal (0/42V) peuvent être tolérées en vertu de règles de conception spécifiques. Ce régime d'isolement est adapté à un environnement automobile drastique. L’isolation par tranchée profonde est utilisé pour réduire la distance d'isolation entre les dispositifs de puissance, ainsi qu’entre le dispositif de puissance et les composants CMOS basse tension, et de réduire donc la superficie totale d’une puce (voir figure 13). Les caractéristiques des états OFF-ON ne sont pas modifiées par l’introduction de ces tranchées.

Figure 13: La structure de cLDMOS et CMOS avec une isolation tranchée profonde

cLDMOS CMOS


IX

Ces dernières années, il y a une technologie émergente; l’intégration trois dimensions (3D, Cette technologie utilise des via traversant le silicium (Through-Silicon-Via: TSV) et des couches de redistribution (ReDistribution Layers: RDL) pour interconnecter plusieurs couches de circuits actifs, empilées. L’intégration 3D offre des améliorations significatives par rapport aux circuits 2D, sur les performances, la fonctionnalité et la densité d'intégration. En réduisant la longueur des interconnexions globales de manière significative, l'intégration 3D promet une solution aux problèmes de retard (sévère) qui sont, et seront rencontrés, lors des processus de réduction géométrique. En outre, l'intégration 3D offre de nouvelles architectures pour les CI sophistiqués et facilite l'intégration de matériaux hétérogènes, des composants, et des signaux, permettant la réalisation de systèmes sur puce (SoC) étendus.

Dans la technique d'intégration 3D empilée, la simulation TCAD 2D et 3D basée sur un

couplage TSV ou RDL est étudiée sur le nMOSFET, le pMOSFET, et les régions sensibles de l'inverseur CMOS. Les transistors MOS fonctionnent en mode statique et un signal carré (f = 200 MHz, 200 ps, 42,0 V tension de crête) est ensuite appliquée sur le TSV ou/et sur la RDL. Dans le NMOS le couplage du substrat a un effet négligeable sur les performances électriques, mais dans le PMOS, le TSV a un fort impact.

L'impact du TSV sur le fonctionnement de l’inverseur CMOS est scruté en utilisant la

simulation en mode mixte (modèles SPICE pour les dispositifs CMOS et la méthode des éléments finis (MEF) pour les régions substrat de ces dispositifs). Cet impact dépend de l'emplacement du TSV: près de la région active de type n du MOS ou de la région active pMOS. Dans le premier cas, il n'y a pas de variations observées dans le rendement électrique du CMOS à cause du signal carré HT. Mais dans ce dernier cas, et avec un substrat pMOS flottant, il y a une forte incidence sur les performances du CMOS, pouvant être diminuée par l'ajout d’un anneau de garde P+ entre le dispositif PMOS et le TSV. Cette région est implémentée en utilisant le même masque de la zone active de type n du MOS Pwell ; alors, il n'y a pas de coût supplémentaire pour la mise en œuvre de ces régions d’isolation.

Nous utilisons le simulateur de Sentaurus; Sentaurus est un logiciel basé sur la méthode

des éléments finis (FEM) pour l'étude « composant » et sur des modèles de type SPICE (cf. lois de Kirchhoff) pour les dispositifs CMOS reliés au substrat. Le TSV a une forme cylindrique remplie de cuivre et d'oxyde d'épaisseur TOXTSV = 0,5μm, comme illustré sur la figure 14. Afin de simplifier l'étude, on suppose seulement un couplage entre le TSV et le NMOS. Le transistor NMOS est placé près du TSV comme l'illustre la figure 14.

Figure 14:Section carrée 3D du TSV-CMOS: couplage en mode mixte


X

Une coupe transversale selon l’axe Y de la distribution de tensions est montrée sur la figure 15.a, pour vin = 0,0/1,2V et vTSV = 0,0/42,0V. Les signaux d’entrée et de sortie de la TSV, entrée CMOS et des tensions de sortie et la sortie sous forme d'onde de courant (le courant dans/à travers le condensateur de charge) sont présentés figure 15.b. Il est clair d’après cette figure que le courant commute selon la forme d'onde du, et il n'y a pas d'effet de la HT sur le TSV.

(a) (b)

Figure 15: (a) Y coupe distribution de potentiel, et (b) Les tensions et les formes d'onde de sortie de courant à vin = 0.0/1.2V and vTSV = 0.0/42.0V

Par ailleurs, nous initions une étude physique prospective sur les dispositifs empilés dans

les circuits 3D, dans la gamme des radiofréquences; en l’occurrence, on scrute la propagation des ondes électromagnétiques le long de certaines interconnections pouvant présenter des discontinuités. Cette étude se fait dans le domaine temporel: une méthode aux différences (FDTD: Time Domain Finite Differences) est appliquée à l'analyse de certains via flanqués, par exemple, de deux « striplines », le tout enfoui dans le silicium. La distribution du champ électrique et magnétique, les paramètres de transmission et de réflexion, et la propagation des impulsions le long d’un via sont présentés. La structure 3D proposée utilisée dans cette étude est montrée sur la figure 16.

Figure 16: Système de VIA et striplines 3D-structure

i

Abstract The evolution of smart power technology offers a variety of advantages in terms of

reliability, reduction of interfaces, and reduced weight and size of the components. The basis for smart power technology is the integration of low voltage circuitry with power devices.

The first goal of the thesis is to design, analyze, and model lateral double diffused MOSFETs (LDMOSFETs), which are suitable for smart power applications. New device structures with recently developed novel device concepts are studied and suggested. The proposed devices are implemented in 0.35µm BiCMOS technology standard layers provided by STMicroelectronics. Also, new technologies are suggested to implement the SPICs.

Clear understanding of the transport physics and physical models used for the analysis of power semiconductors is essential to obtain accurate simulation results and to study new device structures. A better investigation of the HV devices and clear understanding of the special effects is then needed. The intrinsic drain voltage concept (K-point voltage, VK) is proposed and its variation is explained and related to the charge variation and the physical effects inside the device. The K-point voltage is used as a tool to investigate the saturation mechanisms of LDMOS. Once again, the correlation between the capacitances' variations and the intrinsic drain voltage VK is demonstrated. It is clarified that the formation of the conductive channel in the drift zone is responsible for the decrease of both VK potential and capacitances.

The main performance parameters of the lateral power semiconductor devices are the specific ON-resistance (RON,SP), the breakdown voltage (BV), and the safe operating area (SOA). RON,SP and BV are inversely related to each other. Reducing RON,SP while maintaining a BV rating has been the main issue of smart power devices. By applying the REduced SURface Field (RESURF) concept and using a drain buffer layer, best trade off among the performance parameters is achieved. For the general purpose 2D and 3D structures of the buffered RESURF-LDMOS described in chapter 3, the results show excellent RON,SP / BV trade-off of 9.5mΩ.cm2/ 400V. The maximum drain current obtained in the simulation is 1.8 mA/µm at a gate voltage of 5V.

Lateral power semiconductor structures are widely used in smart power automotive and

consumer applications. By using the standard layers of 0.35µm BiCMOS technology (STMicroelectronics technology-like), an nLDMOS and a pLDMOS are developed by slight modifications of the base technological steps. Extra two masks are used for the body and the drift regions formations with slightly added thermal budget and without resorting to high-tilt implants. The body regions doping concentrations of nLDMOS and pLDMOS are tuned to obtain threshold voltages matched with that of the low voltage MOS devices implemented in the same BiCMOS technology. Also, the drift region doses are tuned for optimum RESURF’ing condition. The developed LDMOS devices are optimized using advanced TCAD tools. The specific ON-resistance (RON,SP), and the OFF-state breakdown voltage (BV), of the proposed devices are 1.5 mΩ.cm2 and 62V, respectively for the nLDMOS and 3.0 mΩ.cm2 and 160V, respectively for the pLDMOS. So, the devices can typically be operated around 42V supply voltage, which is suitable for the future automotive applications.

The TCAD numerical simulations are used to obtain the DC and AC characteristics of the

proposed devices. The maximum drain current obtained in the simulation at absolute gate voltage of 3.3V is 0.42 mA/µm for nLDMOS and 0.135 mA/µm for pLDMOS.

ii

An analytical model for the intrinsic MOS part and the drift part is presented. The electrical approximations that have to be taken into account to build the DC model are also explained. With the help of the proposed analytical model, a Spice model is developed and its parameters are extracted using a system that links the ICCAP and ISExtract extraction tools with the results of the ISE-TCAD tools. The simulation results using the Spice model are compared to the results provided by ISE-TCAD tools. The accuracy at room temperature is less than 5% for the whole voltage domain. Finally, An interface circuit, to convert 0.0/3.3 V to 0.0/42.0 V, suitable for automotive applications is proposed

Two technologies are proposed to implement the smart power integrated circuits. The first

is the planar integration using the deep trench isolation (DTI) technique, and the other one is the new stacked 3D integration using through-silicon vias (TSVs) and re-distribution layers (RDLs). Deep trenches filled with silicon dioxide and undoped polysilicon are suggested to achieve the electrical isolation between the power devices as well as between the power devices and low-voltage CMOS parts. The polysilicon has a nearly perfect conformal deposition, that is, both step coverage and bottom coverage are 100%. By using this kind of isolation technique, the injection collected ratio α is reduced by a factor between 3 and 8.5, and the dynamic variations on the currents and the voltages of the CMOS parts due to a (0.0/42.0V) signal, can be tolerated under specific design rules. This isolation scheme is suitable for the automotive harsh environment. The impact of the HV output signal from the cLDMOS drain on the operation of the CMOS inverter using mixed-mode simulation is performed using SENTAURUS-TCAD package. The CMOS output is a function of input waveform and there is no effect of the digital HV output of the cLDMOS.

In the stacked 3D integration technique, Two and three-dimensional TCAD-based simulation of TSV or RDL induced coupling- is investigated on nMOSFET, pMOSFET, and the sensitive regions of the CMOS inverter.The MOS transistors are plugged on their static mode and a square voltage (f = 200 MHz, 200 ps-long rise and fall ramp time, 42.0 V peak voltage) is then applied on the TSV or on the RDL. In nMOS the substrate coupling has insignificant effect on the electrical performance but in pMOS, the TSV has a strong impact. The impact of the TSV on the CMOS inverter operation is performed using mixed mode simulation (SPICE models for the CMOS devices and the finite element method (FEM) for the bulk regions of the devices). This impact is dependent on the location of the TSV; near the nMOS active region or the pMOS active region. In the former case, there are no variations observed in the electrical performance of the CMOS due to the HV square signal. But in the latter case, and with floating pMOS bulk electrode, there is a strong impact on the performance of the CMOS, which can decreased by adding P+ guard-ring between the pMOS device and the TSV. This region is implemented using the same mask of the nMOS Pwell active area so; there is no extra cost for the implementation of these guard regions.

On another hand, we begin to study for the sake of future studies on stacked devices in 3D

circuits, in the radiofrequency range, the propagation of electromagnetic waves along some interconnections with discontinuities. This study is done in the time domain: a Finite-Difference Time-Domain (FDTD) method is applied to the analysis of some via flanked by two striplines, all being embedded in silicon. Electric and magnetic field distributions, transmission and reflexion parameters, and pulse propagations along transverse via are presented.

iii

Contents Abstract …………………………………………………………………...……………. i Contents ...………………………………………………………………...……………. iii List of figures……………………………………………………………...……………. viii List of tables. ………...…………………………………………………...……………. xiv List of abbreviations........………………………………………………...……………. xv List of symbols...……...…………………………………………………...……………. xvii General Introduction……..……………………….…………………………………… 1 Chapter 1: State of art of SPICs……………….……...……….……………………… 7 1.1 Introduction ………………………………………………………………..……... 9 1.2 Smart power integrated circuits (PIC) applications…..………………………...… 9

1.2.1 Flat panel displays……………………………………………..……………. 10 1.2.2 Computer power supplies and disk drivers ………………………………… 10 1.2.3 Variable speed motor drives……………………………….……………..…. 10

1.2.4 Factory automation……………………………………………...……….….. 11 1.2.5 Telecommunications…………………………...……………………….…... 11 1.2.6 Appliance controls……………………………………………..……………. 12 1.2.7 Consumer electronics……………………………………….………………. 12 1.2.8 Lighting controls…………………………………………….……………… 12 1.2.9 Smart house…………………………………………………………….....… 12 1.2.10 Aircraft electronics (Avionics)………………………………..…………… 12 1.2.11 Automotive electronics…………………………………………………..… 12

1.3 Historical view of the power devices…..…………………………………………. 13 1.4 Smart PIC fabrication processes………………………………………..………… 15 1.4.1 Dedicated processes………………………………………………………… 15

1.4.2 Compatible processes………………………………………………..……… 15 1.5 Isolation techniques……………………………………………………….……… 15

1.5.1 Self isolation (SI)……………………………………………………...…….. 16 1.5.2 Dielectric isolation (DI)……………………………………………..………. 16 1.5.3 Junction isolation (JI)…………………………………………………..…… 16 1.5.4 Advanced junction isolation techniques…………………………………..… 16 1.5.4.1 Passive JI……………………………………………………...…….. 17 1.5.4.2 Active JI …………………………………………………….……… 17

1.5.4.3 Active pull-down protection…………………………………..……. 18 1.5.4.4 Multiple structures……………………………………………..…… 18 1.6 Conclusion………………………………………..……………………….……… 18 Chapter 2: Physics of lateral HV devices …………………………..………………... 19 2.1 Introduction............................................................................................................. 21 2.2 Device characteristics for power semiconductor devices ………………..……… 21 2.2.1 Avalanche generation………………………………………………….…… 21

2.2.2 Breakdown voltage and ON-resistance relationship……………..……….… 22 2.3 Junction edge effects ……………………………………………………….……. 23

2.3.1 Cylindrical junction ……………………………………………………...…. 23 2.3.2 Spherical junction ………………………………………………...……..….. 24

2.4 Planar junction breakdown improvement ………………………………..……… 25

iv

2.4.1 Planar junction with field-plate ………………………………..……………. 25 2.4.2 Junction termination extension …………………………….……………..… 25 2.5 MOS interface physics …………………………………………...…………..….. 26

2.5.1 The threshold voltage …………………………………………………..…... 27 2.5.2 MOSFET capacitances ……………………………….…………………..… 28

2.6 A safe operation area ……………………………………..…………………...…. 31 2.6.1 Short-term SOA …………………………………………………...………... 31 2.6.1.1 Electrical effect …………………………………………………..…. 31

2.6.1.1.1 Kirk effect ……………………………………………...… 31 2.6.1.1.2 Parasitic BJT action ………………………………………. 32 2.6.1.2 Electrical–thermal effect ……………………………….…………... 32

2.6.1.2.1 Thermal effect.………............................................………. 32 2.6.1.3 Electrical–thermal coupling …………………………..….......….…. 33 2.6.1.4 Self-heating ………………………………………………..…….…. 33

2.6.2 Long-term SOA ………………………………………………..………..….. 33 2.6.2.1 Hot-carrier effect………………………………………………..…... 33

2.7 RESURF principle…………………………………………….……………..…... 33 2.7.1 Analysis of the RESURF principle…………………………………………. 34 2.7.2 Conditions of the RESURF principle.……………………………………… 37 2.7.3 Double-RESURF effect…………………………...……………………..…. 39 2.7.3.1 Theory and analysis…………...………………………………….… 39 2.8 Conclusion………………………………………..……………………….……… 41 Chapter 3: Designing RESURF LDMOS ………….……….….…………..…...……. 43 3.1 Introduction…………………………………………………………………..…... 45 3.2 The RESURF LDMOS structure…………………………….………………..…. 45 3.3 RESURF LDMOS design…………………………………………..……………. 46 3.3.1 The optimum epitaxial doping concentration (Nepi,opt)…….……………….. 46 3.3.2 The minimum channel length (LCHmin)……….….....……....…….…………. 47 3.3.3 The specific ON-resistance (RON,SP )………………………...…….………... 49 3.4 RESURF LDMOS parametric analysis ……………..………………….…..…… 49 3.4.1 Effect of the epitaxial doping concentration (Nepi)…………...…..…….…... 50 3.4.2 Effect of the drift length (LDrift)……………..……………………….….…... 52 3.4.3 Effect of Tepi for Ldrift =17.5µm…………………………………………….. 54 3.4.4 Effect of Psub for Nepi = 6.1E+15 cm-3 and Ldrift =17.5µm…………..…..…. 54 3.4.5 Effect of LACC for Nepi = 6.1E+15 cm-3 and Ldrift =17.5µm……….……..…. 55 3.4.6 Effect of LGFP for Nepi = 6.1E+15 cm-3 and Ldrift =17.5µm……….……..…. 56 3.4.7 Effect of LDFP for Nepi = 6.1E+15 cm-3 and Ldrift =17.5µm………..……...... 57 3.4.8 Effect of P-body doping on the threshold voltage.…………..…..…...…….. 58 3.5 The technological steps of the Buffered RESURF-LDMOS …………………..... 58 3.6 The ON-state characteristics of Buffered RESURF-LDMOS………………..….. 61 3.6.1 The intrinsic-drain VK………………………………………...……..……… 61 3.6.2 DC effects in Buffered RESURF-LDMOS………………….……………... 62

3.6.2.1 Saturation............................................................................................ 63 3.6.2.2 Quasi-saturation.................................................................................. 63

3.6.3 DC characteristics of Buffered 3D LDMOS………………………………... 64 3.6.4 AC effects in LDMOS …………………………………………..…………. 65 3.6.4.1 C-V curves and charge distribution…………….….………….……. 65 3.7 Conclusion………………………………………..……………………….……… 67

v

Chapter 4: Designing LDMOSFET in 0.35µm BiCMOS technology ……....……… 69 4.1 Introduction…………………………………………………………………..…... 71 4.2 The standard layers of 0.35µm based BiCMOS technology………………….…. 71 4.3 CMOS inverter………………………………………………………………….... 72 4.3.1 CMOS doping profiles……………………………………………………… 75 4.3.2 The static characteristics…………………………………………………..... 75 4.4 Design of nLDMOS in 0.35µm BiCMOS technology…………………..………. 75 4.4.1 The nLDMOS structure…………………………………………………….. 76 4.4.2 Parametric analysis of nLDMOS …………..……………………………..... 79 4.4.2.1 Impact of Drift thickness (TDrift)…………………………………….. 79 4.4.2.2 Impact of Pwell spacing length (LS)………………………………… 81 4.4.2.3 Impact of Drift length (LDrift)……………………………………..…. 82 4.4.2.4 Impact of Pwell thickness (Tpwell)…………………………………… 82 4.4.2.5 Impact of Pwell doping concentration (Pwell)……...………………... 83 4.5 Design of pLDMOS in 0.35µm BiCMOS technology………..……………….… 85 4.5.1 The pLDMOS structure………………………………………………….…. 85 4.5.2 Parametric analysis of pLDMOS …..……………………………………..... 86 4.5.2.1 Impact of Drift thickness (TDrift)…………………………………….. 87 4.5.2.2 Impact of Drift length (LDrift)………………………………………... 88 4.5.2.3 Impact of Pdrift doping concentration (PDrift)……………………….. 89 4.6 The ON- state characteristics of nLDMOS…………..…………………………... 89 4.6.1 The static characteristics ………………………………………………….... 89 4.6.2 Thermal characteristics ……………. .….…………………………...……... 92 4.6.3 AC effects in nLDMOS……………...……………………………..……..... 92 4.7 The ON- state characteristics of pLDMOS………………………………………. 93 4.7.1 The static characteristics……………………………………………………. 93 4.7.2 Thermal characteristics …………….……………………….……………… 95 4.7.3 AC effects in pLDMOS…………...………………………………………... 96 4.8 Conclusion………………………………………..……………………….……… 97 Chapter 5: Modeling of LDMOS ….……………...…………………………………... 99 5.1 Introduction………………………………………………………………………. 101 5.2 Analytical modeling of LDMOS………………………………………………... 101 5.2.1 Channel region model………………………………………………………. 101 5.2.1.1 Threshold voltage…………………………………………………… 102 5.2.1.2 Channel current……………………………………………………… 103 5.3 Drift region model……………………………………………………………….. 104 5.3.1 The accumulated case………………………………………………………. 104 5.3.1.1 Case of VGS -VFBdr <Vk1……………………………………………... 104 5.3.1.2 Case of VGS -VFBdr >Vk1……………….…………………………….. 107 5.3.2 The non-accumulated case………………………………………………….. 107 5.3.3 Dynamic behaviour…………………………………………………………. 108 5.4 The proposed subcircuit model…………………………………………………... 109 5.5 Simulation of the analytical model……………………………………………..... 109 5.5.1 The intrinsic MOS characteristics………………………………………...… 110 5.5.2 The accumulated resistance (Racc) of the LDMOSFET…………………..… 111 5.5.3 The total drift resistance (Rdrift) of the LDMOSFET……………………..… 112 5.6 Implementation of the model into Spice……………………………..……….….. 113 5.6.1 Spice model parameters of the low voltage MOSFETs…………...……..…. 113 5.6.2 Spice model parameters of the high voltage LMOSFETs………..………… 113

vi

5.6.3 The interface circuit……………………………………………………….... 115 5.7 Conclusion………………………………………..……………………….……… 117 Chapter 6: Substrate Coupling in Smart Power Integration……………………….. 119

6.1 Introduction ………………....……………………………..………………..…… 121 Part I: Smart Power Integration using Deep trench isolation technique……………... 121 6.2 Deep trench isolation technology………………………………………………... 121

6.3 Deep trench isolation structure ………….…………....……………………..…… 121 6.4 LDMOSFETs performance with deep trench isolation………………………….. 122

6.4.1 OFF-state performance ……………………………………...……….…...… 122 6.4.2 ON-state performance………………………………………………………. 124

6.5 Parasitics suppression in smart power ICs with deep trench………..………….... 124 6.6 HV dynamic signal impact on CMOS devices ………..……………………….... 126

6.6.1 Impact on nMOS……………………………………………………………. 127 6.6.1.1 Effect of DTI length (LDTI)………………………………………….. 129 6.6.1.2 Effect of DTI spacing (LS)………………………………………….. 129

6.6.2 Impact on pMOS……………………………………………………………. 129 6.6.2.1 Effect of DTI length (LDTI)…………………………………………. 131 6.6.2.2 Effect of DTI spacing (LS)………………………………………….. 131

6.6.3 Impact on CMOS sensitive regions…………………………………………. 133 6.6.3.1 The electro-thermal simulation……………………………………... 133

6.7 Mixed-mode CMOS-substrate coupling simulation……………………………... 134 6.7.1 Simulation with floating nMOS bulk-electrode…………………………….. 134 6.7.2 Simulation with floating pMOS bulk-electrode…………………………….. 135

Part II: Smart Power Integration using stacked 3D-technology……......…………….. 136 6.8 From 2D planar integration to 3D integration……………………………………. 136

6.8.1 3D ICs with through silicon (TSV) or interplane vias…….........…………... 137 6.9 3D Smart Power integration……………………………………………………… 138

6.9.1 Impact of TSV and RDL on nMOS…………………………………………. 139 6.9.1.1 The impact of TSV (RDL is floating)………………………………. 140 6.9.1.2 The impact of RDL (TSV is floating)………………………………. 142 6.9.1.3 Impact of TSV and RDL……………………………………………. 142

6.9.2 Impact of TSV and RDL on pMOS…………………………………………. 143 6.9.2.1 The impact of TSV (RDL is floating)………………………………. 143 6.9.2.2 The impact of RDL…………………………………………………. 147 6.9.2.3 Impact of TSV and RDL……………………………………………. 147

6.9.3 Impact of TSV and RDL on CMOS………………………………………… 149 6.10 TSV-CMOS mixed mode Coupling…………………………………………….. 149

6.10.1 2D TSV-CMOS mixed mode Coupling…………………………………… 150 6.10.1.1 The TSV in the nMOS side………………………………………... 150 6.10.1.2 The TSV in the pMOS side……………………………………....... 151

6.10.1.2.1 The bulk contact of the nMOS is floating…………........ 151 6.10.1.2.2 The bulk contact of the pMOS is floating……………… 152 6.10.1.2.3 Effect of P+ guard-ring…………………………………. 153

6.10.2 3D TSV-CMOS mixed mode Coupling…………………………………… 154 6.11 Electromagnetic impact of TSV in RF range …………………………………... 155

6.11.1 The Finite-Difference Time-Domain (FDTD): brief recall ……………….. 156 6.11.2 Via structure …………………………………………….………………… 157

6.12 Conclusion……………………………………..…………..…………….……… 160

vii

General Conclusions and Future work………...………………….………………...... 161 7.1 General Conclusions………..……………………………………………………. 163 7.2 Future work……………………..………………………………………………... 165

References……………….…………………………………………………………..….. 167 My scientific Production……….………………………………...………..…………... 178

viii

List of figures

Figure 1.1 Applications of power devices…..…………..……………………...…… 10 Figure 1.2 System ratings of power devices……………..……………………….…. 11 Figure 1.3 V-groove MOSFET structure…….………………………………....…… 13 Figure 1.4 VD-MOSFET structure……….....…………….................................…… 13 Figure 1.5 U-MOSFET structure………...………...…..……………………..……... 14 Figure 1.6 LDMOSFET structure………………………………………………..….. 14 Figure 1.7 Dielectric isolation…………..……………..………………………….… 16 Figure 1.8 Standard junction isolation…………………………………………..…... 16 Figure 1.9 Passive junction isolation…………………….……………………..….... 17 Figure 1.10 Active junction isolation……………………………………..………….. 17 Figure 2.1 Reverse biased P-N+ junction. ……………………………………..……. 21 Figure 2.2 The ideal drift region and its electric field distribution………………….. 22 Figure 2.3 Planar junction obtained by diffusion……………………….....………... 23 Figure 2.4 The cylindrical junction…………..……………………………………… 23 Figure 2.5 Breakdown voltages of cylindrical and spherical junctions normalized to

parallel-plane case…………………………………………………...…... 24

Figure 2.6 Planar junction with metal field plate over the field oxide………...……. 25 Figure 2.7 Junction termination extension………………………………………..…. 25 Figure 2.8 MOS structure operating under flat band condition…………………..…. 26 Figure 2.9 MOS structure at various gate biases……………………..……………... 27 Figure 2.10 Band diagrams for silicon MOS structures with heavily doped

polysilicon gate regions…………………………………………..……… 29

Figure 2.11 Work function difference for silicon MOS with polysilicon gate……….. 29 Figure 2.12 Capacitances within the basic MOS structure………………………..….. 30 Figure 2.13 Capacitance variation for a basic MOS structure…………………..….… 31 Figure 2.14 LDMOS design triangle showing trade-offs that affect device SOA……. 31 Figure 2.15 Circuit model of LDMOS showing the intrinsic MOS and the parasitic

BJT………………………………………………………………………. 32

Figure 2.16 Cross-section of a lateral RESURF structure………………………..…... 34 Figure 2.17 The resulting space-charge sharing when the two diodes are merged

together…………………………………………………………………... 34

Figure 2.18 Illustration of the lateral electric field reshaping for the structure in figure 2.16 (a) The electric field reduction due to the lower Nepieff value, and (b) BVlateff calculation as a result of the field reduction……………...

37

Figure 2.19 Illustration of the charge and electric field distributions for different η possible values, (a) 0 < η < 1, under RESURF’ing condition, (b) η = 1, optimal RESURF’ing condition, and (c) η > 1, over RESURF’ing condition…………………………………………………….……………

38

Figure 2.20 Cross-section of a lateral double-RESURF structure showing the P-top region……………………………………………………………………..

39

Figure 3.1 The schematic cross-section of the RESURF LDMOS…………..……… 46 Figure 3.2 The optimum epitaxial doping concentration as a function of the

epitaxial layer thickness …..…………………………………………..… 47

Figure 3.3 P-body/N-epi junction doping distribution…………….……………..….. 48 Figure 3.4 Breakdown voltage and specific ON-resistance as a function of epitaxial

doping concentration at LDrift = 21.5 µm…………...…………………… 50

Figure 3.5 Potential distribution at the breakdown for (a) Nepi = 1.0E+14 cm-3, (b) Nepi =2.0E+16 cm-3, and (c) Nepi = 6.0E+15 cm-3, at LDrift =21.5µm……...

51

ix

Figure 3.6 Electric field distribution for different epitaxial doping concentrations at LDrift=21.5µm……………………………………………………………..

51

Figure 3.7 Impact ionization distribution at the breakdown for (a) Nepi = 1.0E+14 cm-3, (b) Nepi = 2.0E+16 cm-3, and (c) Nepi = 6.0E+15 cm-3, at LDrift = 21.5µm………………...………………………………………………….

52

Figure 3.8 Breakdown voltage and specific ON-resistance as a function of the epitaxial doping concentration for different LDrift………………………..

53

Figure 3.9 Breakdown voltage and specific ON-resistance as a function of the drift length at Nepi = 6.0E+15 cm-3…………………………………………….

53

Figure 3.10 Electric field distribution at breakdown for different drift length at Nepi = 6.0E+15 cm-3……….…………………………………………...………..

54

Figure 3.11 (a) Breakdown voltage and (b) specific ON-resistance as a function of the drift length at Ldrift = 17.5µm………..………………………………..

54

Figure 3.12 Electric field distribution at breakdown for various epitaxial thicknesses at LDrift =17.5 µm and Nepi = 6.1E+15 cm-3……………..………………...

55

Figure 3.13 The effect of substrate doping concentration on the breakdown voltage and specific ON-resistance for LDrift =17.5 µm and Nepi = 6.1E+15 cm-3……………………………………………………………..

55

Figure 3.14 Breakdown voltage and specific ON-resistance as a function of the accumulation length for LDrift = 17.5 µm and Nepi = 6.1E+15 cm-3 ………

55

Figure 3.15 Simple resistive model for the drift region..…………………………...… 56 Figure 3.16 Electric field distribution at the breakdown for various accumulation

lengths for LDrift =17.5 µm and Nepi = 6.1E+15 cm-3…………………….. 56

Figure 3.17 Breakdown voltage and specific ON-resistance as a function of the gate field plate length at LDrift = 17.5 µm and Nepi = 6.1E15 cm-3 …………….

56

Figure 3.18 Electric field distribution at the breakdown for various gate field plate lengths at LDrift = 17.5 µm and Nepi = 6.1E15 cm-3……………………….

57

Figure 3.19 Breakdown voltage and specific ON-resistance as a function of the drain field plate length at LDrift = 17.5 µm and Nepi = 6.1E+15 cm-3 …………...

57

Figure 3.20 Electric field distribution at breakdown for various drain field plate lengths at LDrift =17.5 µm and Nepi = 6.1E15 cm-3………..………………

57

Figure 3.21 P-body doping concentration effect on the threshold voltage…………… 58 Figure 3.22 The schematic cross-section of the Buffered RESURF LDMOS……….. 58 Figure 3.23 The LDMOS process steps………………………..…………..………..... 59 Figure 3.24 2D cross-section of RESURF LDMOS………………………..………… 60 Figure 3.25 (a) The vertical absolute doping profile cut A-A, (b) The vertical

absolute doping profile cut B-B, and (c) The lateral absolute doping profile cut C-C……………………………………………………...….…

60

Figure 3.26 Breakdown voltage and specific ON-resistance for RESURF-LDMOS with and without buffer-layer………………………………………….....

61

Figure 3.27 Electric field distribution at the breakdown in the OFF-state…………… 61 Figure 3.28 VK dependence on VDS and VGS………………………..….…..………….. 62 Figure 3.29 ID -VK characteristics……………..............……………………...…..…… 63 Figure 3.30 ID -VDS output characteristics of Buffered RESURF-LDMOS…………... 63 Figure 3.31 Transfer characteristic at VDS = 150V…….……..……………………...... 64 Figure 3.32 (a)The cross-section of buffered 3D LDMOS, and (b) The potential

distribution at breakdown……………………………………….…….…. 64

Figure 3.33 (a) ID -VDS DC characteristics, and (b) The current distribution at VDS = 400V and VGS = 5V……………………………………………....………

65

Figure 3.34 (a) CGS dependence on VGS, and (b) CGD dependence on VGS……………. 66

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Figure 3.35 The accumulation layer in the drift zone at VDS = 0.1V and VGS =0.4V…. 66 Figure 4.1 The 0.35µm BiCMOS technology standard layers…………………….... 71 Figure 4.2 The 0.35µm BiCMOS technology doping profiles for (a) figure 4.1a,

and (b) figure 4.1b layers …………………………………...…………... 72 Figure 4.3 The schematic cross-section of the CMOS…….……………………..…. 73 Figure 4.4 2D cross-section of CMOS………….……….……………………….….. 74 Figure 4.5 The process steps of 0.35µm BiCMOS technology……………………... 74 Figure 4.6 nMOS vertical profiles (a) the channel, and (b) source/drain…….……... 75 Figure 4.7 pMOS vertical profiles (a) the channel, and (b) source/drain………….. 75 Figure 4.8 OFF-state characteristics of (a) nMOS, and (b) pMOS………………….. 76 Figure 4.9 nMOS and pMOS transfer characteristics………………………..…..….. 76 Figure 4.10 nMOS and pMOS ID -VDS characteristics………………………..………. 76 Figure 4.11 The schematic cross-section of the proposed nLDMOS………………… 77 Figure 4.12 The process steps of nLDMOS in 0.35µm BiCMOS technology……….. 78 Figure 4.13 2D cross-section of nLDMOS………..……………………..…..……….. 78 Figure 4.14 Breakdown voltage and specific ON-resistance for different drift

thicknesses at LDrift =7.5µm, TPwell = 1.7µm, and LS =1.65µm…..……….. 79

Figure 4.15 Electric field distribution at the breakdown for various drift thicknesses at LDrift =7.5µm, TPwell = 1.7µm, and LS =1.65µm………….…………….

80

Figure 4.16 Potential distribution at the breakdown for (a) TDrift = 0.6µm, (b) TDrift = 2.1µm, and (c) TDrift =1.1µm, at LDrift = 7.5µm, TPwell =1.7µm, and LS = 1.65µm……………………………………………………………………

80

Figure 4.17 Breakdown voltage and specific ON-resistance for different Pwell spacing lengths at LDrift =7.5µm, TPwell =1.7µm, and TDrift =1.1µm ……...

81

Figure 4.18 Electric field distribution at the breakdown for various Pwell spacing lengths at LDrift =7.5µm,TPwell = 1.7µm, and TDrift =1.1µm………………..

81

Figure 4.19 Potential distribution at the breakdown for (a) LS = 0.0 µm, and (b) LS = 1.65µm at LDrift=7.5µm, TPwell = 1.7µm, and TDrift =1.1µm …………...…

82

Figure 4.20 Breakdown voltage and specific ON-resistance for different drift lengths at LS =1.65µm, TPwell =1.7µm, and TDrift =1.1µm ………………………...

82

Figure 4.21 Electric field distribution at the breakdown for different drift lengths at LS =1.65µm, TPwell =1.7µm, and TDrift =1.1µm …………………………...

83

Figure 4.22 Breakdown voltage and specific ON-resistance for different Pwell thicknesses at LS =1.65µm, LDrift = 7.5µm, and TDrift =1.1µm ……………

83

Figure 4.23 Electric field distribution at the breakdown for various Pwell thicknesses at LS=1.65µm, LDrift = 7.5µm, and TDrift =1.1µm ……………

84

Figure 4.24 Breakdown voltage and specific ON-resistance for different Pwell doping concentrations at LS = 1.65µm, LDrift =7.5µm, and TDrift = 1.1µm………………………………………………...…………………...

84

Figure 4.25 Electric field distribution at the breakdown for various Pwell doping concentrations at LS =1.65µm, LDrift =7.5µm, and TDrift =1.1µm ………...

84

Figure 4.26 The schematic cross-section of the proposed pLDMOS…...……………. 85 Figure 4.27 The process steps of pLDMOS in 0.35µm BiCMOS technology.............. 86 Figure 4.28 2D cross-section of pLDMOS………..………..………………………… 86 Figure 4.29 Breakdown voltage and specific ON-resistance for different drift

thicknesses at LDrift =7.5µm ………………………………………….….. 87

Figure 4.30 Electric field distribution at the breakdown for various drift thicknesses at LDrift =7.5µm…....…………………………………………………..….

87

Figure 4.31 Potential distribution at the breakdown for (a) TDrift = 0.65µm, and (b) TDrift =2.45µm at LDrift =7.5µm............................................................…...

88

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Figure 4.32 Breakdown voltage and specific ON-resistance for different drift lengths at TDrift =0.65µm ………………………………………………….……...

88

Figure 4.33 Electric field distribution at the breakdown for different drift lengths at TDrift =0.65µm …………………………………………………….……...

88

Figure 4.34 Breakdown voltage and specific ON-resistance for different drift doping concentrations at TDrift = 1.1µm, and LDrift=7.5µm ………………………

89

Figure 4.35 (a) Breakdown voltage characteristic, and (b) Impact ionization distribution at BV of nLDMOS…………………………………...…...…

90

Figure 4.36 (a) Electric field, and (b) potential distributions, of nLDMOS………….. 90 Figure 4.37 VK dependence on VDS and VGS………………………..…...…………….. 90 Figure 4.38 ID -VK characteristics…...........………………………..………...….…… 91 Figure 4.39 ID -VDS output characteristics of nLDMOS for the optimum design

case............................................................................................................. 91

Figure 4.40 The transfer characteristic of nLDMOS…………………………….…… 91 Figure 4.41 (a) Drain current and drain temperature variation at VGS =3 V, and (b)

The temperature distribution at VGS = 3 V and VDS = 60 V……............... 92

Figure 4.42 Thermal ID-VDS characteristics of nLDMOS………………………..…… 92 Figure 4.43 CGS and CDS dependence on VGS……………...……………………..…… 93 Figure 4.44 (a) Breakdown voltage characteristic, and (b) Impact ionization

distribution at BV of pLDMOS……………………………………..…… 93 Figure 4.45 (a) Electric field, and (b) potential lines distributions of pLDMOS……. 94 Figure 4.46 VK dependence on VDS and VGS…………………………….....……..…… 94 Figure 4.47 ID -VK characteristics……………….……………………………..…...… 94 Figure 4.48 ID -VDS output characteristics of pLDMOS for the optimum design

case………………………………………………………………………. 95

Figure 4.49 The transfer characteristics of pLDMOS………………………….....….. 95 Figure 4.50 (a) Drain current and drain temperature variation at VGS =-3 V, and (b)

The temperature distribution at VGS = -3 V and VDS = -100 V…………... 95

Figure 4.51 Thermal ID -VDS characteristics of pLDMOS…...……………………..… 96 Figure 4.52 CGS and CDS dependence on VGS………………...……………………….. 96 Figure 5.1 The schematic cross-section of the RESURF LDMOS………………….. 102 Figure 5.2 Drift region functional partition…..……………....................................... 102 Figure 5.3 Modeling flow chart…………………..………...……………………….. 104 Figure 5.4 The proposed subcircuit LDMOS model………………………………... 109 Figure 5.5 Analytical output characteristics of the intrinsic MOSFET……………... 110 Figure 5.6 Comparison of the model simulation (Red dashed curves), and the

TCAD results (Black solid curves)……………………………………… 111

Figure 5.7 The accumulation resistance as a function of VGS and VK ………………. 111 Figure 5.8 The total drift resistance as a function of VDS and VK at VGS =2V ………. 112 Figure 5.9 Approximate analytical static model of LDMOS………………………... 112 Figure 5.10 The Spice model parameters of low voltage MOSFETs……………….. 114 Figure 5.11 The Spice model parameters of LDMOSFETs…..…………………….. 114 Figure 5.12 Comparison of the TCAD simulation (Black solid curves) and the Spice

model simulation (Red dashed curves) for nLDMOS…………… 115

Figure 5.13 Comparison of the TCAD simulation (Black solid curves) and the Spice model simulation (Red dashed curves) for pLDMOS……………

115

Figure 5.14 The circuit schematic of the interface circuit……...…………………….. 116 Figure 5.15 The input and output waveforms of the interface circuit………………... 116 Figure 6.1 The deep trench isolation structure ……………………………………... 122 Figure 6.2 The structure of cLDMOS with deep trench isolation…………...……… 122

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Figure 6.3 The drain and bulk currents of (a) nLDMOS, and (b) pLDMOS, without trench isolation (dashed curves), and with trench isolation (solid curves)……………………………………………………………………

123

Figure 6.4 (a) Potential distribution, and (b) Electric field distribution, in nLDMOS…………………………………………………………………

123

Figure 6.5 (a) Potential distribution, and (b) Electric field distribution, in pLDMOS……….…………………………………………………..…….

123

Figure 6.6 The drain currents of (a) nLDMOS, and (b) pLDMOS, at |VGS | =3 V, without trench isolation (dashed curves), and with trench isolation (solid curves)……………..……………………………………………………..

124

Figure 6.7 Simplified cross-section, showing the cLDMOS, the CMOS, and the parasitic NPN transistor…….….…............................................................

124

Figure 6.8 The injection collected ratio of (a) pLDMOS, and (b) pMOS in two cases with and without P+……...................................................................

125

Figure 6.9 The potential contours distributions in case of (a) without P+, and (b) with P+ implant…………….……………………………………………..

126

Figure 6.10 Substrate noise injection mechanisms in a digital inverter……………… 126 Figure 6.11 The 2D structure of the nMOS with DTI …...…………………………... 128 Figure 6.12 The Potential distribution of the nMOS structure with DTI ……………. 128 Figure 6.13 (a) The saturation drain current, and (b) the bulk electrode current due to

0/42 signal switching applied on the cLDMOS drain for LDTI=8µm……. 128

Figure 6.14 (a) The saturation drain current, and (b) the bulk current, as a function of the deep trench length for LS = 3µm……………………………….….

129

Figure 6.15 (a) The saturation drain current, and (b) the bulk current, as a function of the keep away zone length for LDTI = 8µm……………………….…...

130

Figure 6.16 The 2D structure of the pMOS with DTI …....………………………….. 130 Figure 6.17 The Potential distribution of the pMOS structure with DTI ……………. 130 Figure 6.18 (a)The saturation drain current, (b) the bulk electrode current, and (c)

the bulk voltage due to 0/42 signal switching applied on the cLDMOS drain for LDTI = 8µm………………………....……………………...……

131

Figure 6.19 (a) The saturation drain current, (b) the bulk electrode current, and (c) the bulk voltage as a function of trench length ...………………………..

132

Figure 6.20 (a) The saturation drain current, (b) the bulk electrode current and (c) the bulk voltage as a function of DTI spacing …………………………...

132

Figure 6.21 The 2D structure of the CMOS with DTI….……….................................. 133 Figure 6.22 The Potential distribution in the CMOS structure with DTI…………….. 133 Figure 6.23 The temperature waveform in the CMOS structure with DTI...………… 134 Figure 6.24 The Potential distribution in the CMOS structure with DTI when the

nMOS bulk electrode is floating………………………………………… 134 Figure 6.25 (a) The Potential distribution, and (b) The voltages and output-current

waveforms for vin = 1.2V and vDdMOS = 42.0V, with floating nMOS bulk electrode…………………………………………………………………. 135

Figure 6.26 The Potential distribution in the CMOS structure with DTI when the pMOS bulk electrode is floating………………………...….………….... 135

Figure 6.27 (a) The Potential distribution, and (b) The voltages and output-current waveforms for vin = 1.2V and vDdMOS = 42.0V for floating pMOS bulk contact…………………………………………………………………… 136

Figure 6.28 The cost and performance comparison among the various technologies... 137 Figure 6.29 An example of a heterogeneous 3D system-on-chip…………………….. 138 Figure 6.30 TSV and RDL – based 3D integration…………………………………... 138

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Figure 6.31 The 2D structure of the thinned stratum with nMOS……………………. 139 Figure 6.32 Potential distribution for RDL floating for TSUB =10µm and TOXTSV =

0.05µm…………………………………………………………………… 140 Figure 6.33 (a) The saturation drain current and (b) the bulk electrode current due to

0/42 square signal on the TSV for TSUB=10µm and TOXTSV =0.05µm…... 140 Figure 6.34 The saturation drain current as a function of the substrate thickness for

different TSV oxide thicknesses for LS = 3.0µm and TOXRDL =0.5µm…... 141 Figure 6.35 (a) The bulk current as a function of the substrate thickness for different

TSV oxide thicknesses for LS =3.0µm and TOXRDL =0.5µm…….……….. 141 Figure 6.36 (a) The drain current and (b) the bulk current as a function of the TSV

spacing in the ON and OFF states for TSUB=10µm, TOXTSV =0.05µm and TOXRDL =0.5µm…………………………………………………………… 142

Figure 6.37 Potential distribution for TSV floating for TSUB=10µm, TOXTSV =0.05µm, and TOXRDL =0.5µm………………………………………….…………… 142

Figure 6.38 Potential distribution for TSUB=10µm and TOXTSV =0.05µm……………... 143 Figure 6.39 (a) The saturation drain current and (b) the bulk electrode current due to

0/42 square signal on the TSV and RDL for TSUB=10µm and TOXTSV = 0.05µm…………………………………………………………………… 143

Figure 6.40 The 2D structure of the thinned stratum with pMOS……………………. 144 Figure 6.41 Potential distribution for RDL floating for TSUB=10µm and TOXTSV =

0.05µm…………………………………………………………………… 144 Figure 6.42 (a) The saturation drain current , (b) the bulk electrode current, and (c)

the body voltage due to 0/42 transient signal on the TSV for TSUB=10µm and TOXTSV = 0.05µm and LS = 3.0µm………………………. 145

Figure 6.43 The saturation drain current as a function of the TSV spacing at various TSV oxide thicknesses for TSUB =10µm, TOXTSV = 0.05µm and TOXRDL = 0.5µm……………………………………………………….……………. 145

Figure 6.44 The bulk voltage as a function of the TSV spacing for different TSV oxide thicknesses for TSUB =10µm, TOXTSV =0.05µm and TOXRDL = 0.5µm 145

Figure 6.45 The bulk current as a function of the TSV spacing for different TSV oxide thicknesses for TSUB=10µm, TOXTSV =0.05µm and TOXRDL =0.5µm 146

Figure 6.46 The saturation drain current as a function of the substrate thickness at various TSV oxide thicknesses for LS= 3.0µm, TOXTSV = 0.05µm and TOXRDL =0.5µm…………………………………………………………… 146

Figure 6.47 The bulk current as a function of the substrate thickness at various TSV oxide thicknesses for LS= 3.0µm, TOXTSV =0.05µm and TOXRDL = 0.5µm... 146

Figure 6.48 The bulk voltage as a function of the substrate thickness at various TSV oxide thicknesses for LS= 3.0µm, TOXTSV =0.05µm and TOXRDL =0.5µm… 146

Figure 6.49 Potential distribution for TSV floating for TSUB=10µm, TOXTSV =0.05µm and TOXRDL = 0.5µm……………………………………………………... 147

Figure 6.50 Body-voltage for RDL 0.5µm ON case TSUB =5µm……………………... 147 Figure 6.51 Potential distribution for TSUB=10µm TOXTSV =0.05µm………………….. 148 Figure 6.52 (a) The saturation drain current, (b) the bulk electrode current, and (c)

the body voltage due to 0/42 square signal on the TSV and RDL for TSUB=10µm TOXTSV =0.05µm…………………………………………….. 148

Figure 6.53 The CMOS sensitive regions…………………………………………….. 149 Figure 6.54 The CMOS potential distribution for (a) floating RDL, and (b) floating

TSV……………………………………………………………………… 149 Figure 6.55 The 2D structure of TSV-CMOS with floating nMOS bulk contact......... 150 Figure 6.56 (a) The Potential distribution, and (b) The voltages and output-current 151

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waveforms for vin = 1.2V and vTSV = 42.0V, with TSV located in the nMOS side………………………………………………………………..

Figure 6.57 The structure of TSV-CMOS with floating nMOS bulk contact………... 151 Figure 6.58 (a) The Potential distribution, and (b) The voltages and output-current

waveforms for vin = 1.2V and vTSV = 42.0V, with TSV located in the pMOS side and with floating nMOS bulk contact………………………. 152

Figure 6.59 The structure of TSV-CMOS with floating pMOS bulk contact………... 152 Figure 6.60 (a) The Potential distribution, and (b) The voltages and output-current

waveforms for vin = 1.2V and vTSV = 42.0V, with TSV located in the pMOS side and with floating pMOS bulk contact………………………. 153

Figure 6.61 The structure of TSV-CMOS with floating pMOS bulk contact and with P+ guard-ring…………………………………………………………….. 153

Figure 6.62 (a) The Potential distribution, and (b) The voltages and output-current waveforms for vin = 1.2V and vTSV = 42.0V……………………………... 154

Figure 6.63 3D Cross-section of TSV-CMOS mixed mode coupling…….………….. 154 Figure 6.64 (a) Y-cut potential distribution, and (b) The voltages and output-current

waveforms at vin = 1.2V and vTSV = 42.0V………………………………. 155 Figure 6.65 System via and striplines: (a) 3D-structure, and (b) Cut along the X-

axis……………………………………………………………………….. 157 Figure 6.66 Electric field map, transient regime……………………………………... 158 Figure 6.67 Voltage at different probe points : excitation : pulse on Port0 (see

figure 65b)……………………………………………………………….. 159 Figure 6.68 Transmission parameters: S12 and S21…………………………….……. 159 Figure 6.69 System via and striplines bended at 90°…………………………….…… 159 Figure 6.70 Voltage at different probe points: excitation: pulse on Port0 (see figure

65b)………………………………………………………………...…….. 160 List of tables Table 4.1 The optimum geometrical parameters of nLDMOS……………………... 89 Table 4.2 The optimum geometrical parameters of pLDMOS …..………………… 93

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List of abbreviations

Integrated circuit IC Metal-oxide semiconductor MOS Low-voltage LV High-voltage HV Current voltage IV Metal-oxide semiconductor MOS Metal-oxide semiconductor field-effect transistor MOSFET n-channel MOS nMOS p-channel MOS pMOS Complementary MOS CMOS Bipolar junction transistor BJT Junction field-effect transistor JFET Bipolar CMOS BiCMOS Double diffused MOS DMOS lateral double diffused MOS LDMOS Complementary LDMOS cLDMOS Double-diffused MOSFET DMOSFET Power IC PIC Bipolar-CMOS-DMOS BCD Very large scale integration VLSI Technology computer aided design TCAD High-voltage IC HVIC Insulated gate bipolar transistor IGBT Lateral IGBT LIGBT Breakdown voltage BV Reduced surface field RESURF V-groove MOSFET VMOSFET Vertical DMOSFET VDMOSFET U-shape MOSFET UMOSFET Electro-luminescence EL Liquid crystal display LCD Video cassette recorder VCR Self isolation SI Silicon on insulator SOI Dielectric isolation DI Junction isolation JI N+ diffusion ring ND Safe operating region SOA

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Long-term SOA LT SOA Short-term SOA ST SOA Junction termination extension JTE Direct current DC Alternate current AC graphical user interface GUI Deep trench isolation DTI Lightly doped drain LDD Rapid thermal annealing RTA N-buried layer NBL P-buried layer PBL Local oxidation of silicon LOCOS Integrated systems engineering TCAD ISE-TCAD Matrix laboratory MATLAB Integrated circuit characterization and analysis program ICCAP Analog behavioural modeling ABM Borophosphosilicate glass BPSG Rapid thermal annealing RTA Gradual channel approximation GCA Two dimensions, three dimensions 2D, 3D Deep trench isolation DTI Through-silicon-via TSV System-on- a chip SoC Radio frequency RF International technology roadmap for semiconductors ITRS

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List of Symbols

Ω ON-resistance RON Ω.cm2 Specific ON-resistance RON,SP Ω Interconnect resistance Rvia 1 Multiplication coefficient M(x) 1 Electron impact ionization coefficient αn 1 Hole impact ionization coefficient αp 1 Effective impact ionization coefficient αeff V.cm-1 Electric field E V.cm-1 Critical electric field Ec V.cm-1 Lateral critical electric field Eclat V.cm-1 Vertical critical electric field Ecver V.cm-1 Maximum electric field Emax cm2 .V -1 .s-1 Carrier mobilities µn, p cm-3 Hole concentration P cm-3 Electron concentration N cm-3 Intrinsic density ni F.cm-1 Silicon dielectric constant εs µm Depletion region width WD µm Junction radius rj µm Depletion region radius rD µm Junction depth xj cm-3 Donor atoms concentrations ND µm Oxide thickness tox µm Junction termination extension length LJTE µm Field plate length LFP µm Parallel plane junction width Wpp 1.602E-19 J Electron volt eV eV Work function of the metal φΜ eV Semiconductor electron affinity χS eV Semiconductor energy band gap EG eV

Potential difference between intrinsic level and Fermi level in the bulk

ψB

eV Barrier height between metal and oxide φΒ eV Oxide electron affinity χO 1.602E-19 C Electron charge q K Temperature T 1.38E-23 J.K-1 Boltzmann's constant K C.cm-2 Fixed surface charge QFC

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C.cm-2 Mobile ions in the oxide QI C.cm-2 Oxide-silicon interface charge QSS eV Work function difference φΜS s Dielectric relaxation time τd Ω-1.cm-1 Semiconductor conductivity σs F.cm-2 Oxide capacitance Cox F.cm-2 Semiconductor capacitance Cs F.cm-2 Depletion capacitance CDEP cm-3 Effective electron density of states Nc cm-3 Effective hole density of states Nv cm-3 Epi-layer doping concentration Nepi cm-3 Optimum epi-layer doping concentration Nepi,opt µm Epi-layer thickness Tepi cm-3 Substrate doping concentration Psub V Applied voltage Vapp µm Drift layer length LDrift µm Lateral depletion region extension Xlat µm Vertical depletion region extension Xver C.cm-2 Lateral space charge Qlat C.cm-2 Vertical space charge Qver V Lateral breakdown voltage BVlat V Vertical breakdown voltage BVver C.cm-2 Effective lateral space charge Qlateff V.cm-1 Effective lateral critical electric field Eclateff µm Effective lateral depletion region extension Xlateff cm-3 Effective epi-layer doping concentration Nepieff V RESURF structure breakdown voltage BVresurf 1 RESURF coefficient η cm-3 Doping concentration of the P-top region Ptop V Single RESURF structure BV BVsr C.cm-2 Single RESURF charge Qnsr C.cm-2 Maximum single RESURF charge Qnsr,max V Double RESURF structure BV BVdr C.cm-2 P-top charge Qpdr C.cm-2 Double RESURF epi-charge Qndr C.cm-2 Maximum P-top charge Qpdr,max C.cm-2 Maximum double RESURF epi- charge Qndr,max µm Channel length LCH V Intrinsic drain voltage VK V Flat band voltage VFB

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cm-3 P-body doping concentration in the channel PCH

V Reverse biased voltage Vr

V Drain-source voltage VDS V Gate-source voltage VGS A /µm Drain current ID A/µm Bulk current IB C Gate charge QG µm Accumulation layer length LACC µm Gate field plate length LGFP µm Drain field plate length LDFP V Threshold voltage VTH cm-4 Slope of the linearly graded junction G V Punch-through voltage VPT µm Depletion layer width at punch-through WPT Ω Source contact resistance RN+source Ω Drain contact resistance RN+drain Ω Drift resistance RDrift Ω Channel resistance RCH µm The pitch length WP µm Minimum drift length LDriftmin Ω Accumulation resistance RACC V Metallurgical junction surface potential VK (ΨSL ) F Gate-source capacitance CGS F Gate-drain capacitance CGD cm-3 P-well doping concentration Pwell µm Optimum drift thickness TDrift,opt. µm P-well space length Ls µm P-well thickness Tpwell cm-3 P-drift region concentration PDrift V Depletion region boundary voltage VK1 (ΨD) V Fermi potential φF V Drift region flat band voltage VFBdr µm Drift region depletion width ddep cm2 .V -1 .s-1 Low field mobility μn0 V -1 Mobility fitting parameter θ cm-3 Channel doping density near the source NA0 cm.s-1 Drift velocity v cm.s-1 Saturation drift velocity vsat 1 Channel doping gradient η F.cm-2 Average depletion capacitance

dC

xx

F.cm-1 Oxide permittivity εox V Intrinsic drain at onset of saturation VKsat µm Depth of the current path ypath 1 Current path slope tan α cm2 .V -1 .s-1 Effective electron mobility µneff C.cm-2 Invesion charge density Qn A /µm Channel current Ich A /µm Saturation channel current Ichsat V Surface potential ψs C.cm-2 Bulk charge density Qb A /µm Total drift current It cm2 .V -1 .s-1 Accumulation layer effective mobility μaneff Ω Quasi neutral drift resistance Rdr C.cm-2 Drift region charge density Qdr µm Neutral drift layer thickness Zdr µm Neutral drift layer length Ldr Ω High voltage drift resistance Rdvsat Ω Low voltage drift resistance Rd0 C.cm-3 Charge density ρ Ω Depletion resistance Rdep F.cm-2 Zero-bias capacitance Cj0 1 Junction graduality factor. m cm2 Gate-source overlap area An+os cm2 Gate-N+

accumulation layer overlap area An+oacc µm Device width W V Diffusion voltage of the junction VJ V Gate-depletion boundary voltage VGK1 V -1 Mobility fitting parameter in the acc. layer θacc Ω Total drift resistance RDrift V Low-level supply voltage VDDL V High-level supply voltage VDDH A /µm Collector current IC A /µm Emitter current IE 1 Injection collected ratio α =IC /IE µm Deep trench isolation length LDTI Hz Material cut-off frequency fc V Source-bulk voltage Vsb µm Deep trench isolation spacing Ls

1-m.H The medium permeability µ

General Introduction


2


3

Smart power integrated circuits, which monolithically integrate low-loss power devices and control circuitry, have attracted much attention in a wide variety of applications. These ICs improve the reliability, reduce the volume and weight, and increase the efficiency of a system. Considerable effort has been put into the development of smart power devices for automotive electronics, computer peripheral appliances, and portable equipment, etc.

Commonly used smart power devices are the lateral double diffused MOS transistors

(LDMOSFETs). The main issues in the development of these devices are to obtain the best trade-off between specific ON-resistance RON,SP and breakdown voltage BV, and to shrink the feature size without degrading device characteristics. A lot of work has been done on both characterization and modeling of LDMOSFETs in the literature starting from the late ’70. Still, there is some confusion concerning the origin of special phenomena like, for instance, quasi-saturation and explanation of the capacitive behavior of the HV device as a function of the biasing conditions. Unfortunately, this matter was not treated in a thorough manner, most of the times only a few characteristics, that do not cover the entire voltage domain, being presented.

Device simulation with TCAD (technology computer-aided design) tools have proven to play an important role for the design engineers and researchers to analyze, characterize, and develop new devices. It saves time and lowers the cost of design when compared to the experimental approach. In addition, it allows seeing physical effects clearly in the semiconductor devices concerning new device concepts. Therefore, clear understanding of TCAD tools used for the analysis of power semiconductors is essential to obtain an accurate and reliable simulation results.

This work deals with novel power semiconductor concepts for smart power applications. New device structures are suggested and studied to improve the device characteristics related to traditional power devices. Two- and three-dimensional device simulations are performed to study new device concepts. These new structures are implemented in 0.35µm BiCMOS technology.

An important motivation point is the planar integration of the HV LDMOSFETs with the low voltage CMOS devices. New electrical isolation scheme between the power devices as well as between the power devices and low-voltage CMOS devices is suggested using a deep trench to reduce the isolation distance between the high voltage devices considerably and hence to reduce the total chip area drastically compared to technologies with a standard junction isolation scheme.

In recent years, there is an emerging technology which is the Three-dimensional (3D)

integration. This technology uses through-silicon-vias (TSVs) and re-distribution Layers (RDLs) to interconnect multiple active circuit layers. 3D integration offers significant improvements over two-dimensional (2D) integrated circuits (ICs) on performance, functionality, and integration density and promises a solution to the so called “wiring crisis” problem. Furthermore, 3D integration also provides new architectures for sophisticated ICs and facilitates the integration of heterogeneous materials, devices. The important motivation question is that: Is this 3D technology can be used for the implementation of smart power integrated circuits?


4

In this thesis, ISE and SENTAURUS-TCAD tools, general purpose device simulators, are used for the simulation of established and newly proposed power semiconductor devices and integration schemes.

From modeling point of view; two model types are presented in the literature. Several attempts were made to build compact models for the HV devices. Some authors stress on the construction of the intrinsic MOS model and treat the drift part as a trivial extension, Others, stress on the modeling of the drift part only. Still to fulfill this target, very simple expressions are needed for both drift and intrinsic MOS part. This results most of the time in poor accuracy when compared with real device characteristics. In the second category are the macro-models, which are models built by merging several Spice elementary devices in a subcircuit and using the result as a black box for the transistor model. The proposed LDMOS devices are used to construct an interface circuit to convert the low logic level voltage to high level voltage.

The above mentioned issues led to the work of this thesis. One of the purposes is to highlight the physical phenomena that take place inside the HV LDMOSFETs. An extended analysis including DC and AC characteristics as well as TCAD simulations is performed revealing each important effect. It is demonstrated that the separation of the device into two parts by using the metallurgical junction between the body region and the drift region, offers the possibility to use a low voltage MOS model for the intrinsic part. Consequently, DC models were built by using low voltage MOS Spice models in conjunction with drift resistance model for the drift extension. Another purpose is to study the substrate coupling in planar and vertical integration schemes of LDMOS devices and low-voltage CMOS devices

This work is divided into six chapters. The first two chapters give an overview of power

semiconductors and related analytical studies. Then simulation results of new LDMOSFETs structures proposed in 0.35 µm BiCMOS technology are described.

A comprehensive study of the physical effects that take place in the HV devices is the

subject of analysis in chapter 2. The effect of the junction curvature on the breakdown voltage is explained. The analytical treatment of the REduced SURface Field (RESURF) principle is done.

In chapter 3, a general purpose RESURF-LDMOS structure is designed based 2D and 3D

numerical TCAD simulations to verify the RESURF concept. The key device/process parameters are optimized to get the best trade-off between RON,SP and BV. VK (The intrinsic drain potential) variation is extracted as a function of the gate and drain voltages. The last part of chapter 3 introduces charge consideration in the RESURF-LDMOS in AC biasing conditions.

The design and optimization of LDMOSFETs implemented in 0.35 µm BiCMOS

technology (STMicroelectronics technology-like) are the focus of chapter 4. The proposed nLDMOS has a breakdown voltage independent of the drift region thickness. This device is suitable for the design of the Smart power ICs, as, it can be integrated with low voltage devices with thin epitaxial layers. Also, a proposed pLDMOS is designed and optimized using the same epitaxial layer of the optimized nLDMOS.

The analytical model of the intrinsic MOS part and the drift zone is the focus of chapter 5.

The model is discretized in several cases as a function of the position of the depleted area and


5

the limit of the accumulation layer. A very interesting result is obtained for the intrinsic drain voltage, which remains at low values. It is to be mentioned, the right variation of the intrinsic drain voltage is the starting point in obtaining good device model. The model for the entire HV device was built using a two module approach, one for the intrinsic MOS area and the drift model. With the help of the proposed analytical model, Spice models are developed and used to construct an interface circuit.

In chapter 6, two technologies are proposed to implement the smart power integrated

circuits. The first one is the planar integration using the deep trench isolation (DTI) technique. This technique is used to achieve the isolation between power devices as well as between power devices and low-voltage circuitry. The second technology is the new stacked 3D- integration using through-silicon vias (TSVs) and re-distribution Layers (RDLs). The impact of these technologies on the performance of both the HV LDMOS and the LV CMOS devices are discussed. Also, the electrical impact of substrate perturbations due to the HV square signal of the future automotive applications on the performance of the low voltage MOS devices are studied. On another hand, we begin to study, for the sake of future studies on stacked devices in 3D circuits, in the radiofrequency range, the propagation of electromagnetic waves along some interconnections with discontinuities.

Finally, we summarize the work with some conclusions, and recommendations for the

future work.


6

CHAPTER 1

State of art of SPICs

Chapter 1: State of Art of SPICs

8


9

1.1 Introduction

Since 1965, integrated circuit (IC) technology has followed Moore’s law which states that the number of devices integrated doubles every 18 months. This growth is made partly by increasing the size of ICs which can be produced. However the dominant effect is due to reduction in feature size of component devices which are integrated. Reduction of feature size tends to bring advantages of increased speed and the possibility to operate at lower voltages allowing reduced power consumption. These advantages make technology shrink very attractive for technical performance reasons as well as cost.

However there are many applications where voltage cannot be reduced for external

reasons. Three areas where this is the case are: power electronics, automotive applications and wide dynamic range circuits. In such applications system integration of high voltage, analog and digital circuitry on a single IC is attractive in order to gain advantage in terms of miniaturization, reliability, efficiency and cost. However in order to make these gains, the conflict of reducing voltage due to technology feature size has to be resolved with the requirements for operation at continued relatively high voltage.

The different operation and interface requirements of high voltage, analog and digital

require a technology development optimized for these system requirements. Different technologies to address these applications have been developed such as smart power and various Bipolar-CMOS-DMOS (BCD) processes [1-3].

Smart power integrated circuits (ICs) which monolithically integrate low-loss power

devices and control circuitry have attracted much attention in a wide variety of applications. These ICs improve the reliability, reduce the volume and weight, and increase the efficiency of a system. Considerable effort has been put into the development of smart power devices for automotive electronics, computer peripheral appliances, and portable equipments, such as cellular phones, video cameras, etc. [4, 5].

Commonly used smart power devices are the lateral double diffused MOS transistors (LDMOSFETs) and lateral insulated gate bipolar transistors (LIGBTs) implemented in bulk silicon or SOI (Silicon on Insulator) [6-8]. The main issues in the development of these devices are to obtain the best trade-off between specific ON-resistance RON,SP (RON × area) and breakdown voltage BV, and to shrink the feature size without degrading device characteristics [3, 9]. 1.2 Smart power integrated circuits (SPICs) applications

Smart PIC technology is expected to have an impact on all areas in which discrete power semiconductor devices are presently being used. It is expected to open up new applications based upon the added features of smart controls. In figure 1.1, the applications of power devices are shown as a function of operating frequency. Another approach of classification of the applications of power devices is in terms of their current and voltage handling requirements, as shown in figure 1.2 [2, 10, 11]. Some of these applications are listed in the following.


10

Figure 1.1: Applications of power devices

1.2.1 Flat panel displays

The popularity of portable electronic products such as mobile phones and notebook computers has triggered a tremendous demand on flat panel displays. These displays are usually LCD (liquid crystal display) or EL (electro-luminescence) panels arranged in a matrix with large number of column and row drivers (e.g. 640×480 for VGA resolution). Although the required voltage may be large, the current level is small (usually in the mA range). Smart PICs with as many as 80 output channels have been fabricated on a monolithic chip. 1.2.2 Computer power supplies and disk drivers

Computer systems are growing continuously in terms of their speed and processing capability. This demand is met by higher density of integration in VLSI technology. However, the increase in power requirement has resulted in an increase in the physical size of the power supply. In 1976, the CPU board and the power supply each represented 1/3 the total physical volume in computer system. By 1990’s, the power supply has grown to 50% while the CPU board has shrunk to about 20% of the physical volume. In order to reverse this trend, it is necessary to develop smart PIC technology to improve the density and hence the volume of the power supplies. 1.2.3 Variable speed motor drives

Variable-speed motor drives are being developed to reduce the power loss in all applications. The improvement in performance requires smart power technology that can operate at relatively high frequencies with low power losses. This translates to a low ON-state

HVDC POWER DISTRIBUTION

ELECTRIC TRAINS

UNINTERRUPTIBLE POWER SUPPLY

HYBRID-ELECTRIC CARS

INDUCTION HEATING

AUDIO AMPLIFIERS FLUORESCENT LAMPS

TELEVISION SWEEP

CELLULAR COMMUNICATION

MICROWAVE OVEN

101 102 103 104 105 106 107 108 109

108 107

106 105 104

103 102

101

100

System operating frequency (Hz)

Syst

em p

ower

rat

ing

(Vol

t-A

mpe

res)


11

voltage drop at high current levels, fast switching speed, and rugged operation. For smart PIC implementation, additional consideration such as level shifting to and from high voltages, over-temperature, over-current, over-voltage, and short-circuit protection are more critical.

Figure 1.2: System ratings of power devices

1.2.4 Factory automation

Advanced numerical control and robotic systems require efficient smart PIC technology to create a distributed power control network under the management of a central computer. The smart PICs for this application must be capable of providing AC or DC power to various loads such as motors, solenoids, arc-welder, etc. They are also required to perform diagnostic, protection and feedback functions. 1.2.5 Telecommunications

One of the high-volume markets for smart power technology is in telecommunications. The technology required for this applications must be capable of integrating multiple high-voltage, high current devices on a single chip. At present, this has been accomplished using MOS devices fabricated using dielectric isolation. Improvements are required to reduce the cost of the dielectric isolation fabrication process. On-going development on direct wafer bonding has showed promise in providing a cost effective process.

HVDC TRANSMISSION

ELECTRIC TRAINS

POW

ER

SUPP

LY

MOTOR DRIVES

ROBOTICS

LAMP BALLAST

DISPLAY DRIVERS

TELECOMM.

AU

TOM

OTI

VE

ELEC

TRO

NIC

S

101 102 103 104

104

103

102

101

100

10-1

10-2

Voltage rating (V)

Cur

rent

rat

ing

(A)


12

1.2.6 Appliance controls

The main benefit of utilizing smart PICs in appliance control is to provide improvements in performance and efficiency. On-board sensors can also provide more precise controls (e.g. temperature settings). Simple house appliance such as toasters, washing machines, irons, rice cookers are appearing with smart PICs for this reason.

1.2.7 Consumer electronics

Smart PICs are required for a large variety of entertainment systems such as CD players,

tape recorders, VCRs, etc. For example, a monolithic motor control IC that regulates the speed of the motor while minimizing power losses is essential to all battery-operated consumer entertainment systems. The development of improved lateral power devices with greater power density is required to increase the efficiency of this technology. 1.2.8 Lighting controls

Traditional fluorescence lights use mechanical ballast (transformer) for start-up. The electrical characteristics of fluorescence lights vary drastically from start-up to normal operation. In order to provide better efficiency and life for a lighting system, more precision control is needed. The cost of electronic fluorescence light ballast implemented using smart PICs can easily be justified by the savings in energy and maintenance. In addition, the incorporation of smart PIC technology enables control of the light by a central computer; further enhance the energy saving in commercial buildings. 1.2.9 Smart house

The concept of smart house is getting increasing attention due to advances in smart power technology that are driving the cost down for the control module. A smart house system requires the development of a multiplexed network with smart power modules to control loads such as ovens, furnaces, air conditioners, lights, and small appliances.

1.2.10 Aircraft electronics (Avionics)

The concept of fly-by-wire, where the hydraulic actuators in aircraft are replaced by electromechanical actuators, is gaining acceptance among manufacturers. The success in development will depend on the availability of smart PIC technology to perform the control within a small size and weight. The power switches must be extremely reliable, capable of operating at high voltage and current levels with low ON-state voltage drop. MOS-gated devices are essential for compact PICs. 1.2.11 Automotive electronics

One of the biggest anticipated markets for smart PICs is automotive electronics. In the 1960’s to 1970’s, there was a slow acceptance of the use of discrete devices and analog ICs for automotive applications. In the 1980’s, digital ICs and microprocessors were incorporated. In the 1990’s smart PICs are already being used to create a multiplexed control network in the car to reduce the size and weight of the wiring harness. The smart PIC modules control loads such as lights and motors while providing protection functions. This has greatly enhanced fault management and diagnostics capability.


13

1.3 Historical view of the MOS power devices

The basic operation of the MOSFET entails the formation of a conductive channel at the surface of the semiconductor below an insulator by the application of a voltage to a gate electrode. The first MOSFET structure reported in 1960 was not designed to support high voltages or handle high-current levels, and also thin metal electrodes were used which had poor current-handling capability [1, 12].

In 1970’s, it was recognized that the vertical architecture is required to handle high voltages and currents to produce a power device. The vertical structure enables the use of thick source and drain electrodes. The first power MOSFET structure was fabricated using a V-groove process as shown in figure 1.3.

Figure 1.3:V-groove MOSFET structure

The V-MOSFET structure fell out of favour because of manufacturing difficulties. In

addition, the sharp corner at the bottom of the V-groove was found to degrade the breakdown voltage.

The first commercial Power MOSFET was the vertical diffused (VD) MOSFET in the mid

1970’s, which is illustrated in figure 1.4.

Figure 1.4: VD-MOSFET structure

The non-uniform current distribution enhances its resistance (JFET region), making the

internal resistance of the VD-MOSFET structure larger than the ideal specific ON-resistance

Drain

N+

N+substrate

Channel

N-drift-region

P-base P-base N+

JFET region

Source

Gate

Drain

N+

Source

Gate

N+substrate

Channel

N-drift-region

P-base P-base N+


14

of the drift region. The large internal resistance of the VD-MOSFET structure provided motivation for the development of the trench-gate power structure in the 1990’s.

The U-MOSFET is shown in figure 1.5. There is no JFET region in the structure, enabling

a reduction of the internal resistance when compared to the VD-MOSFET structure.

Figure 1.5: U-MOSFET structure

One important drawback of the vertical devices is the fact that it is difficult to include

multiple power devices on the same monolithic chip. The lateral structure allows all terminals to be accessed from the top surface of the chip. The current flows from the drain, laterally along the surface through the MOS channel and up into the source, hence the name Lateral DMOSFET (LDMOSFET) as shown in figure 1.6 [11, 13-15].

LDMOSFET generally suffers a higher specific ON-resistance due to the longer current path. Furthermore, the blocking voltage of the LDMOSFET depends critically on the curvature of the P-body to N-drift region junction. In order to obtain high blocking voltage, it is necessary to use a low doping concentration in the N-drift region. However, this directly contradicts with the low specific ON-resistance requirement. It must be optimized to achieve high breakdown voltage with low RON,SP.

Figure 1.6:LDMOSFET structure

Drain

P-body N+

Source Gate

N+ Drift-region N-epitaxy

P-substrate

Bulk

Drain

N+

Source

Gate

N+substrate

Channel

N-drift-region

P-base P-base N+

Trench


15

1.4 Smart PIC fabrication processes

The smart power integrated circuit fabrication processes are classified into two categories, the dedicated processes and the compatible processes. 1.4.1 Dedicated processes

A dedicated smart PIC technology refers to a fabrication process with the optimization of the power devices at the highest priority. The performance of the low voltage CMOS devices is usually compromised. SGS Thomson is a long time advocate of such trend with their family of BCD (Bipolar-CMOS-DMOS) processes [9].

1.4.2 Compatible processes

The compatible approach is to integrate the power devices into an existing process. While this invariably would lead to a greater degree of compromise in the performance of the power devices; it is a significantly more cost-effective approach. The goal would be to minimize the number of additional steps that have to be introduced to the original process. This will ensure low production cost since most existing processes are already fine-tuned and are running at high volume.

The blocking voltage and specific ON-resistance ratings can be optimized by selecting the

appropriate doping profiles. The compatible approach is currently being adopted by many manufacturers for their existing CMOS processes, especially for out-dated processes. Since most of the production volume is being migrated to more advanced processes (e.g. BiCMOS processes), in order to maintain the existing process lines, new applications have to be found. Smart PIC technology is the ideal way to inject new life into these soon to be obsolete processes.

1.5 Isolation techniques In power integrated circuit (PIC) technology, power transistors are controlled by low-

voltage BiCMOS circuitry. Isolation between these two types of components, high power devices and control/logic circuitry, is necessary in order to avoid cross-talk and to ensure regular operation.

Under certain conditions a negative bias can be applied on the drain contact with respect to

the substrate of laterally diffused MOS (LDMOS) due to the switching of an inductive load. If the technology employs junction isolation this may lead to unwanted injection of minority charge carriers into the substrate. The resulting currents may lead to malfunction of the whole PIC device. Minority carriers injected into the substrate can cause disturbances of the signals in the low power circuitry or latch-up in the CMOS structures.

Several isolation techniques have been employed in order to protect the low voltage

CMOS circuitry from substrate currents originating from power transistors [1, 4, 16, 17].


16

1.5.1 Self isolation (SI)

Self isolation is characterized by a very simple process flow based on CMOS process with a few additional steps. However, as all devices in the same chip have to share the positive supply voltage, additional parasitics are introduced. Siemens smart SIPMOS technology is an example. 1.5.2 Dielectric isolation (DI)

Silicon on insulator (SOI) isolation whereby the active devices are completely surrounded by a nonconducting, dielectric layer is shown in figure 1.7. This technology provides excellent isolation, however, since the dielectric is a poor thermal conductor this may lead to serious thermal problems for the power devices. Additionally, SOI wafers are produced at significantly higher cost than conventional silicon wafers.

Figure 1.7 : Dielectric isolation

1.5.3 Junction isolation (JI)

Junction isolation (JI) does not suffer such serious self-heating problems however; the electrical isolation is much poorer. Standard junction isolation structures consist of a reversed

biased P-N junction as shown in figure 1.8 [11].

Figure 1.8: Standard junction isolation

1.5.4 Advanced junction isolation techniques To enhance the performance of the junction isolation structures, advanced techniques are used.

P+ P+

P-substrate

POWER DEVICE LOGIC CMOS P+

N-epitaxy N-epitaxy

P-substrate

Buried-oxide

N-epitaxy N-epitaxy

POWER DEVICE

LOGIC CMOS


17

1.5.4.1 Passive JI

In order to make the isolation more effective, an extra N-region is added and enclosed by two deep P-diffusions. The N-region is permanently tied to the highest potential of the circuit as shown in figure 1.9. Its purpose is to remove the minority carriers as close to their point of injection as possible [19].

Figure 1.9: Passive junction isolation

1.5.4.2 Active JI

A significant step forward has been achieved by introducing the multi-ring active analogic protection (MAAP) junction isolation (JI) as shown in figure 1.10. This self-triggered JI technique is able to reduce the current reaching the low power circuitry by up to several orders of magnitude compared with the passive JI.

In the MAAP device, ND and P2 are shorted and left floating as shown in figure 1.10. This

time, the on-chip metallization was implemented on the chip instead of external wiring to reduce the interconnect resistance Rvia.

Once injected from the drain side, electrons flow through the substrate and some of them

are collected by ND reducing the ND’s potential. This negative potential is now transferred through the metallization to P2, which adds to its built-in potential. P2 is now on lower potential than P1 and the resulting electric field will reject the substrate minority carriers injected from the drain of the power device.

Figure 1.10: Active junction isolation

POWER DEVICE LOGIC CMOS

N-epitaxy N-epitaxy

P+ P+

P-substrate

N+

N-epitaxy

MAAP ND P2 P1

POWER DEVICE LOGIC CMOS

N-epitaxy N-epitaxy

P+ P+

P-substrate

N+

N-epitaxy

V+


18

1.5.4.3 Active pull-down protection

Active pull-down protection combines junction isolation with a bipolar transistor that biases a P-substrate contact according to the injected current level. This isolation structure is highly effective; however, its complexity and number of variables to be considered may significantly increase the number of iterations during the design process. 1.5.4.4 Multiple structures

In an attempt to further improve the blocking capabilities of junction isolations, the use of multiple or combined structures has been investigated, whilst keeping the surface area used for isolation device as small as for the single structures. This means that the width for P and N diffusion zones is decreased in order to keep the total area the same.

1.6 Conclusion Smart power integrated circuits (ICs) offer a variety of advantages in terms of reliability,

reduction of interfaces, and reduced weight and size of the components. Considerable effort has been put into the development of smart power devices for automotive electronics, computer peripheral appliances, and portable equipments, such as cellular phones, video cameras, etc. It is expected to open up new applications based upon the added features of smart controls. The fabrication processes of SPICs are classified into two categories; the dedicated processes and the compatible processes. Isolation between high power devices and control/logic circuitry is necessary in order to avoid cross-talk and to ensure regular operation.

CHAPTER 2

Physics of lateral HV devices

Chapter 2: Physics of lateral HV devices

20


21

2.1 Introduction

A comprehensive study of the physical effects that take place in the HV devices is the subject of analysis in this chapter. The effect of the junction curvature on the breakdown voltage is explained. The factors that affect the safe operating area (SOA) of the device are discussed. Moreover, an analytical treatment of the REduced SURface Field (RESURF) principle is done.

2.2 Device characteristics for power semiconductor devices

In this section, we will discuss important device characteristics related to power semiconductor devices. These include the BV and ON-state characteristics [13, 20].

2.2.1 Avalanche generation

In order to compute the BV, it is necessary to determine the condition under which the impact ionization achieves an infinite rate. Generation of electron-hole pairs due to impact ionization requires certain threshold energy (approximately 3.6eV for electrons and 5.0eV for holes in silicon) and the possibility of acceleration of the energy of electrons and holes, i.e. wide space charge regions. If the width of the space charge region is larger than the mean free path of carriers, charge multiplication occurs, which can cause electrical breakdown.

Consider a reverse-biased parallel-plane P-N+ junction with a positive bias applied to the N+ region as shown in figure 2.1. Under the influence of the electric field E in the depletion region, the electron will be swept towards the N+ region and the hole will be swept towards the P region.

Figure 2.1: Reverse biased P-N+ junction

The total number of electron-hole pairs M(x) created in the depletion region by a single

electron-hole pair generated at a distance x is given by:

( )( )

( )∫ ∫∫

−−

−= W

x

xpnp

xpn

dxdx

dxxM

]exp[1

]exp[

0

0

ααα

αα (2.1)

Where W is the depletion layer width. M(x) is commonly known as the multiplication coefficient. The electron and hole impact ionization rates αn and αp are defined as the number of electron-hole pairs generated by the carriers traveling unit distance along the direction of

E Depletion region

N+

P

V

Electron Hole

x


22

the electric field. The breakdown voltage is defined as the voltage at which M(x) reaches infinity. It occurs if the following integral equals one,

( ) 1]exp[ 0 =−∫ ∫Wx

xpnp dxdxααα (2.2)

Where the left-hand side of equation is known as the ionization integral. Applying Fulop's power series an approximation for the impact ionization coefficient is [20]:

735 )108.1( Eeff ××= −α (2.3)

αeff is known as effective impact ionization coefficient. This expression is useful to derive a closed-form solution for the breakdown voltage of abrupt and linearly graded junctions.2.2.2 Breakdown voltage and ON-resistance relationship

The BV and ON-resistance of power devices are inversely related to each other. To obtain a lower ON-resistance while maintaining a higher voltage is one of the main issues for the design of power devices [20-22].

The unipolar power devices contain a drift region, which is designed to support the blocking voltage. The properties (doping concentration and thickness) of the ideal drift region can be analyzed by assuming an abrupt junction profile. The solution of Poisson’s equation leads to a triangular electric field distribution as shown in figure 2.2.

Figure 2.2: The ideal drift region and its electric field distribution

The specific ON-resistance of the ideal drift region is given by:

=

Driftn

DriftSPON Nq μ

LR , =

3

24

cns E μBV

ε (2.4)

The denominator ( 3

cns E με ) is referred to as Baliga’s figure of merit for power devices.


23

2.3 Junction edge effects

A cornerstone of modern semiconductor devices is the planar junction formed by the diffusion of impurities through a window in a silicon dioxide mask grown on the silicon surface as shown in figure 2.3.

Figure 2.3: Planar junction obtained by diffusion [20]

It is customary to thermally drive the doping atoms into the silicon at elevated

temperatures to produce junction depths appropriate for power devices. The dopants migrate vertically and laterally, producing a cylindrical-shaped junction at the edges and one-eight spherical-shaped junctions at the corners. At these locations, the electric field enhanced and the breakdown voltage lowered. 2.3.1 Cylindrical junction

The breakdown voltage of the cylindrical junction shown in figure 2.4 can be obtained by

solving Poisson’s equation in cylindrical-coordinates.

Figure 2.4: The cylindrical junction [20]

( )s

DqNrEdrd

rdrdVr

drd

r ε−=−=

11 (2.5)

The electric field distribution is given by:

( )

−=

rrrqNrE D

s

D22

2ε (2.6)


24

By comparing the maximum electric field for both parallel-plane junction and cylindrical junction and assuming that (rD=WD), one find that:

j

D

PPm

CYLm

rr

EE

2,

, ≅ (2.7)

2.3.2 Spherical junction

The behaviour of the spherical junction can be obtained by solving Poisson’s equation in spherical-coordinates.

( )si

DqNErdrd

rdrdVr

drd

r ε−=−=

2

22

211 (2.8)

The electric field distribution is given by:

( )

−= 2

33

3 rrrqNrE D

si

D

ε (2.9)

By comparing the maximum electric field for both spherical junction and cylindrical junction, it is found that:

j

D

CYLm

SPm

rr

EE

32

,

, ≅ (2.10)

From equations (2.7, 2.10) it is obvious that, Em,SP > Em,CYL > Em,PP. The normalized breakdown voltage for cylindrical and spherical junctions is plotted in figure 2.5 as a function of the normalized radius of curvature.

One can conclude that, for power devices to achieve large breakdown voltage, the depth of the junction must be increased. But this will increase also the capacitance and degrade the high frequency performance.

Figure 2.5: Breakdown voltages of cylindrical and spherical junctions normalized to parallel-plane case [20]


25

2.4 Planar junction breakdown improvement For improving the breakdown voltage of the planar junctions, several approaches are used. 2.4.1 Planar junction with field-plate

The field plate is formed by extending the contact metal over the field oxide at the edge of the junction as shown in figure 2.6.

Figure 2.6: Planar junction with metal field plate over the field oxide [20]

The electric field in the semiconductor is related to the electric field in the oxide in

proportion to their permittivity near the interface (Gauss’s law). Based upon this, the junction depth corresponding to an oxide thickness of tox is given by:

oxoxox

sij ttx 3≈

=

εε (2.11)

The length of the field plate and the field oxide thickness must be optimized to achieve the maximum allowable breakdown voltage. 2.4.2 Junction termination extension (JTE)

Another approach to alter the surface electric field at the edges is by adding charge to the junction as shown in figure 2.7.

Figure 2.7: Junction termination extension [20]

The charge can be adjusted by ion implantation. The charge within the JTE region must be precisely controlled to maximize the breakdown voltage. If the charge is small, it has little


26

impact on the electric field distribution and the maximum electric field will occur at point A. This will result in a breakdown voltage limited by the cylindrical junction curvature. If the charge in the JTE is high, it will serve as an extension of the junction to point B with a smaller radius of curvature. This will result in a reduction of the breakdown voltage.

To reduce the electric field at the main junction at point A without encountering

breakdown at point B, the charge in the JTE region must be such that it is completely depleted by the reverse bias. For this charge value, the electric field is distributed along the surface over the length (LJTE) of the junction extension. 2.5 MOS interface physics

The conductivity of the channel in the power MOSFET structure depends upon the density of carriers and their mobilities. The charge density in the channel is governed by the gate bias.

One dimensional structure is assumed with no electric field applied parallel to the surface. The energy band diagram is shown in figure 2.8. Here an ideal MOS structure is defined as one satisfies the following conditions:

1. The insulator has an infinite resistivity, 2. Charge can exist only in the semiconductor and on the metal electrode , and 3. There is no energy difference between the work function of the metal and the

semiconductor.

Under these conditions, there is no band bending in the absence of a gate bias and the band structure is known as the flat band condition [23, 24].

Figure 2.8: MOS structure operating under flat band condition

From figure 2.8, it can be observed that: qφΜ = qχS+EG/2+qψB=qφΒ+ qχO (2.12) Where, φΜ is the work function of the metal, χS is the electron affinity of the semiconductor,

EG is the energy band gap for the semiconductor, ψB is the potential difference between the

EC

qφS

EG/2

qψΒ

EV

qφM

d Metal Semiconductor

Oxide

Vacuum Level

Ei EF

qχO qχS


27

intrinsic and Fermi levels in the bulk of the semiconductor, φΒ is the barrier height between the metal and the oxide, and χO is the electron affinity of the oxide.

The MOS structure at various gate biases is shown in figure 2.9. Three different cases are distinguished according to the gate bias.

When a negative bias is applied to the metal electrode in the MOS structure, the negative charge developed in the metal attracts the positively charged holes in the semiconductor toward the interface between the semiconductor and the oxide as shown in figure 2.9a. The presence of the excess majority carriers at the surface of the semiconductor is referred to as accumulation.

When a positive bias is applied to the metal electrode in the MOS structure, the positive charge developed in the metal repels the positively charged holes in the semiconductor away from the interface between the semiconductor and the oxide. At small positive bias voltage, the semiconductor at the oxide interface becomes depleted, leading to the energy band bending as illustrated in figure 2.9b.

As the positive bias applied to the metal electrode in the MOS structure is increased, the

band bending also increases until the intrinsic level crosses the Fermi-level. The semiconductor surface now has the properties of an N-type semiconductor as shown in figure 2.9c. The free electrons created within this inversion region form the channel in the power MOSFET structure.

(a) (b) (c)

Figure 2.9 : MOS structure at various gate biases 2.5.1 The threshold voltage

The voltage on the gate electrode at which strong inversion begins to occur in the MOS structure is an important design parameter for power MOSFETs because it determines the minimum gate bias required to induce an N-type conductance in the channel. This voltage is called the threshold voltage. For proper device operation, its value can be neither too large nor too small.

If the threshold voltage is large, a high gate bias voltage will be needed to turn-ON the power MOSFET. This imposes problems in the design of the gate drive circuitry. It is also important that the threshold voltage not be too low. Because of the existence of charge in the gate oxide, it is possible for the threshold voltage to be negative for N-channel power MOSFETs. This is an unacceptable condition because a conductive channel will now exist at zero gate bias voltage; that is, the device will exhibit normally ON characteristics. Even if the threshold voltage is above zero for an N-channel power MOSFET, its value should not be too


28

low because the device can then be inadvertently triggered into conduction either by noise signals at the gate terminal or by the gate voltage being pulled up during high-speed switching.

Box

sTHG C

QVV ψ2+==

)ln(2/

)/ln(4

2)/ln(4

i

A

oxox

iAAs

Box

iAAs

nN

qKT

tnNNKT

CnNNKT

+≅

+≅

εε

ψε

(2.13)

In actual MOS structures, the threshold voltage is altered due to:

1. An unequal work function for the metal and the semiconductor, the difference between metal and the semiconductor work function can be obtained as,

)2

( BG

SOBms qEqqqq ψχχφφ ++−+= (2.14)

2. The presence of fixed surface charge QFC at the oxide-silicon interface, 3. The presence of mobile ions in the oxide with charge QI, and 4. The presence of charged surface states at the oxide-silicon interface with charge QSS.

All these charges cause a shift in the threshold voltage:

)(2ox

FCISSSBmsTH C

QQQQV

+++−+= ψφ (2.15)

As indicated by equation 2.15, the threshold voltage for inversion in an MOS capacitor is affected by the barrier height between metal and the oxide.

A greater control over the threshold voltage can be achieved by substituting polycrystalline silicon for the metal. The utilization of polysilicon provides a gate material that can withstand the high temperatures required during driving the dopants into the silicon in the vertical and lateral directions after the ion implantation. This process allows formation of submicron channels without high-resolution lithography.

The energy band diagrams for the case of silicon MOS structures with heavily doped polysilicon gate electrodes are illustrated in figure 2.10. The work function differences for the four possible MOS structures are shown in figure 2.11.

2.5.2 MOSFET capacitances

The ON-state current flow in a power MOSFET structure occurs by unipolar transport, namely, only electrons are involved for an N-channel device. The absence of minority carrier injection allows interruption of the current flow immediately after reduction of the gate bias below the threshold voltage.


29

Figure 2.10: Band diagrams for silicon MOS structures with heavily doped polysilicon gate regions [20]

Figure 2.11 : Work function difference for silicon MOS with polysilicon gate [20]

The process by which the majority carrier density is returned to equilibrium in a

semiconductor is referred to as the dielectric relaxation. The dielectric relaxation time is

given by: s

sd σ

ετ = , which is on the order of picoseconds. Although this implies a very fast

switching speed for the power MOSFET structure, in practice the switching speed is limited by the device capacitances. In an N-channel power MOSFET structure, the inversion layer channel is formed over the surface of a P-type base region. As shown in figure 2.12a, when a negative gate bias is applied, holes are attracted from the bulk toward the oxide-semiconductor interface to form an accumulation layer. As holes are the majority of the P-base region, the holes can respond to an AC signal superposed on the negative DC voltage. Consequently, the capacitance for the MOS structure becomes equal to that of the gate oxide under accumulation mode,

ox

oxoxACC t

CCε

== (2.16)

When a positive bias is applied to the gate electrode, a depletion region is formed in the P-

base as illustrated in figure 2.12b. The application of an AC signal superposed on the positive DC voltage produces a response only from the P-base region located at the edge of the


30

depletion layer because there are no mobile charges within the depletion region. Consequently, the capacitance for MOS structure becomes equal to that of the series combination of the gate oxide capacitance and the depletion layer capacitance. Under depletion mode operation,

soxDEP CCC111

+= (2.17)

Where Cs is the specific capacitance of the semiconductor depletion region.

Figure 2.12: Capacitances within the basic MOS structure [20]

When the positive bias applied to the gate electrode is increased, eventually an inversion

layer forms at the oxide-semiconductor interface. This is illustrated in figure 2.12b by mobile electrons. Once the inversion layer is formed, any further increase in the DC voltage applied to the gate electrode is supported across the gate oxide.

Despite the creation of a layer of mobile electrons at the oxide-semiconductor interface, the

application of an AC signal superposed on the positive DC voltage applied to the gate electrode produces a response only from the P-base region located at the edge of the depletion layer. Any variation in the charge must be produced by the carrier generation process. The space charge generation life time in silicon is usually far larger than the period of the AC signal (typically 1MHz).

Consequently, the charge in the inversion layer can not respond to the AC signal and the

capacitance of the MOS structure becomes equal to that of the series combination of the gate oxide capacitance and the depletion layer capacitance. Under inversion mode operation,

min

111

soxINV CCC+= (2.18)

The capacitance variation of the basic MOS structure is illustrated in figure 2.13. This

behaviour is observed in power MOSFET structures. In the power MOSFET structure, the inversion layer charge can be supplied from N+ source region circumventing the slow minority carrier generation process. Consequently, at large positive gate bias voltages, the capacitance is shown by the dashed line in figure 2.13. Furthermore, a deep depletion region forms.


31

Figure 2.13 : Capacitance variation for a basic MOS structure [20]

2.6 A safe operation area

The term ‘Safe Operation Area’ is used to describe the region in the ID -VDS plane through which the device can switch without suffering damage. As the operating point approaches the SOA boundary, the slope of the curve increases and eventually becomes infinite at the boundary. Beyond this ‘snapback’ point, the device exhibits negative resistance and fulmination occurs, usually with accompanying damage to the device [25-30].

Figure 2.14: LDMOS design triangle showing trade-offs that affect device SOA

The determination of SOA is not a simple matter. Current, voltage, waveform, stress time, and temperature are all involved in defining the SOA. 2.6.1 Short-term SOA 2.6.1.1 Electrical effects 2.6.1.1.1 Kirk effect

For lateral HV devices (see figure 1.6) at high current density, the moving carriers influence the depleted charge, which result in higher electric field near N/N+ junction. This is called Kirk effect. In the ON-state, significant amount of negative charge adds to the positive space charge of the N-type drift region. It leads to a shift of the potential lines towards the drain. For application, the effect means the use of a longer drift region or less current per gate width [31].

Several methods have been proposed to alleviate Kirk effect. Adding an N-buffer region, whose concentration is higher than the drift region while lighter than the drain region, has been well-know. A double RESURF technology was put forward to improve SOA.


32

2.6.1.1.2 Parasitic BJT action

Conventional RESURF LDMOSFET consists of N+ source/drain, N-drift with low doping concentration to block high voltage, and field plate which reduces electric field at the gate edge. In LDMOS devices, there is an inherent parasitic NPN BJT that consists of N+ source, P-body and N-drift. When high drain current owes at high gate and drain voltages, the electron-hole pairs are generated by impact ionization and hole current Ib owes through the base of the parasitic BJT as shown in figure 2.15 [32].

Figure 2.15: Circuit model of LDMOS showing the intrinsic MOS and the parasitic BJT

At high gate voltage, depleted drift region is extended further to the N+ drain than that at

low gate voltage for the same drain voltage, and electric field at the drain is high enough to generate impact ionization. The crowding current around N+ drain is also high enough to generate a lot of impact ionization and the hole current owing through P-body turns-ON the parasitic BJT of LDMOSFET. After BJT is turned-ON, ID-VDS characteristic curves experience snap back phenomenon, resulting in the loss of gate control.

Therefore, to enhance the SOA performance of LDMOSFETs, the electric field around N+ drain should be released and the crowding current should be spread by enlarging the radius of N+ drain curvature by using a buffer layer. 2.6.1.2 Electrical–thermal effect 2.6.1.2.1 Thermal effect

With temperature increase, number of factors inside and outside the semiconductor limits the operation of the electronic devices and circuits. Every semiconductor has a certain number of thermal electron and hole carriers presented in the crystal. The concentration of these intrinsic carriers is exponentially dependent upon the temperature of the semiconductor,

KTE

vciGeNNn 2/−= (2.19)

Where T is the temperature (in Kelvin), K is the Boltzmann constant, EG is the energy bandgap of the semiconductor measured in electron-volts, and Nc and Nv are the effective electron and hole density of states, respectively. Some authors associate the fail of the semiconductor device with the intrinsic temperature of the substrate, which is defined by solving ni =Nsub [33].

With the increase of the intrinsic carrier concentration, leakage current of a reverse-biased P-N junction increases dramatically. This current is harmful to devices and circuits operation


33

2.6.1.3 Electrical–thermal coupling

As temperature is increased well above room temperature, the ability of carriers to move through a semiconductor crystal decreases. This arises because atoms in the crystal lattice have more thermal vibrational energy that results in more collisions with carriers moving through the crystal in response to an electric field [34-36]

The increase in semiconductor device resistance with temperature follows the formulation: R =R0 (1+T x), where R0 is the value of semiconductor device resistance in room temperature and x is usually between 1.5 and 2.5 for most semiconductors. The base-emitter voltage needed to turn-ON the parasitic BJT has a negative temperature coefficient in the range of 1.6–2 mV/K. 2.6.1.4 Self-heating

In the non-isothermal consideration of LDMOS, self-heating is essential to understand the operation limit of LDMOS. Self-heating refers to the condition when charge carriers are not able to transfer their excess energy to the lattice efficiently. A temperature difference is created between electrons and the lattice resulting in localized heating in the active area of the device. The localized heating is maximum, where electric field is maximum. 2.6.2 Long-term SOA 2.6.2.1 Hot-carrier effect

As the electric field increases, electrons and holes travelling in the channel and drift region may gain kinetic energy high enough to be injected to silicon dioxide and cause permanent changes in the silicon dioxide interface charge distribution. This defines the well-known hot-carrier effects, which is one of the major failure mechanisms affecting long-term reliability. In the case of LDMOS applied with high voltage to the gate and drain, hot-carriers impose severe limitations to long-term SOA (LT SOA) [37, 38].

As a matter of fact, hot-carrier effects are induced by high electric field. Consequently, any action devoted to reduce the peak/plateau of the electric field in the channel and the drift region can improve the ruggedness of LDMOS and increase the corresponding LT-SOA. 2.7 REduced SURface Field (RESURF) principle

In 1979, the reduced surface field (RESURF) concept was suggested [39-43]. The RESURF concept gives the best trade-off between the breakdown voltage and the ON-resistance of lateral devices. The technique provides the ability to form high-voltage lateral devices using an inherently low-voltage IC technology.

RESURF-based technologies allowed for a more efficient interface between low-voltage/ low-power logic/analog signals and high-voltage/high-power output devices. As shown in figure 2.16, the RESURF structure is constructed by a lateral P+/ N-epi diode and a vertical P-sub/ N-epi diode.


34

Figure 2.16: Cross-section of a lateral RESURF structure

The success of RESURF principle requires an optimization of key device/process

parameters (see figure 2.16): epi-layer doping concentration Nepi, epi-layer thickness Tepi, substrate doping concentration Psub, and device structural geometry.

The concept relies on reducing the lateral (surface) electric field of the P+/ N-epi diode,

which represents the structure’s weakest point for breakdown (most susceptible junction to high electric field) therefore enabling higher voltages to be applied . 2.7.1 Analysis of the RESURF principle.

At any given applied reverse voltage Vapp, the basic lateral RESURF structure shown in figure 2.16 can be considered as a composite of two planar diodes.

In figure 2.17, Xlat represents the P+/ N-epi depletion region extension into the N-epi layer

at Vapp, and Xver represents the P-sub/ N-epi depletion region extension into the N-epi layer at Vapp. Actually, for this diode, Xlat approximates the depletion width of that junction at Vapp, and is given by :

( )epi

appsapplat Nq

VVX

ε2= (2.20)

Figure 2.17: The resulting space-charge sharing when the two diodes are merged together

Tepi P+

N+ N-epi (Nepi)

P-sub (Psub)

LDrift Vapp

Xlat

Xver

Tepi P+ N+

N-epi (Nepi)

P-sub (Psub)

LDrift Vapp


35

The charge (per unit vertical area) supported by Xlat and the corresponding electric field are given by:

( ) latepiapplat XNqVQ = (2.21)

( )lat

app

s

latapplat X

VQVE

2==

ε, (Gauss’s law) (2.22)

As Elat approaches a critical field, breakdown occurs. The junction breakdown voltage of this diode for punch-through and nonpunch-through conditions is given by:

epi

clats

lat

latDrift

lat

latDriftlat Nq

EX

XLX

XLBV

2],[Min

2],[Min 2ε

×

−×= (2.23)

Where Eclat is the critical field of the junction. For the vertical diode, Xver is given by:

( ) ( )episubepi

subappsappver NPNq

PVVX

+=

ε2 (2.24)

The charge (per unit vertical area) supported by Xver is given by:

( ) epiverDriftepiappver TXLNqVQ = (2.25) The junction breakdown voltage of this diode for punch-through and nonpunch-through conditions is given by:

( )( )

( )( ) sub

cvers

epi

cvers

verver

ververepi

verver

ververepiver Pq

ENqE

BVXBVXT

BVXBVXT

BV22

],[Min2

],[Min 22 εε+×

−×= (2.26)

As evident by equation 2.26, the breakdown voltage of the vertical diode is much higher

than the one predicted by equation 2.23 for the lateral diode due to the presence of the typically lightly doped P-sub region.

Figure 2.17 illustrates the depletion region/charge distribution when the lateral and vertical diodes are merged together. Notice the depletion charge/region shared by the two junctions. The charge (per unit vertical area) supported by this region is given by:

( ) ηlatepiapplat XNqVQ =∆ (2.27)

Where, η(Vapp)=Xver(Vapp) / Tepi ≥ 0 As a result of this charge contribution from the vertical diode, the “effective” charge supported by the lateral diode Qlateff is lessened and is given by:


36

( ) ( ) ( )[ ] ( )applat

applatapplatapplateff

VQ

VQVQVQ

η−=

∆−=

1 (2.28)

Using equation (2.22), the equivalent “effective” lateral field due to Qlateff is given by:

( ) [ ] ( )[ ]

( )

( )( )

s

applateffepieff

applateff

app

applatapp

applatapplateff

VXNq

VXV

VXV

VEVE

ε

η

η

=

=

−=

−=

2

12

1

(2.29)

Where,

( ) ( )[ ]η−

=1

applatapplateff

VXVX (2.30)

( ) [ ]21 η−= epiappepieff NVN (2.31)

The equations (2.29-2.31) completely demonstrate the RESURF mechanism, and

quantitatively show the field reshaping/reduction effects. With the presence of the vertical P-sub/N-epi diode and the interaction of its space-charge region with the lateral space-charge region, the lateral depletion width spans a larger distance Xlateff compared to the case without the presence of the vertical diode. Accordingly, the lateral electric field at the P+/N-epi junction Elateff gets much reduced, therefore enabling higher voltages to be applied (see figure 2.18(a)). From figure 2.18(b) and by assuming constant critical electric field Eclat (indeed Ec is a function of doping concentration), the resulting “effective” lateral junction breakdown voltage is now given by:

epieff

clats

lateff

lateffDrift

lateff

lateffDriftlat Nq

EX

XLX

XLBV

2],[Min

2],[Min 2ε

×

−×= (2.32)

Equation (2.32) quantitatively demonstrates the increase in the lateral breakdown voltage as observed in RESURF type structures.

Having determined the lateral breakdown voltage accounting for vertical charge coupling,

the breakdown voltage of the complete RESURF structure BVresurf is simply the minimum of BVlat and BVver . BVresurf =Min[BVlat, BVver] (2.33)


37

(a) (b)

Figure 2.18: Illustration of the lateral electric field reshaping for the structure in figure 2.16 (a) The electric field reduction due to the lower Nepieff value, and (b) BVlateff calculation as a result of the field reduction

2.7.2 Conditions of the RESURF principle.

From equations (2.29-2.31), η (through its dependence on Nepi, Psub, and Tepi) is a measure of the RESURF'ing efficiency and is critical for sensitivity analysis calculations. In RESURF structures, any of the following conditions may occur depending on the value of Nepi, Psub, and Tepi :

I) η = 0, this situation occurs only if there is no P-sub region, in such case, there is no charge coupling and Eresurf = Eclat. Accordingly, breakdown occurs at the P+/N-epi junction and is simply given by equation (2.23). II) 0 < η < 1, under RESURF’ing condition. Such situation may occur either when Tepi is made thick, Nepi is large, or Psub is very low. As discussed previously, such condition clearly illustrates the electric field reduction/reshaping mechanism. Here, breakdown occurs at the P+/N-epi junction and is given by equation (2.32). Figure 2.19(a) depicts an illustration of the charge and electric field distributions for such situation. III) η = 1, optimal RESURF’ing condition. In such situation, the epi-layer is fully depleted by the vertical junction. As a result,

0→lateffE , 0→epieffN , ∞→latBV , and verresurf BVBV → as predicted by equations (2.29-2.33), respectively. Since the breakdown of the structure is defined entirely by the vertical junction, this situation defines the optimal RESURF condition for operation. Although equations (2.31) and (2.33) predict 0→epieffN and ∞→latBV , in reality this is not the case. Actually, once the epi-region is fully depleted, it behaves as a very low-doped (very high-resistivity) layer which for simplicity can be approximated by an intrinsic layer. Because of the low doping intrinsic behaviour of the epi-layer, BVlat is now limited only by the drift length LDrift and is given by:

Eclat

Xlat (BVlat) Xlateff (BVlateff)

Slope=qNepi /εs Area=BVlat

Slope=qNepieff /εs Area=BVlateff

Elat

Elateff

Xlat Xlateff

Slope=qNepi /εs Area=Vapp

Slope=qNepieff /εs Area=Vapp


38

BVlat=Eclat× LDrift (2.34) Consequently, the structure breakdown voltage is determined using equation (2.33). The charge and electric field distributions for this situation are illustrated in figure 2.19(b).

Figure 2.19: Illustration of the charge and electric field distributions for different η possible values (a) 0 < η < 1, under RESURF’ing condition, (b) η = 1, optimal RESURF’ing condition, and (c) η > 1,

over RESURF’ing condition

Tepi P+

N+

N-epi (Nepieff)

P-sub (Psub)

LDrift BVresurf

Xlateff

Xver

(a)

(b)

(c)

Qlateff

Elateff

Qlateff

Elateff

Elateff

Qlateff


39

IV) η > 1, over RESURF’ing condition. This situation arises when Tepi is made thin, Nepi is very low, or Psub is very high. Here, the N-epi region is “already” fully depleted by the vertical diode at voltages less than BVlat. In such condition, as predicted by equation 2-29, the electric field Elateff changes sign and the fully depleted N-epi layer now appears to behave as P-type equivalent. Now, another junction becomes critical, N+/N-epi junction. Accordingly, in such cases, breakdown occurs at the N+/N-epi junction. The charge and electric field distributions for this situation are illustrated in figure 2.19(c).

2.7.3 Double-RESURF effect

Similar to the single-RESURF effect stated, another RESURF effect can be achieved in lateral devices where an additional layer of opposite conductivity (P-top region) is incorporated inside the N-epi region (see figure 2.20). In such structure, the vertical depletion of the N-epi region is supported by two junctions: the P-substrate/ N-epi and the P-top/ N-epi. Such device structure is referred to as double-RESURF [44, 45].

Because of the two-sided vertical depletion in double-RESURF devices, the total integrated charge Qn in the N-epi layer can be increased allowing the ON-resistance to be decreased compared to single-RESURF devices. In order to maintain high breakdown voltages in double-RESURF devices, it is required that both the P-top and the N-epi regions be fully depleted.

Actually, in double-RESURF technology, the additional P-top layer requires a tight charge control and, therefore, adds more complexity to charge control requirements. 2.7.3.1 Theory and analysis

For the basic single-RESURF structure, and as a requirement to achieve the benefit from

RESURF effect, the vertical full depletion of the N-epi region has to take place before the lateral diode breaks down. Since the lateral diode is the most susceptible junction to high electric field (i.e., represents the weakest breakdown point), this requirement causes the electric field at that junction to reduce and leads the structure to breakdown at another higher voltage than the one predicted by equation (2.23).

Figure 2.20: Cross section of a lateral double-RESURF structure showing the P-top region

Tepi P+

N+

N-epi (Nepi)

P-sub (Psub)

LDrift Vapp

P-top (Ptop)


40

Therefore, to ensure full vertical depletion of the N-epi, it is required that:

Xver (BVsr) ≥ Tepi (2.35) Where, Xver (BVsr) is the vertical depletion extension into the N-epi at BVsr . As a result, in single-RESURF devices, the optimal N-epi integrated charge Qnsr = Nepi × Tepi is given by :

Qnsr ≤ 2×1012.episub

sub

NPP+

(2.36)

In the above equation, we assume nonpunch-through BV and Eclat ≈ 3×105 V/cm is taken. When processing and forming doped regions in IC technologies, and in order to have

reasonable control over the thickness and doping concentrations of these regions, it is essential that the doping concentration of the N-epi region be higher than that of the P-substrate. In other words, Nepi > Psub. Consequently, an upper “theoretical” bound for Qnsr can be obtained by setting Nepi = Psub in equation (2.36) and is given by:

max,nsrQ = 1.4×1012 (2.37)

Similarly, for the double-RESURF structure shown in figure 2.20, it is essential that the doping concentration of the P-top region (Ptop) be such that Ptop > Nepi > Psub. In such cases, the weakest breakdown point is at the lateral N+/P-top junction with breakdown voltage given by:

top

csdr .q.P

.Eε=BV

2

2

(2.38)

As was stated earlier, in order to achieve high breakdown voltages in double-RESURF

structures, full depletion of the P-top and N-epi regions is required. Here, and just like the case of single-RESURF devices, full depletion should occur before the lateral N+/P-top junction breaks down. Therefore, in the double-RESURF case, the following conditions must be met:

o Xptop (BVdr) ≥ Xjptop, where Xptop (BVdr) is the vertical depletion extension into the

P-top region at BVdr, and Xjptop is the junction depth of the P-top region. o Xver1(BVdr) + Xver2(BVdr) ≥ Tepi, where Xver1(BVdr) is the vertical depletion

extension into the N-epi region from the P-top/N-epi junction and Xver2(BVdr) is the vertical depletion extension into the N-epi region from the P-substrate/N-epi junction.

As a result, an expression for the optimal P-top integrated charge Qpdr = Ptop ×Xjptop and

the optimal N-epi integrated charge Qndr = Nepi ×Tepi can be determined as follows:

Qpdr ≤ 2×1012.episub

epi

NPN+

(2.39)


41

Qndr ≤ 2×1012.

+ episub

epi

NPN

+

+ )(.

episubtop

episub

NPPNP

(2.40)

Based on equations (2.39) and (2.40), an upper bound for Qpdr and Qndr can be determined as

max,pdrQ = 1.4×1012

max,ndrQ = 2.8×1012 (2.41)

As is evident by (2.41), the presence of the P-top layer in double-RESURF structures

allows the total charge in the N-well region to be increased by twice as much as that in single-RESURF, leading to a much lower ON-resistance. To be RESURF’ed properly for any Qndr and Qpdr, an additional relationship must be satisfied in double-RESURF structures, Qndr- Qpdr≤ max,nsrQ (2.42)

This relationship defines the charge balance requirements in double-RESURF structures. It dictates the requirements for the total effective charge defined by (Qndr -Qpdr). Based on (2.42), as Qpdr approaches zero (i.e., P-top vanishes), the integrated charge in the N-epi region Qndr should be bounded by the single-RESURF requirements defined by equation (2.37).

2.8 Conclusion Clear understanding of the transport physics and physical models used for the analysis of

power semiconductors is essential to obtain accurate simulation results and to study new device structures. A better investigation of the HV devices and understanding of the special effects is then needed. A comprehensive study of the physical effects that take place in the HV devices is done. The effect of the junction curvature on the breakdown voltage is explained. The factors that affect the safe operating area (SOA) of the device are discussed. Moreover, an analytical treatment of the REduced SURface Field (RESURF) principle is done.


42

CHAPTER 3

Designing RESURF LDMOS

Chapter 3: Designing RESURF LDMOS

44


45

3.1 Introduction

In recent years lateral double-diffused MOS transistors (LDMOSFETs) have become the preferred devices for monolithic high-voltage and smart power applications. The advantages over VDMOSFETs are a reduction in the number of fabrication steps, multiple devices on the same chip and compatibility with advanced VLSI technologies. LDMOSFETs with VLSI processes make the prospect of smart power ICs a reality.

There are two major categories of LDMOS devices. One is a conventional LDMOSFET, and the other is a RESURF LDMOSFET. The conventional LDMOSFETs usually require thick and low doped epitaxial layer, which makes them difficult to integrate with low-voltage circuitry. Because of the high-resistivity epitaxial layer, the ON-state resistance of such devices is large. But, when the RESURF concept (see details in 2.7) is applied, it gives the best trade-off between the breakdown voltage and the ON-resistance.

In this chapter, a general purpose RESURF LDMOS is designed and simulated. Device simulations with advanced TCAD tools are essential to investigate the physical phenomena and electrical characteristics. We have utilized a commercial device simulator ISE-TCAD (GENESISe). The simulator provides facility for performing simulation in both 2D and 3D. The software provides a convenient framework to design, organize, and automatically run complete TCAD simulation projects. It provides a graphical user interface (GUI) to drive a variety of ISE simulation and visualization tools, and to automate the execution of fully parameterized projects [46].

3.2 The RESURF LDMOS structure

The schematic cross-section of a general-purpose RESURF LDMOS is shown in figure 3.1. In this structure, the effective channel length LCH is defined by the difference in the lateral diffusions of the P-body and the N+-source regions (lateral double-diffused MOS transistor). So, the doping in the channel is laterally graded along the channel length from the N+-source to the K-point, which is called the intrinsic drain (the metallurgical junction between the P-body and the N-epitaxy regions). The LDMOS channel length depends only on the process (the vertical junction depth and doping concentration) and not on the device layout [10, 47].

By introducing the P+ doping region, the channel is grounded through the P-substrate. Hence, the punch-through breakdown is impossible between the source and the substrate. LACC is the length of the accumulation region, that is formed in the linear region of operation when VG-VFB >VK. LGFP and LDFP are the lengths of field plates of the gate and the drain, respectively, which are used to overcome the curvature of the junctions (see section 2.4), and hence to reduce the surface electric field in the gate and drain regions. LDrift and Tepi are the length and the thickness of the drift region, respectively.

Power semiconductors are used as switches, and there are static and dynamic considerations for them [48]. The static considerations include: OFF state: breakdown voltage, leakage currents. ON state: drive current, ON-resistance, current handling capability, power dissipation, safe operating area (SOA).


46

The dynamic considerations include: Switching speed, storage time, power dissipation, safe operating area (SOA) To achieve these characteristics, proper device design and optimization are needed. 3.3 RESURF LDMOS design

In this section, the general-purpose LDMOS structure in figure 3.1 is optimum designed by using the RESURF principle conditions in chapter two (optimum RESURF'ing efficiency condition). Analytical conditions for the optimum epitaxial doping concentration (Nepi,opt), the minimum drift length (LDriftmin), and the minimum channel length (LCHmin) are derived [49]. 3.3.1 The optimum epitaxial doping concentration (Nepi,opt)

Starting from a defined substrate concentration Psub=3.0E+15 cm-3, the optimum epitaxial concentration (Nepi,opt.) is the concentration which achieves maximum breakdown voltage of the structure and gives the best trade-off between the breakdown voltage and the ON-resistance. This occurs by applying the RESURF principle for the optimum case (see section 2.7 case III). Xver(BVver) = Tepi (3.1)

⇒ ( ) ( ) epioptepisuboptepi

subversverver T

NPNqPBVBVX =

+=

,,

2ε (3.2)

And,

sub

cvers

optepi

cversver qP

EqN

EBV22

2

,

2 εε+= =

+

suboptepi

cvers

PNqE 112 ,

2ε (3.3)

optepi

cversepi Nq

ET,

1×=⇒

ε (3.4)

Figure 3.1 : The schematic cross-section of the RESURF LDMOS

Drain

P-body N+

Source Gate


P-substrate

P+

LGFP

LDrift Tepi

LACC LCH

Bulk

LDFP

K


47

Where Ecver is the critical electric field, which is given by [20]:

81

.4010 Dcver NE = (3.5)

Combining equations 3.4 and 3.5,

⇒7

8

,4010

=

epi

soptepi qT

N ε (3.6)

As evident by equation 3.6 (figure 3.2), the optimum epitaxial concentration Nepi,opt is

dependent only on the epitaxial layer thickness Tepi.

1.0E+14

2.1E+15

4.1E+15

6.1E+15

8.1E+15

1.0E+16

1.2E+16

1.4E+16

1.6E+16

1.8E+16

0 1 2 3 4 5 6 7 8 9 10

Tepi(µm)

Nep

i,opt

(cm

-3) Nepi>Nepi,opt

Breakdown occurs at P-body/N-epi junction

Nepi<Nepi,opt

Punch-through Breakdown occurs at N+/N-epi junction

Figure 3.2 : The optimum epitaxial doping concentration as a function of the epitaxial layer thickness

Actually, in the optimum case, the breakdown is limited by the drift length LDrift. So, to achieve breakdown at the vertical P-sub/N-epi junction, BVlat > BVver ,

c

verDrift E

BVL ≥⇒ (3.7)

3.3.2 The minimum channel length (LCHmin)

The effective channel length LCH is defined by the difference in the lateral diffusions of the P-body region and the N+-source region and its value must be ensured to avoid channel punch-through breakdown.

For laterally graded channel, the threshold voltage VTH is determined by P-body doping

concentration at the source side, as the P-body doping decreases along the channel length from the source side to the P-body/N-epi junction.

( )

ox

FsourceCHsFFBTH C

PqVV

φεφ

42 ++= (3.8)


48

A minimum channel length LCHmin must be ensured to prevent punch-through between drain and source. Assuming that the P-body/N-epi junction has a linearly graded doping distribution in the channel side and abrupt in the drift region of the junction as shown in figure 3.3, the depletion layer width in the channel is given by [20]:

31

3

= r

s VqG

W ε (3.9)

Where G is the slope of the graded junction (P-body/N-epi junction) and Vr is the reverse voltage.

Figure 3.3 : P-body/N-epi junction doping distribution

The slope G can be approximately defined as the ratio of the difference between the P-body doping concentrations at the boundaries of the channel to the channel length.

( ) ( )

CH

driftCHsourceCH

LPP

G−

= (3.10)

Where PCH(source) is the doping concentration at the source end and PCH(drift) is that at the drift end.

Assuming the punch-through condition is reached when the channel becomes completely depleted by the drift junction, the minimum channel length required to avoid punch-through is given by:

( ) ( ) )(33

31

mindriftCHsourceCH

PTsPT

sPTCH PPq

VV

qGWL

−=

==

εε (3.11)

Where WPT is depletion layer width in the channel at the punch-through breakdown voltage VPT.

By using the Fulop’s approximation for the impact ionization coefficients and the electric

field distribution of the linearly graded junction, WPT and VPT can be obtained [20]:

529102.9 −×= GVPT (3.12)

1575min 106.5 −×== GWL PTCH (3.13)

P-body N-epi (Drift-region)

LCH

Source

X

Dop

ing

Con

cent

ratio

n


49

3.3.3 The specific ON-resistance ( RON,SP )

RON =RN+source + RCH +RDrift +RN+drain (3.14)

Where RN+source is the source contact resistance, which is given by:

ZXNqL

RjNN

sourceNsourceN

++

+

+ +=µ

(3.15)

Where LN+source is the length of the source contact and XjN+ is the junction depth. RN+drain is the drain contact resistance, which is given by:

ZXNqL

RjNN

drainNdrainN

++

+

+ +=µ

(3.16)

Where LN+drain is the length of the drain contact and XjN+ is the junction depth RCH is the channel resistance and is given by:

( ) ZVVCL

RTHGoxinv

CHCH −

=µ

(3.17)

RDrift is the drift region resistance and is given by:

ZTNqL

RepiepiNepi

DriftDrift µ

= (3.18)

RON,SP= RON × Z WP (3.19) Where, Z is the device width and WP is the pitch length.

From the equations above, one find that RDrift is the dominant resistance in RON,SP .So, there is a conflict between the value of the breakdown voltage and the value of the specific ON-resistance.

3.4 RESURF LDMOS parametric analysis

In this section the LDMOS parameters are optimized by using 2D TCAD numerical simulations. There are many device/process parameters that should be optimized to achieve the required characteristics [50-53]. The drift region doping concentration Nepi , thickness Tepi ,and length LDrift are optimized by applying the RESURF principle to achieve proper breakdown voltage (BV) and specific ON-resistance (RON,SP) for certain substrate doping concentration Psub.

The RESURF principle helps to achieve maximum breakdown voltage by reducing the surface electric field. To overcome the junction curvature and reduce further the surface electric field, field plates at the gate and the drain are used and their lengths are optimized [54].


50

The accumulation layer length LACC is also optimized as it affects the value of the specific ON-resistance. The channel length LCH also is optimized to avoid premature channel punch-through breakdown. This can be achieved by proper choosing of the P-body doping concentration.

3.4.1 Effect of the epitaxial doping concentration (Nepi)

In this sub-section, the effect of the drift length LDrift and epitaxial doping concentration Nepi on the breakdown voltage (BV) and specific ON-resistance (RON,SP) are discussed. Also the distribution of the potential, the electric field, and the impact ionization are shown. In these 2D numerical simulations, a substrate doping concentration Psub of 3×1015 cm-3 and epitaxial thickness Tepi of 4µm, are used.

The breakdown voltages (BV) and the specific ON-resistances (RON,SP) of the LDMOS structure for different epitaxial doping concentrations Nepi are shown in figure 3.4.

50

100

150

200

250

300

350

400

450

1.0E+14

5.0E+14

1.0E+15

5.0E+15

6.0E+15

8.0E+15

1.0E+16

1.2E+16

1.5E+16

2.0E+16

Nepi (cm-3)

BV (V

)

0.00

0.05

0.10

0.15

0.20

0.25

RON

,SP (

Ω.c

m2 )

Breakdown voltage


Figure 3.4: Breakdown voltage and specific ON-resistance as a function of epitaxial doping concentration

at LDrift = 21.5 µm The breakdown voltage increases with increasing the epitaxial doping concentration until

Nepi=6.0E+15 cm-3, then it decreases with increasing the doping concentration. This result reflects very well the RESURF principle which stated that the maximum breakdown voltage is achieved at Nepi,opt (see figure 3.2).

For our case, the maximum breakdown voltage is achieved in the vicinity of Nepi=6.0E+15 cm-3. From figure 3.2 for Tepi= 4µm, Nepi,opt = 6.1E+15 cm-3, which is independent on the substrate doping concentration Psub. The specific ON-resistances (RON,SP) decreases with increasing the doping concentration. This is matched with equation 3.18. The potential distributions of the LDMOS at breakdown for three different values of Nepi are shown in figure 3.5.

When the Nepi is in the vicinity of Nepi,opt, the potential lines are uniformly distributed along

the drift region (optimal RESURF’ing condition) (figure 3.5c). In this case, BV is increased and the surface electric field is decreased.


51

(a) (b)

(c)

Figure 3.5 : Potential distribution at breakdown for (a) Nepi = 1.0E+14 cm-3, (b) Nepi =2.0E+16 cm-3, and (c) Nepi = 6.0E+15 cm-3 , at LDrift =21.5 µm

The electric field distribution is shown in figure 3.6 for the same cases of Nepi of figure 3.5 [55]. For Nepi = 2.0E+16 cm-3, a high electric field is seen at the gate edge and only a low electric field is found at the drain edge. For the other extreme case when Nepi = 1.0E+14 cm-3, it is noticed that the slope of the electric field changes its sign which means that the type of doping of the drift region is changed. So, the P-body /N-epi junction is no longer critical.

Figure 3.6 : Electric field distribution for different epitaxial doping concentrations at LDrift =21.5 µm

In fact, another junction becomes critical; the junction defined by the N+drain/N-epi.

Accordingly, in such case, maximum electric field is seen at the drain edge and the breakdown occurs at the N+/N-epi. For Nepi = 6.0E+15 cm-3, the electric field is uniformly distributed along the drift region.


52

The impact ionization distribution is shown in figure 3.7 for the same epitaxial doping concentration cases of figure 3.5. The avalanche breakdown occurs at the drain junction for low doped case. In this case, the generated holes move toward the source and can turn-ON the parasitic bipolar transistor formed from the source region, the body region, and the epitaxial region. If this parasitic transistor turns-ON, a snap-back is occurred in the ID -VDS characteristics and this limits the safe operating area of the LDMOS.

But, in case of high doping concentration, the avalanche breakdown occurs at the gate. In this case, the generated electrons move toward the gate oxide (hot carriers effect) and cause shift of the threshold voltage of the device and this cause degradation of all the device performance.

In the third case, when the doping concentration is in the vicinity of Nepi,opt, the avalanche breakdown occurs in the space charge region of the vertical diode between the epitaxial layer and the substrate. In this case the surface electric field is reduced. This reduction of the electric field helps to avoid the previous problems and to increase the breakdown voltage of the device.

(a) (b)

(c)

Figure 3.7: Impact ionization distribution at the breakdown for (a) Nepi = 1.0E+14 cm-3, (b) Nepi =2.0E+16 cm-3, and (c) Nepi = 6.0E+15 cm-3 , at LDrift =21.5 µm

3.4.2 Effect of the drift length (LDrift)

The breakdown voltage and the specific ON-resistance are shown in figure 3.8, as a function of the epitaxial doping concentration for different LDrift.


53

0

50

100

150

200

250

300

350

400

450

1.0E+14

5.0E+14

1.0E+15

5.0E+15

6.0E+15

8.0E+15

1.0E+16

1.2E+16

1.5E+16

2.0E+16

Nepi (cm-3)

BV

(V)

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

RO

N,S

P (Ω

.cm

2 )

LDrift=11.5 µm

LDrift=14.5 µm

LDrift=17.5 µm

LDrift=21.5 µm

Figure 3.8 : Breakdown voltage and specific ON-resistance as a function of the epitaxial doping

concentration for different LDrift The maximum breakdown voltage is achieved in the vicinity of Nepi=6.0E+15 cm-3. In

figure 3.9, the breakdown voltage and specific ON-resistance are drawn as a function of the drift length (LDrift) for Nepi=6.0E+15 cm-3.

It can be easily seen from figures 3.8 and 3.9 that, the maximum BV is approximately

unchanged for LDrift ≥ 14.5µm. For smaller values, BV is decreases progressively, which is matched with the RESURF analysis and equation 3.7 for LDriftmin.

250

270290

310

330350

370

390410

430

21.5 17.5 14.5 11.5 9.5LDrif t (µm)

BV (V

)

0.0E+00

2.0E-03

4.0E-03

6.0E-03

8.0E-03

1.0E-02

1.2E-02

1.4E-02

RON

,SP (

Ω.cm

2 )

Breakdown voltageSpecific ON-resistance

Figure 3.9: Breakdown voltage and specific ON-resistance as a function of the drift length at

Nepi = 6.0E+15 cm-3

Electric field distribution at breakdown for different LDrift at Nepi = 6.0E+15 cm-3 is illustrated in figure 3.10. For all drift lengths, the electric field is distributed along the drift region, but its values are increased with decreasing the drift length.

So, for best trade-off among the breakdown voltage, the surface electric field, and the specific ON-resistance, LDrift = 17.5µm, and Nepi = 6.1E+15 cm-3 can be taken in our design.

LDriftmin=14µm


54

Figure 3.10 : Electric field distribution at breakdown for different drift length at Nepi = 6.0E+15 cm-3

3.4.3 Effect of Tepi for Ldrift =17.5µm

From figure 3.2, the optimum value of the epitaxial doping concentration at constant drift length is only a function of the drift thickness; this effect is illustrated in figure 3.11a. In figure 3.11b, the specific ON-resistance as a function of Nepi is shown and the results are agreed with the analytical expresion of equation 3.19.

50

100

150

200

250

300

350

400

450

500

1.0E+14

5.0E+14

1.0E+15

5.0E+15

6.0E+15

8.0E+15

1.0E+16

1.2E+16

1.5E+16

2.0E+16

Nepi (cm-3)

BV

(V)

BV for Tepi=3µm

BV for Tepi=4µm

BV for Tepi=5µm

0.00

0.05

0.10

0.15

0.20

0.25

1.0E+14

5.0E+14

1.0E+15

5.0E+15

6.0E+15

8.0E+15

1.0E+16

1.2E+16

1.5E+16

2.0E+16

Nepi (cm-3)

RO

N,S

P (Ω

.cm

2 )

RON,SP for Tepi=3µm



(a) (b)

Figure 3.11: (a)Breakdown voltage, and (b) specific ON-resistance as a function of the drift length at Ldrift =17.5µm

Electric field distribution at the breakdown for various epitaxial thicknesses at LDrift =

17.5 µm, and at Nepi = Nepi,opt = 6.1E+15 cm-3 (the optimum doping for Tepi = 4 µm) is shown in figure 3.12. From the figure, it is obvious that the minimum and best uniform electric field distribution is for Tepi = 4 µm. For Tepi = 3µm, the electric field is maximum at the gate side as Nepi is greater than the optimum value defined in figure 3.2. 3.4.4 Effect of Psub for Nepi = 6.1E+15 cm-3 and LDrift =17.5µm

The effect of substrate doping concentration on the breakdown voltage and specific ON-resistance for LDrift=17.5 µm and Nepi = 6.1E+15 cm-3 is shown in figure 3.13. As the substrate doping concentration increases, the breakdown voltage decreases, equation 3.3, and the specific ON-resistance slightly increases, equation 3.19. This reflects the fact that RDrift is the dominant part of RON.


55

Figure 3.12 : Electric field distribution at breakdown for various epitaxial thicknesses

at LDrift=17.5 µm and Nepi=6.1E+15 cm-3

200

250

300

350

400

450

500

1.0E+15

3.0E+15

5.0E+15

7.0E+15

9.0E+15

1.2E+16

1.5E+16

2.0E+16

Psub (cm-3)

BV (V

)

8E-03

9E-03

9E-03

1E-02

1E-02

R ON

,SP (

Ω.c

m2 )

Breakdown voltageSpecific ON-resistance

Figure 3.13: The effect of substrate doping concentration on the breakdown voltage and specific ON-

resistance for LDrift=17.5 µm and Nepi = 6.1E+15 cm-3 3.4.5 Effect of LACC for Nepi = 6.1E+15 cm-3 and LDrift =17.5µm

Breakdown voltage and specific ON-resistance as a function of the accumulation length LACC for LDrift =17.5 µm and Nepi = 6.1E+15 cm-3 are shown in figure 3.14. It is noticed that, changing LACC causes a significant change in the specific ON-resistance and insignificant change in the breakdown voltage.

413

414

415

416

417

418

419

420

421

1 2 3.2 4LACC (µm)

BV

(V)

7.5E-03

8.0E-03

8.5E-03

9.0E-03

9.5E-03

1.0E-02

1.1E-02

RO

N,S

P (Ω

.cm

2 )

Breakdown voltage

Specific ON-resistance

Figure 3.14: Breakdown voltage and specific ON-resistance as a function of the accumulation length for

LDrift=17.5 µm and Nepi = 6.1E+15 cm-3 In figure 3.15, a simple model of the drift region is shown. This model represents the effect

of RACC on RON (the total resistance between points K and D) of the device. It is clear that, as LACC increases, RACC has more effect on the RON value, causes a decrease of its value.


56

Figure 3.15: Simple resistive model for the drift region The electric field increases with increasing the accumulation length as the accumulation

end becomes located deeply in the depletion region of the drift region. This is shown in figure 3.16.

Figure 3.16 : Electric field distribution at the breakdown for various accumulation lengths

for LDrift=17.5 µm and Nepi = 6.1E+15 cm-3 3.4.6 Effect of LGFP for Nepi = 6.1E+15 cm-3 and LDrift =17.5µm

Breakdown voltage and specific ON-resistance as a function of the gate field plate length LGFP for LDrift=17.5 µm and Nepi = 6.1E+15 cm-3 are shown in figure 3.17. It is noticed that, the breakdown voltage is approximately unchanged as soon as LGFP > 0. In case of gate field plate absence, the breakdown voltage decreases rapidly due to the effect of the lateral junction curvature. Also, the specific ON-resistance decreases insignificantly with increasing the gate field plate.

0

50

100

150

200

250

300

350

400

450

0 2 3 4LGFP (µm)

BV (V

)

8.6E-03

8.7E-03

8.8E-03

8.9E-03

9.0E-03

9.1E-03

R ON

,SP (

Ω.cm

2 )

Breakdown voltage


Figure 3.17 : Breakdown voltage and specific ON-resistance as a function of the gate field plate length

at LDrift=17.5 µm and Nepi=6.1E15 cm-3 Electric field distribution at the breakdown for various gate field plate lengths at LDrift =

17.5 µm, Nepi=6.1E15 cm-3 is shown in figure 3.18. In case of LGFP =0, the RESURF effect is

RDrift

RACC

D K


57

no longer sustained due to the junction curvature. For LGFP >0, the electric field is redistributed over the drift region according to length of the gate field plate.

Figure 3.18 : Electric field distribution at the breakdown for various gate field plate lengths

at LDrift=17.5 µm and Nepi=6.1E15 cm-3

3.4.7 Effect of LDFP for Nepi = 6.1E+15 cm-3 and LDrift =17.5µm

The drain field plate has insignificant effect on the breakdown voltage or the specific ON-resistance or the electric field distribution as shown in figures 3.19 and 3.20. This is because the junction N+/N has no influence in the optimum RESERF’ing case, which is our design case.

410

412

414

416

418

420

0 1 2 3LDFP (µm)

BV (V

)

9.40E-03

9.45E-03

9.50E-03

9.55E-03

9.60E-03

9.65E-03

9.70E-03RO

N,S

P (Ω

.cm2 )

Breakdown voltage


Figure 3.19 : Breakdown voltage and specific ON-resistance as a function of the drain field plate length

at LDrift=17.5 µm and Nepi = 6.1E+15 cm-3

Figure 3.20 : Electric field distribution at breakdown for various drain field plate lengths

at LDrift=17.5 µm, Nepi=6.1E15 cm-3


58

3.4.8 Effect of P-body doping on the threshold voltage

Figure 3.21 presents the effect of P-body doping on the threshold voltage. The numerical simulation results are matched with the analytical expression of VTH in equation 3.8.

To increase the current driving capability and the switching speed of the device, the channel length must be minimized and this can be achieved by increasing the P-body doping concentration to a limit which prevents the channel punch-through breakdown. This in turn causes the threshold voltage to increase. So, the P-body doping concentration must be optimally chosen to achieve these requirements.

0

0.5

1

1.5

2

2.5

2.0E+17 5.0E+17 6.0E+17 8.0E+17

PBody (cm-3)

VT

H (V

)

Figure 3.21 : P-body doping effect on the threshold voltage

3.5 The technological steps of the Buffered RESURF-LDMOS

The schematic cross-section of the Buffered RESURF-LDMOS is shown in figure 3.22.

The Buffer layer is added to decrease the electric field crowding at the drain to alleviate the Kirk-effect and to overcome the phenomenon of snap-back. This layer with the RESURF effect is the key to enlarge the SOA and to get the best trade-off between the breakdown voltage and the ON-resistance.

Figure 3.22 : The schematic cross-section of the Buffered RESURF LDMOS

From figure 3.5, it is observed that the values of the potential contours in the P+ sinker are

very small compared to the punch-through breakdown voltage. Hence, the P+ sinker implant step can be omitted from the process flow.

Bulk

Drain

P-body N+

Gate


P-substrate

LGFP

LDrift

LACC LCH LDFP

K

Tepi N-buffer

Source

Intrinsic MOS


59

By using the optimum parameters derived in section 3.4, the technological process steps of the general purpose RESURF LDMOS is shown in figure 3.23:

Figure 3.23: The LDMOS process steps

Using the process steps in figure 3.23, the 2D cross-section of the device with its layers doping concentrations is shown in figure 3.24. Doping profiles for lateral and vertical cuts are shown in figure 3.25. It is noticed from the inset of figure 3.25c, that the channel doping is laterally graded.

LOCOS Thickness = 0.8 µm

CHANNEL DOPING Boron for VTH adjustment

Dose =2×1011cm-2, Energy=30Kev

N-BUFFER Phosphorus, Dose=8×1013cm-2

SOURCE /DRAIN Arsenic, Dose =4×1015cm-2

BPSG Thickness = 0.5 µm

METALIZATION

SUBSTRATE Boron, orientation=<100> Concentration=3×1015 cm-3

Base BiCMOS technology Add-on steps for LDMOS

EPITAXY Phosphorus, thickness=4µm Concentration=6.1×1015cm-3

GATE FORMATION Gate oxide thickness = 0.01µm Polysilicon thickness = 0.5 µm

Poly doping with Arsenic, Dose =4×1015cm-3

, tilt =7

P-BODY Boron, Dose=2×1013cm-2


60

(a) (b)

(c)

Figure 3.25 : (a) The vertical absolute doping profile cut A-A, (b) The vertical absolute doping profile cut B-B, and (c) The lateral absolute doping profile cut C-C

By using the Buffer layer, the BV is reduced by a factor of 8.15 %, and the RON,SP is

reduced by a factor of 8.65 % as illustrated in figure 3.26.

Figure 3.24: 2D cross-section of RESURF LDMOS


61

50

100

150

200

250

300

350

400

450

with

Buf

fer-

laye

r

with

out

Buffe

r-lay

er

BV (V

)

9.0E-03

9.2E-03

9.4E-03

9.6E-03

9.8E-03

1.0E-02

1.0E-02

1.0E-02

1.1E-02

RON

,SP (

Ω.c

m2 )

Breakdown voltage


Figure 3.26 : Breakdown voltage and specific ON-resistance for RESURF-LDMOS with and

without Buffer-layer

A comparison of the electric field distribution in the two cases (with and without Buffer layer) is shown in figure 3.27. The Electric field at the drain-side is reduced by a factor of 16.35 %. It is clear that the distribution does not change over the drift region.

Figure 3.27 : Electric field distribution at breakdown in the OFF-state

3.6 The ON-state characteristics of Buffered RESURF-LDMOS

Before proceeding into understanding the ON-state behaviour of the LDMOS, we define first the intrinsic-drain VK. The K-point is the surface point of the metallurgical junction between the P-body region and the drift-region. It is of great interest for the characterization and modeling purposes as it will be shown in the following. The associated surface potential of the K-point is VK or ΨSL. 3.6.1 The intrinsic-drain VK

To explain the interest in K-point, the architecture of the device has to be taken into account. Furthermore, it was demonstrated that the intrinsic MOS device behaves like a low voltage MOSFET, the potential of the K-point remains low even when VDS and VGS are increased as shown in figure 3.28. Obviously, this voltage in conjunction with the one applied on the gate gives the operation regime of the intrinsic MOSFET.

From figure 3.28 (a), the K-point voltage rises with VDS, as an increase in the drain voltage

leads to a raise of the voltage drop on each part of the device. Figure 3.28 (b) shows that, the K-point voltage raises first with VGS, then, after exceeding the peak, this voltage decreases.


62

The explanation is strongly related on the charge analysis. The voltage VDS creates a depleted area in the drift. The major part of the drain voltage drops on this depleted area, so for constant VDS with the increase of VGS the K-point voltage increases.

In the same time, the increase of gate voltage creates an accumulation area at the surface of the thin oxide at the drain side. When this accumulation charge is enough high to compensate the depleted part of the drift zone and to create a conductive channel, VK potential reaches the maximum. Once the channel is formed in the drift zone, the potential lines redistribute all over the length of the conduction path, from the source to the drain. The redistribution of the potential lines at constant drain voltage leads to the decrease of the VK function of gate voltage.

Figure 3.28 : VK dependence on VDS and VGS

By using the K-point potential, it is possible to obtain the output characteristics of the

intrinsic MOSFET device (see figure 3.29). It can be easily observed from the characteristics that the distance between the currents is constant. The equal-distance between saturated currents is the mark of the saturation phenomenon via carrier velocity saturation in the intrinsic MOS channel.

It is also observed that, when the potential VK starts to decrease from its maximum boundary as indicated by the down arrow in figure 3.28a, the intrinsic MOSFET operates in linear mode as shown in figure 3.29. This is the onset of the quasi-saturation zone as the saturation of the output characteristics of the LDMOS is due to carrier velocity saturation in the drift-region. 3.6.2 DC effects in Buffered RESURF-LDMOS

We are now able to distinguish between the physical effects that take place in LDMOS.

The K-point (intrinsic drain) voltage provides a powerful and robust criterion for the separation between the different saturation mechanisms [56-59]. We will differentiate two saturation mechanisms:

o Saturation o Quasi-saturation

VDS

Maximum

VGS

Step = 0.5 V


63

Figure 3.29 : ID -VK characteristics

3.6.2.1 Saturation

The saturation mechanism (see figure 3.30) takes place in the intrinsic MOS part. Like in the case of normal CMOS transistors, there are two possible mechanisms for this phenomenon. For long channel devices the saturation occurs as a pinch-off at the drain side. The second mechanism is specific for the short channel devices and the saturation is dominated by carrier velocity saturation which is the explanation for our case. The maximum drain current is equal to (1.8mA/µm) at VGS = 5V. 3.6.2.2 Quasi-saturation

The quasi-saturation effect (see figure 3.30) is so far the most interesting and discussed phenomenon in high voltage devices.

Figure 3.30 : ID -VDS output characteristics of Buffered RESURF-LDMOS

The quasi-saturation consists in a limitation in the current level that can be attained in the

device. This limitation appears for high gate voltages and manifests as an insensitivity of the current to the increase in the gate voltage at high current levels. In quasi-saturation, the intrinsic MOS transistor is in quasi-linear regime. This explains the linear dependence of the current with the drain voltage, and the carrier velocity in the drift-region is saturated.

Quasi-saturation

Saturation

Step = 0.5 V

Quasi-saturation

Saturation

VGS


64

The transfer characteristic is shown in figure 3.31 for drain voltage of 150V. The threshold voltage for the proposed device is about 0.77V. It is observed that the transfer characteristic is nearly linear for this device, which means that the transconductance of this device is nearly constant. This is desirable for power amplifications as the distortion of the output is very small.

0.0E+00

5.0E-04

1.0E-03

1.5E-03

2.0E-03

2.5E-03

0 2 4 6 8 10

VGS (V)

ID (A

/µm

)

Figure 3.31 : Transfer characteristic at VDS = 150V

3.6.3 DC characteristics of Buffered 3D LDMOS

The structure of the Buffered 3D LDMOS is shown in figure 3.32a. The device has geometrical and process parameters the same as the optimized 2D Buffered RESERF-LDMOS and with device width equal to 10µm.

(a) (b)

Figure 3.32 : (a)The cross-section of Buffered 3D LDMOS, and (b)The potential distribution at breakdown The potential distribution at breakdown is shown in figure 3.32b. It is observed that,

changing the device width does not affect the RESURF principle, and the potential lines are uniformly distributed. Also, the device breakdown voltage changes a little bit with the device width, and it has approximately the same value of the 2D device breakdown which is 400 V.

The DC characteristics are shown in figure 3.33a. The maximum drain current at VGS =5V is equal to 18mA, which equals to IDmax.2D-LDMOS ×W. The saturation current and the ON-resistance are modulated with the device width. The current distribution is illustrated in figure 3.33b, at VDS = 400V and VGS = 5V.

Linear characteristic


65

(a) (b)

Figure 3.33 : (a) ID -VDS characteristics, and (b) The current distribution at VDS = 400V and VGS =5V 3.6.4 AC effects in LDMOS

Our goal in this section is the understanding of the charge variations. Physical effects are analyzed and discussed using 2D numerical simulations, which provide useful insights.

Before taking into discussion the charge and its variation in the device, it is useful to start with discussing the difference between the flat band voltage of the drift zone and the threshold voltage of the intrinsic MOSFET. All discussions concern the thin oxide on both sides of the metallurgical junction [48, 60]. From section 2.5, it is observed that the flat-band voltages for both intrinsic MOS and drift zone are negative. This remark is very important for the drift part which is supposed to work in accumulation. The intrinsic MOS part (P-type) works in inversion so of much interest is its threshold voltage which is positive. This remark is of great importance for the explanation of the C-V characteristics in the following discussion. 3.6.4.1 C-V curves and charge distribution

This sub-section is focused on the variations of the capacitances and the associated charges function of the gate and drain voltages. The definitions of these capacitances are given as:

GS

GGS dV

dQC = ,

GD

GGD dV

dQC = , where, QG represents the gate charge. The simulated structure is

source-body short connected, as these devices are often fabricated like this.

Figure 3.34a shows the variation of CGS as a function of VGS. At very low drain voltages, this dependence is similar to the one obtained for a low voltage MOS transistor at low frequency (quasi-static). It can be easily seen the transition from the depletion to inversion occurs around VGS = 0.75V, which is the value of the device threshold voltage. Unlike the case of a classical MOS transistor, these devices present totally different variations for the CGD capacitance.


66

(a) (b)

Figure 3.34 : (a) CGS dependence on VGS, and (b) CGD dependence on VGS

Moreover, CGD capacitance is more important than the rest of other capacitances below the threshold (see figure 3.34b), due to the charge accumulation on the drift side as it will be explained latter. The coupling between the gate and the drain is very important for low drain voltages, while the intrinsic MOS part is still in depletion mode (low VGS). Indeed, if very small voltage (or zero) is applied on the drain, the surface below the thin oxide in the drift zone is in accumulation. This could be valid even if zero bias is applied on the gate, as the flat-band voltage of this zone is negative (see figure 2.11).

Moreover, as the P-type part of the device (intrinsic MOS) is in depletion, it is reasonable

to suppose that, at the interface, electrons from the accumulation sheet diffuse into the depleted area. By gradually increasing the gate voltage between 0 and VTH, the accumulation charge increases in the drift, and consequently, the amount of electrons which diffuse in the P-part increases. The proposed mechanism explains well the observed increasing behavior of CGD capacitance and also confirms that the corresponding charge is coupled exclusively by the drain. TCAD simulation was used to verify the given explanation (see figure 3.35).

Figure 3.35: The accumulation layer in the drift zone at VDS =0.1V and VGS =0.4V

Furthermore, by increasing the gate voltage above the threshold, the intrinsic MOS part

starts to be inverted. An inversion layer in the P-part connected with the source and body of the transistor gives an increase in the capacitance CGS. Meanwhile, the gate-drain capacitance starts to decrease, as the electron-charge sheet is no longer connected only to the drain as it was before, but also to the source.


67

A much complex behavior is observed for the above-mentioned capacitances as the drain voltage is increased. Both, the gate-to-source and gate-to-drain capacitances present peaks as VGS voltage is swept. Easily to observe, the peaks for both capacitances are related and occur at the same value of VGS voltage. For the analysis, let’s take first the intrinsic MOS part. Below threshold, the gate-to-source capacitance increases slightly with VDS as the depleted area in the drift lowers the coupling between gate and drain. When the gate voltage exceeds the threshold the inversion is created in the P-part of the device. Consequently, the gate-to-source capacitance increases as this inversion area extents towards the intrinsic drain of the MOS transistor. Suppose the inversion area reaches the intrinsic drain. The gate-to-source capacitance attains a value which is around the plateau value obtained for VDS =0.

Further increase of the gate voltage extents the inversion layer in the depleted part of the drift. Essentially, the electrons are injected by the intrinsic MOSFET in the drift and, due to the action of the electric field, this charge remains at the surface, still, calling this charge “accumulation” is somehow improper as this charge is induced in and not accumulated in the drift. The extension of this electron sheet charge coupled to the source in the drift zone explains the uprising behavior of the CGS over the limit of inversion. The described effect takes place continuously and lasts till the charge injected in the drift is enough high to form a channel in the depleted area of the drift.

At this point it is interesting to describe also the behavior of the drift zone. The N-type area is analogous with two capacitances in series. The first capacitance is between the gate and the “accumulated” area in the drift, the second represents the drift depleted area. As more electrons are progressively injected in the depleted area of the drift zone with the gate voltage, the capacitance between the gate and the non-depleted drift area (on the drain side) increases. At some point, the amount of the injected charge in the drift is enough high to form the above-mentioned channel in the depleted area of the drift. This is represented by the aggressive increase of the depletion capacitance as the depletion thickness is reduced. The peak of CDG capacitance represents exactly the gate voltage for which the channel is completely formed in the drift.

The last detail that remains to be clarified is the decrease of the both capacitances at high VG voltage. Let’s take first the case when no channel is formed in the drift area. The depleted area in the drift zone is highly resistive; therefore there is a large voltage drop on this region. Once the channel is formed, the resistance of this zone decreases, and as a result, the potential lines rearrange on the entire drift region. The rearrangement of the potential lines induces the relocation of the charge in the entire structure. For this reason, the charge that compensates the gate charge contribution migrates, as VG increases more, from the interface of the thin oxide towards, and below, the thick oxide. The charge movement decreases both the CGS and CGD capacitances. The decrease is steep just after the channel is created, as the potential line rearrangement is fast.

3.7 Conclusion

A general purpose RESURF-LDMOS structure is designed based on 2D and 3D numerical TCAD simulations to verify the RESURF concept. The key device/process parameters are optimized to get the best trade-off between RON,SP and BV, as they are inversely related to each other. Reducing RON,SP while maintaining a BV rating has been the main issue of smart power


68

devices. By applying the REduced SURface Field (RESURF) concept, best trade off between the performance parameters is achieved.

For the general purpose 2D and 3D structures of the RESURF-LDMOS described, the

results show excellent RON,SP / BV trade-off of 9.5mΩ.cm2/ 400V. The maximum drain current obtained in the simulations is 1.8 mA/µm at a gate voltage of 5V. Also, VK variation is extracted as a function of the gate and drain voltages. Furthermore, it was demonstrated that the intrinsic MOS device behaves like a low voltage MOSFET; the potential of the K-point remains low even when VDS and VGS are increased. Obviously, this voltage in conjunction with the one applied on the gate gives the operation regime of the intrinsic MOSFET.

Once again, the correlation between the capacitances' variations and the intrinsic drain voltage VK is demonstrated. Unlike the case of a classical MOS transistor, these devices present totally different variations for the CGD capacitance.

CHAPTER 4 Designing LDMOSFETs in 0.35µm BiCMOS technology

Chapter 4: Designing LDMOSFETs in 0.35µm BiCMOS technology

70


71

4.1 Introduction

This chapter is focused on the development of LDMOSFETs using typical standard layers available in low voltage digital bulk 0.35µm BiCMOS technology (STMicroelectronics technology-like). The LDMOSFETS are developed by slight modifications of the base technological steps. Extra two masks are used for the body and the drift regions formations with slightly added thermal budget and without resorting to high-tilt implants [61-63].

The breakdown voltage of the proposed nLDMOS does not depend on the epitaxial layer thickness as in the conventional RESURF LDMOS of the previous chapter, so the proposed device is suitable for integration with low voltage CMOS with shallow epitaxial layers.

To understand the methodology to form LDMOSFETs, one must first survey the technological steps necessary to form CMOS in 0.35µm BiCMOS technology. Moreover, the electrical characteristics and important electrical parameters should be obtained.

For this reason, the first part of this chapter is specifically for the CMOS inverter and its electrical characteristics and how to modify the process to support high voltage with the minimum cost and thermal budget.

The structures of nLDMOSFET and pLDMOSFET in 0.35µm BiCMOS technology are

presented in the second and third parts of this chapter. The key device/process parameters optimizations are presented and the electrical characteristics are obtained. 4.2 The standard layers of 0.35µm BiCMOS technology The standard layers of the 0.35µm BiCMOS technology provided by ST Microelectronics are shown in figure 4.1, for both types of dopings on P-substrate.

(a) (b)

Figure 4.1: The 0.35µm BiCMOS technology standard layers

The corresponding doping profiles are shown in figure 4.2. It is obvious that, the substrate doping concentration is 2E15 cm-3 and the N-epitaxial doping concentration is 2.5E16 cm-3 and the P-epitaxial doping concentration is 1.25E17 cm-3. These values are very important in the following sections.

Psub

Nepi

Nburied

Ncontact

Psub

Pepi

Pburied

Pcontact


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(a) (b)

Figure 4.2: The 0.35µm BiCMOS technology doping profiles for (a) figure 4.1a, and (b) figure4.1b layers 4.3 CMOS inverter

This section describes the technological process steps of the CMOS in 0.35µm BiCMOS technology [64].

We start up with a lightly-doped P-type wafer (2E15 cm-3) and form the buried N+ layer by ion implantation of arsenic into the respective mask pattern. Afterwards, a high temperature anneal is performed to remove damage defects and to diffuse the arsenic into the substrate. During this anneal an oxide is grown in the buried N+ windows to provide a silicon step for alignment of subsequent levels. Therefore, the nitride mask is selectively removed and the remaining oxide serves as blocking mask for the buried P+ layer implant.

After finishing the alignment of the buried layer and the deposition of the epitaxial-layer a twin well process is used to fabricate the N-well of the pMOS and the P-well of the nMOS. As compared to conventional CMOS a relatively short well drive-in (100min) is performed at 1150 oC.

After the wells are fabricated, the whole wafer is planarized and a pad oxide is grown. The oxide is capped with a thick nitride. After patterning the active regions of the devices, an etch step is used to open up the field isolation regions. Prior to field oxidation, a blanket channel stop is implanted.

Oxidation is used to fabricate a 300nm thick field oxide. To minimize buried layer diffusion, the oxidation temperature is quite moderate (900 oC). Then the nitride masks are removed from the active regions.

We proceed with the resist strip and perform a pre-gate oxide etch to clean the oxide surface. A 7.6nm thick gate oxide is grown on top. Then a polysilicon layer is deposited. This polysilicon layer is implanted with arsenic for the nMOS and boron for the pMOS, the dopants will diffuse out from the polysilicon layer at the final source-drain anneal.

The polysilicon layer is patterned to define the CMOS gates. Phosphorus and boron are implanted to form shallow LDD regions for the nMOS and pMOS devices. Then the sidewall spacer formation is initiated. Therefore, an oxide layer is deposited and anisotropically etched


73

back. Next, the source-drain regions are heavily doped by phosphorus and boron, which is depicted.

Finally, the fabrication of the active regions is finished by the source-drain anneal. Hence, a 30s long RTA anneal at 850 oC is performed. The schematic cross-section of the CMOS including the active area dopings concentrations is shown in figure 4.3.

Figure 4.3 : The schematic cross-section of the CMOS

Conventional technologies are limited by gaussian profiles where surface concentration,

sheet resistance, and junction depth are directly coupled and the resulting threshold voltage is high. Low threshold voltages require either deep junctions or high sheet resistance.

The implanted wells in this technology are retrograde wells with peak charge resides 1µ

below the surface which allows spacing between N- and P-channel devices to be reduced from 12-15µ in conventional technologies to 3-6µ [64].

The retrograde well utilizes high-energy implant to produce a self-aligned channel stop and an extremely shallow, low sheet-resistance while maintaining controllable, low channel threshold voltages. It shunts the vertical device which is the key to successfully harnessing the parasitic vertical bipolar transistor.

Short channel effects can be minimized by increasing the background doping concentration and decreasing the gate oxide thickness. Shallow source/drain (≈ 0.2µm) is used to reduce short channel effects and overlap capacitance. The hot carrier effects are controlled by introducing the lightly-doped drains (LDD). In the light of the above mentioned technological steps, the CMOS 2D cross-section is shown in figure 4.4, and the technological process steps are summarized in figure 4.5.

Drain

Source

Gate

N+

P-substrate (2.0E15 cm-3)

NBL (3.5E18 cm-3) PBL (2.5E17 cm-3)

N-WELL (1.0E17cm-3) P-WELL (1.25E17 cm-3)

N+ N+ P+ P+

P+

pMOS nMOS

Source Gate

Drain

(2.0E19 cm-3) (2.0E19 cm-3)

(2.5E16 cm-3)

N-Epi


74

Figure 4.4: 2D cross-section of CMOS

Figure 4.5 : The process steps of 0.35µm BiCMOS technology

LOCOS

CHANNEL DOPING for VTH adjustment

SOURCE /DRAIN LDD

BPSG

METALIZATION

EPITAXY, ARSENIC

GATE FORMATION

RETROGRADE WELLS

OXIDE SPACERS

SOURCE /DRAIN

BURIED Layers

SUBSTRATE Boron , orientation=<100>


75

4.3.1 CMOS doping profiles

The vertical doping profiles are shown in figure 4.6 for the nMOS and in figure 4.7 for the pMOS. The doping profiles are matched with the standard layers of the 0.35 µm BiCMOS technology.

(a) (b)

Figure 4.6: nMOS vertical profiles (a) the channel, and (b) source/drain

(a) (b)

Figure 4.7: pMOS vertical profiles (a) the channel, and (b) source/drain 4.3.2 The static characteristics

The breakdown voltage of both nMOS and pMOS are shown in figure 4.8a and b. It is obvious that the absolute value of breakdown voltage of the devices is approximately 10 V. Their transfer characteristics are shown in figure 4.9. The threshold voltages of the transistors are approximately 0.6 V for nMOS and -0.65 V for pMOS. The ID -VDS characteristics are shown in figure 4.10. The maximum drain current is 1.2mA/µm for nMOS and 0.25mA/µm for pMOS. 4.4 Design of nLDMOS in 0.35µm BiCMOS technology

In this section, high-voltage n-type lateral double diffused MOSFET is designed in 0.35µm BiCMOS process. Extra two masks are used for the body and the drift regions formation with slightly added thermal budget and without resorting to high-tilt implants [65-70].


76

(a) (b)

Figure 4.8: OFF-state characteristics of (a ) nMOS, and (b) pMOS

Figure 4.9: nMOS and pMOS transfer characteristics

Figure 4.10: nMOS and pMOS ID -VDS characteristics

4.4.1 The nLDMOSFET structure

The schematic cross-section of the proposed nLDMOS is shown in figure 4.11. In this

structure, the effective channel length LCH is defined by the difference in the lateral diffusions of the P-body (LB-PWELL) and the N+-source region [71-77].


77

Figure 4.11 : The schematic cross-section of the proposed nLDMOS

LACC is the length of the accumulation region, that is formed in the linear region of operation when VG-VFB >VK. LGFP and LDFP are the lengths of the gate and drain field plates, respectively, which are used to overcome the curvature of the junctions, and hence to reduce the surface electric field in the gate and drain regions. LDrift and TDrift are the length and the thickness of the drift region, respectively. LS and Tpwell are the space length and the thickness of the Pwell region, respectively.

The technological processes steps are shown in figure 4.12. The same standard 0.35 µm BiCMOS technological steps are used, two steps are added. One for the Pwell formation and the other for Low thermal Budget LB-Pwell (body-region) using the smallest possible thermal budget to not affect the characteristics of the CMOS parts. The modifications to the standard process are as follows [78-80]:

After the buried layer alignment is finished, an N- epitaxial layer is deposited (EPITAXY1), then, the Pwell is implanted with dose=3E13 cm-2 and implantation energy = 240 keV. A short drive-in is performed (25min) at 1150 oC. A second N-epitaxial layer is deposited (EPITAXY2), then the whole structure is derived-in for (35min) at 1150 oC. The summation of the drive-in times for all the processes (buried layer+ epitaxial layers+ Pwell) is the same as the time taken to drive-in the buried layer and the CMOS retrograde wells in the standard process. So, no extra thermal budget is needed until now. After the LOCOS, a high energy LB-Pwell is implanted to form the body region of the nLDMOS transistor. A very short drive-in time is taken (8min) at 1150 oC, to not alter the low voltage devices characteristics.

Using these process steps, the 2D cross-section of the device with the doping concentration distribution is shown in figure 4.13.

N+

Bulk

Drain

LB-PWELL

Gate

N+

P-substrate

LGFP

TDrift

LACC LCH LDFP

K

N-Epi

NBL

PWELL

LDrift

LS Tpwell

Source


78

0.35µm BiCMOS technology Add-on steps for nLDMOS

Figure 4.12 : The process steps of nLDMOS in 0.35µm BiCMOS technology

Figure 4.13: 2D cross-section of nLDMOS

LOCOS

P-WELL

SOURCE /DRAIN LDD

BPSG

METALIZATION

SUBSTRATE /BURIED

LB-PWELL

EPITAXY1, ARSENIC

GATE FORMATION

RETROGRADE WELLS

OXIDE SPACERS

SOURCE /DRAIN

EPITAXY2, ARSENIC



79

4.4.2 Parametric analysis of nLDMOS

In this sub-section the impact of the proposed nLDMOS device/process parameters are studied by using 2D TCAD numerical simulations.

There are many parameters that should be optimized to achieve the required characteristics. The drift region thickness TDrift, and length LDrift must be optimized to reduce the surface electric field by using the RESURF principle.

The Pwell spacing LS , thickness TPwell, and doping concentration Pwell are optimized to achieve the best trade-off among the electrical parameters of the device.

4.4.2.1 Impact of Drift thickness (TDrift)

The impact of the drift thickness is illustrated in figure 4.14, at LDrift =7.5µm, TPwell =1.7µm, and LS =1.65µm. It is noticed that the breakdown voltage is slightly changed, which confirms that the breakdown is not a function of the drift thickness. The breakdown voltage depends only on the Pwell/N-burried metallurgical junction properties.

This result is on contrary to the conventional RESURF LDMOSFETs, which have

breakdown voltages function of the drift region thickness (see figure3.2). This dependency limits the integration of these devices with low voltage CMOS devices that use thin epi-layers as in the BiCMOS technology.

80

81

82

83

84

0.6 1.1 1.6 2.1

TDrif t (µm)

BV

(V)

0E+00

1E-03

2E-03

3E-03

4E-03

RO

N,S

P (Ω

.cm

2 )

Breakdown voltage


Figure 4.14 : Breakdown voltage and specific ON-resistance for different drift thicknesses at LDrift =7.5µm,

TPwell =1.7µm, and LS =1.65µm

It is illustrated also from the figure that the specific ON-resistance is a strong function of the drift thickness. It is inversely proportional to TDrift.

The drift region thickness affects the distribution of the surface electric field as shown in figure 4.15. According to the RESURF principle, the surface electric field distribution is a function of the drift dose, so, the drift thickness should be optimized to get the best trade-off between the specific ON-resistance and surface electric field.

It is obvious that at LDrift =7.5µm, TPwell =1.7µm, LS =1.65µm, the optimum drift thickness TDrift,opt. =1.1µm. This value achieves the optimum RESURF’ing condition, above this value, the drift dose is increased and the maximum surface electric field is at the gate side (under


80

RESURF’ing condition), in the other extreme case, the maximum electric field is at the drain side (over RESURF’ing condition).

Figure 4.15 : Electric field distribution at the breakdown for various drift thicknesses at LDrift =7.5µm,

TPwell =1.7µm, and LS =1.65µm The potential distributions of the LDMOS at breakdown for three different drift thicknesses are shown in figure 4.16.

(a) (b)

(c)

Figure 4.16 : Potential distribution at the breakdown for (a) TDrift =0.6µm, (b) TDrift =2.1µm, and (c) TDrift = 1.1µm, at LDrift =7.5µm, TPwell =1.7µm, and LS =1.65µm

It is clear from the figure that the potential lines are crowded in the Pwell/N-buried

junction, far from the device surface. This minimizes the hot carrier effect and improves the


81

ruggedness of the device and consequently, increases the corresponding SOA. Obviously, the minimum and more flat surface electric field and the more uniform potential contours are achieved at TDrift =TDrift,opt.=1.1µm.

4.4.2.2 Impact of Pwell spacing length (LS)

The breakdown voltage and the specific ON-resistance as a function of the Pwell spacing length LS at LDrift =7.5µm, TPwell =1.7µm, and TDrift =1.1µm are shown in figure 4.17. The maximum breakdown voltage is achieved in case of absence of the Pwell spacing (i.e. LS = 0.0). In this case the avalanche breakdown occurs at the drain side due to punch-through phenomenon and the breakdown voltage is a function of the drift region thickness, the drain-junction curvature, and the Pwell/N-burried metallurgical junction properties.

80

90

100

110

120

130

140

0.00 0.70 1.65 2.65 3.70

LSpwell (µm)

BV (V

)

0.0E+00

4.0E-04

8.0E-04

1.2E-03

1.6E-03

2.0E-03

RON

,SP (

Ω.c

m2 )


Figure 4.17 : Breakdown voltage and specific ON-resistance for different Pwell spacing lengths at

LDrift =7.5µm, TPwell =1.7µm, and TDrift =1.1µm

For LS >0.0 µm, the breakdown voltage almost constant. The specific ON-resistance slightly decreases with increasing the spacing length; this is due to increasing the effective cross-section area of the drain current path.

The surface electric field distributions for LS =0.0 and LS =1.65µm are shown in figure 4.18. It is noticed that the electric field increases sharply at the drain side in case of absence of the Pwell spacing. In the case of LS =1.65µm, the effective drain junction curvature is increased, which has the same effect as using a buffer layer. This reduces the electric field at the drain as shown in the figure. The corresponding potential distributions for these two cases are illustrated in figure 4.19.

Figure 4.18 : Electric field distribution at the breakdown for various Pwell spacing lengths at LDrift=7.5µm,

TPwell =1.7µm, and TDrift =1.1µm


82

For LS =0.0µm the potential lines are crowded at the drain side, and this enhances the snap-back phenomenon, but for LS =1.65µm, the potential lines are nearly uniformly distributed through the drift length.

(a) (b)

Figure 4.19 : Potential distribution at the breakdown for (a) LS =0.0µm ,and (b) LS =1.65µm at LDrift=7.5µm, TPwell =1.7µm, and TDrift =1.1µm

4.4.2.3 Impact of Drift length (LDrift)

In figure 4.20, the breakdown voltage and specific ON-resistance are drawn as function of the drift length (LDrift) at LS =1.65µm, TPwell =1.7µm, and TDrift =1.1µm.

80

82

84

86

88

90

03.5 04.0 05.0 07.5 10.0 12.5

LDrif t (µm)

BV (V

)

0E+00

1E-03

2E-03

3E-03

4E-03

5E-03

6E-03RO

N,S

P (Ω

.cm

2 )Breakdown voltage


Figure 4.20 : Breakdown voltage and specific ON-resistance for different drift lengths at LS =1.65µm,

TPwell =1.7µm, and TDrift =1.1µm The breakdown voltage slightly decreases with increasing the drift length. This slight

change is due to the rearrange of the potential contours and the change of the Pwell/N-burried metallurgical junction properties with changing the device drift length. Also, it is clear from the figure that, increasing the drift length, increases the specific ON-resistance.

The surface electric field is decreased with increasing the drift length and it is inversely proportional to LDrift, as shown in figure 4.21. 4.4.2.4 Impact of Pwell thickness (Tpwell)

The breakdown voltage and the specific ON-resistance are shown in figure 4.22, as a function of the Pwell thickness (Tpwell).The breakdown voltage is decreased with decreasing the Pwell thickness due to the punch through breakdown. The slight decrease of the BV with increasing Tpwell is a function of the Pwell/N-burried metallurgical junction properties.


83

Figure 4.21 : Electric field distribution at the breakdown for different drift lengths at LS =1.65µm,

TPwell =1.7µm, and TDrift =1.1µm

75

77

79

81

83

85

87

89

0.70 1.25 1.70 2.30

TPwell (µm)

BV (V

)

0.0E+00

4.0E-04

8.0E-04

1.2E-03

1.6E-03

2.0E-03

RON

,SP (

Ω.c

m2 )


Figure 4.22 : Breakdown voltage and specific ON-resistance for different Pwell thicknesses at LS =1.65µm,

LDrift =7.5µm, and TDrift =1.1µm

The specific ON-resistance nearly constant with increasing Tpwell then it decreases for Tpwell >2.0µm, this is a cause of increasing the cross-section area of the drain current path. As Tpwell increases, the doping concentration in the vicinity of the N-epi / Pwell metallurgical junction is decreased. Consequently, the space charge region extends more in the Pwell. This causes the cross section area of the current path in the drift region to increase and the ON-resistance to decrease. From figure 4.13, the Pwell thickness affects the Pwell dose and hence the effective N-dose changes. Ndose,eff = ∫∫∫ −+

pwellburriedDrift Twell

Tburried

TDrift dyPdyNdyN (4.1)

So, the optimum RESURF dose is a function of the Pwell thickness. It is illustrated in figure 4.23, for Tpwell = 0.7µm, Ndose,eff > Ndose,opt and the maximum surface electric field is achieved at the gate side (under RESURF’ing condition). In contrary, for Tpwell = 2.3µm, Ndose,eff < Ndose,opt and the maximum surface electric field is achieved at the drain side (over RESURF’ing condition). For 0.7µm < Tpwell < 2.3µm, the maximum surface electric field is almost uniformly distributed (optimum RESURF’ing condition). 4.4.2.5 Impact of Pwell doping concentration (Pwell)

The breakdown voltages (BV) and the specific ON-resistances (RON,SP) of the nLDMOS structure for different Pwell doping concentrations Pwell are shown in figure 4.24.


84

Figure 4.23: Electric field distribution at the breakdown for various Pwell thicknesses at LS=1.65µm,

LDrift =7.5µm, and TDrift =1.1µm

75

85

95

105

115

125

135

145

4.0E+16

5.0E+16

6.0E+16

7.0E+16

8.0E+16

9.0E+16

1.3E+17

Pwell (cm-3)

BV (V

)

0.0E+00

5.0E-04

1.0E-03

1.5E-03

2.0E-03

2.5E-03

RON

,SP (

Ω.c

m2 )


Figure 4.24 : Breakdown voltage and specific ON-resistance for different Pwell doping concentrations at

LS = 1.65µm, LDrift =7.5µm, and TDrift =1.1µm The BV is decreased with increasing Pwell, as the breakdown voltage is inversely proportional to the doping concentration:

well

cs

PqE

BV2ε

= (4.2)

RON,SP is not independent on Pwell, as it depends mainly on the drift region properties. The

surface electric field distributions for various Pwell are shown in figure 4.25. As the Pwell doping decreases, the effective drift dose increases, causing a shift of the maximum surface electric field towards the gate side (under RESURF’ing condition). For Pwell = 1.25E17 cm-3, the electric field distribution is uniform over the surface of the device. This achieves the condition of optimum RESURF’ing.

Figure 4.25 : Electric field distribution at the breakdown for various Pwell doping concentrations at

LS=1.65µm, LDrift =7.5µm, and TDrift =1.1µm


85

4.5 Design of pLDMOS in 0.35µm based BiCMOS technology

In this section, high-voltage p-type lateral double diffused MOSFET is designed in 0.35µm BiCMOS process. Extra two masks are used for the body and the drift region formation with slightly added thermal budget and without resorting to high-tilt implants [81-83]. The pLDMOSFET is implemented using the same the epitaxial layer thickness of the optimized nLDMOSFET. 4.5.1 The pLDMOS structure

The schematic cross-section of the proposed pLDMOS is shown in figure 4.26. In this structure, the effective channel length LCH is defined by the difference in the lateral diffusions of the N-body and the P+-source regions.

LACC is the length of the accumulation region, and LGFP and LDFP are the lengths of the gate and drain field plates, respectively. LDrift and TDrift are the length and the thickness of the drift region, respectively.

Figure 4.26 : The schematic cross-section of the proposed pLDMOS

The technological process steps are shown in figure 4.27. The same standard 0.35 µm

BiCMOS technological steps are used, two extra masks are used. One for the P-Drift formation and the other for N-body (SNWELL) region using small thermal budget to not affect the characteristics of the CMOS parts. The modifications to the standard process are as follows [84-88]:

After the alignment of the buried layer, and the deposition of the two steps N- epitaxial layer, and the fabrication of the CMOS retrograde wells, then the PDrift is implanted with dose=8E12 cm-2 and implantation energy = 200 keV. A short drive-in is performed (10min) at 1150 oC. After the LOCOS, a high energy Nwell is implanted to form the body region of the pLDMOS transistor. A short drive-in time is taken (10min) at 1150 oC, to not alter the low voltage devices characteristics.

Using these process steps, the 2D cross-section of the device with the doping concentration distribution is shown in figure 4.28.

LDrift

Drain

SNWELL P+

Source

Gate

P+

P-substrate

LGFP LACC LCH

Bulk

LDFP

K

NBL

P-Drift N-Epi

Tepi


86

0.35µm BiCMOS technology Add-on steps for pLDMOS

Figure 4.27: The process steps of pLDMOS in 0.35µm BiCMOS technology

Figure 4.28: 2D cross-section of pLDMOS

4.5.2 Parametric analysis of pLDMOS

In this sub-section the impact of the proposed pLDMOS device/process parameters are studied by using 2D TCAD numerical simulation.

PDRIFT

SNWELL

LOCOS


SOURCE /DRAIN LDD

BPSG

METALIZATION

SUBSTRATE/BURIED

GATE FORMATION

RETROGRADE WELLS

OXIDE SPACERS

SOURCE / DRAIN

EPITAXY, ARSENIC


87

The drift region thickness TDrift, and length LDrift are optimized to reduce the surface

electric field by using the RESURF principle and to achieve the required characteristics. 4.5.2.1 Impact of Drift thickness (TDrift)

The impact of the drift thickness is illustrated in figure 4.29. It is obvious that the

breakdown voltage and the specific ON-resistance is a strong function of the drift thickness. The breakdown voltage obeys the RESURF principle and it has the maximum value at the drift thickness that gives the optimum drift dose.

-140

-130

-120

-110

-100

-90

-800.65 0.75 1.30 2.00 2.50

TDrif t (µm)

BV

(V)

5.0E-4

1.0E-3

1.5E-3

2.0E-3

2.5E-3

3.0E-3

RO

N,S

P (Ω

.cm

2 )


Figure 4.29 : Breakdown voltage and specific ON-resistance for different drift thicknesses at LDrift =7.5µm

The drift region thickness affects the distribution of the surface electric field as shown in

figure 4.30. According to the RESURF principle, the surface electric field distribution is a function of the drift dose, so, the drift thickness must be optimized to obtain the best trade-off among the breakdown voltage, the specific ON-resistance and the surface electric field.

It is obvious that at TDrift = 0.65µm, the optimum RESURF'ing condition is achieved, above this value, the drift dose is increased and the maximum surface electric field is at the gate side (under RESURF’ing condition).The potential distributions of the LDMOS at breakdown for two different drift thicknesses are shown in figure 4.31.

Figure 4.30 : Electric field distribution at the breakdown for various drift thicknesses at LDrift =7.5µm

The minimum and more flat surface electric field distribution is achieved at TDrift = TDrift,opt. = 0.65µm.


88

(a) (b)

Figure 4.31 : Potential distribution at the breakdown for (a) TDrift =0.65µm, and (b) TDrift =2.45µm at LDrift =7.5µm 4.5.2.2 Impact of Drift length (LDrift)

In figure 4.32, the breakdown voltage and specific ON-resistance are drawn as a function of the drift length (LDrift). The breakdown voltage is decreased with decreasing the drift length due to punch-through effect (see section 3.4.2). And the specific ON-resistance is increased with the increase in the drift length.

-130

-125

-120

-115

-110

-105

-100

-95

-90

3.5 4.0 5.0 7.510.0 12.5

LDrif t (µm)

BV

(V)

0E+001E-032E-033E-034E-035E-036E-037E-038E-039E-03

RO

N,S

P (Ω

.cm

2 )


Figure 4.32 : Breakdown voltage and specific ON-resistance for different drift lengths at TDrift =0.65µm

The surface electric field is inversely proportional to LDrift, as shown in figure 4.33.

Figure 4.33 : Electric field distribution at the breakdown for different drift lengths at TDrift =0.65µm


89

4.5.2.3 Impact of Pdrift doping concentration (PDrift) The breakdown voltages (BV) and the specific ON-resistances (RON,SP) of the pLDMOS structure for different drift doping concentrations PDrift are shown in figure 4.34.

-150

-140

-130

-120

-110

-100

3.0E+16

4.0E+16

6.0E+16

7.0E+16

7.5E+16

8.0E+16

8.5E+16

9.0E+16

1.3E+17

2.5E+17

PDrif t (cm-3)

BV

(V)

0.0E+00

5.0E-03

1.0E-02

1.5E-02

2.0E-02

2.5E-02

3.0E-02

RO

N,S

P (Ω

.cm

2 )


Figure 4.34 : Breakdown voltage and specific ON-resistance for different drift doping concentrations at

TDrift = 1.1µm, and LDrift=7.5µm

The breakdown voltage increases with increasing the drift doping concentration until PDrift = 6.0E+16 cm-3, then it rest constant until PDrift = 9.0E+16 cm-3. The optimum RESURF’ing condition that gives the maximum breakdown voltage is achieved for 6.0E+16 cm-3 > PDrift > 6.0E+16 cm-3. It is clear also from the figure that, the specific ON-resistances (RON,SP) decreases with increasing the doping concentration. 4.6 The ON- state characteristics of nLDMOS

In this section, the static and dynamic characteristics of the proposed nLDMOS are stated and analyzed. 4.6.1 The static characteristics

From the previous section, the optimum geometrical parameters of nLDMOS are listed in table 4.1:

Table 4.1: The optimum geometrical parameters of nLDMOS

LCH = 1.00µm LDrift = 6.00µm LACC = 0.40µm TDrift = 1.80µm LGFP = 1.50µm Tpwell = 2.15µm LDFP = 0.50µm LS = 1.65µm

By using these parameters, the breakdown voltage of the nLDMOS and the impact

ionization distribution are shown in figure 4.35. It is obvious that BV ≈ 60V and the avalanche breakdown is occurred at the Pwell / N-burried junction far from the surface. In figures 4.36, the electric field, and potential lines distributions are illustrated at the breakdown condition.

The potential lines are uniformly distributed over the drift region with surface electric field

smaller than 3E5 V/cm.


90

(a) (b)

Figure 4.35 : (a) Breakdown voltage characteristic, and (b) Impact ionization distribution at BV of nLDMOS

(a) (b)

Figure 4.36 : (a) Electric field, and (b) potential distributions, of nLDMOS

Before proceeding into understanding the ON-state behaviour of the nLDMOS, the intrinsic-drain VK is examined first. It is of great interest for the characterization and modeling purposes as it will be shown in the following. The intrinsic-drain VK : To explain the interest in K-point, the architecture of the device has to be taken into account. Furthermore, it was demonstrated that the intrinsic MOS device behaves like a low voltage MOSFET, the potential of the K-point remaining low even when VDS and VGS are increased as shown in figure 4.37.


VGS Step = 0.3 V


91

The maximum value of VK is equal to 4.3V at VDS = 60V and VGS =3.3V. Obviously, this voltage in conjunction with the one applied on the gate gives the operation regime of the intrinsic MOSFET. From the figure, the K-point voltage rises with VDS, as an increase in the drain voltage leads to a raise of the voltage drop on each part of the device.

By using the K-point potential, it is possible to obtain the output characteristics of the intrinsic MOSFET device (see figure 4.38).


The IDS-VDS characteristics are shown in figure 4.39. The characteristics have a parabolic

dependence of VGS and with maximum drain current of 0.42 mA/µm at VGS =3.3V. The transfer characteristic is shown in figure 4.40, for drain voltage of 0.5V. The threshold voltage for the proposed device is about 0.6V, which is matched with the threshold voltage of the low voltage nMOSFET.

Figure 4.39 : ID -VDS output characteristics of nLDMOS for the optimum design case

Figure 4.40 : The transfer characteristic of nLDMOS

Step = 0.3 V VGS


92

4.6.2 Thermal characteristics

The drain current and drain temperature variation at VGS =3V as a function of VDS are shown in figure 4.41a. The reduction of ID with increasing VDS, is illustrated in the figure. This reduction is due to the decrease of the carriers’ motilities with the increase in temperature, so, the device exhibits negative temperature coefficient. At VDS = 60V, the drain temperature is equal to 360 K.

The temperature distribution at VGS =3 V and VDS = 60 V, is shown in figure 4.41b. The

maximum values appear in the drift region in the high electric field zone.

(a) (b)

Figure 4.41 : (a) Drain current and drain temperature variation at VGS =3 V, and (b) The temperature distribution at VGS =3 V and VDS = 60 V

The thermal ID -VDS characteristics are shown in figure 4.42.

Figure 4.42 : Thermal ID -VDS characteristics of nLDMOS

4.6.3 AC effects in nLDMOS

This section is focused on the variations of the capacitances and the associated charges function of the gate and drain voltages. Physical effects are analyzed and discussed using 2D numerical simulations, which provide useful insights.

Figure 4.43 shows the variation of CGS and CGD as a function of VGS. The dependence of

CGS is similar to the one obtained for a low voltage MOS transistor. It can be easily seen that the transition from the depletion to inversion occurs around VGS =0.6V, which is the same


93

value of VTH. Unlike the case of a classical MOS transistor, these devices present totally different variations for the CGD capacitance [89].

Figure 4.43: CGS and CDS dependence on VGS

Moreover, CGD capacitance is more important than the rest of other capacitances below the threshold see figure 4.43, due to the charge accumulation on the drift side as it was explained before (see section 3.6.3) . 4.7 The ON- state characteristics of pLDMOS

In this section, the static and dynamic characteristics of the proposed pLDMOS are stated

and analyzed.

4.7.1 The static characteristics The optimum geometrical parameters of pLDMOS are listed in table 4.2:

Table 4.2: The optimum geometrical parameters of pLDMOS

LCH = 0.90µm LDFP = 0.50µm LACC = 1.10µm LDrift = 6.00µm LGFP = 0.80µm TDrift = 0.92µm

Using these parameters, the breakdown voltage of the nLDMOS and the impact ionization distribution are shown in figure 4.44. It is obvious that the BV ≈ -170V and the breakdown is occurred at the drain side due punch-through breadown. In figure 4.45, the electric field, and potential lines distributions are illustrated at the breakdown condition.

(a) (b)

Figure 4.44 : (a) Breakdown voltage characteristic, and (b) Impact ionization distribution at BV of pLDMOS

CGS (F/µm)

CGD (F/µm)


94

The potential lines are uniformly distributed over the drift region with average surface electric field about 5E5 V/cm and they are crowded under the drain.

(a) (b)

Figure 4.45 : (a) Electric field, and (b) Potential lines distributions of pLDMOS

From figure 4.46, the absolute value of the K-point voltage KV rises with DSV , as any increase in the drain voltage leads to a raise of the voltage drop on each part of the device. The potential of the K-point remaining low even when DSV and GSV are increased as shown in figure 4.46. The value of VK is equal to -2.8V at VDS = -100V and VGS = -3.3V. Obviously, this voltage in conjunction with the one applied on the gate gives the operation regime of the intrinsic MOSFET.


The output characteristics of the intrinsic MOSFET device are illustrated in figure 4.47.


VGS

Step = -0.3 V

Step = -0.3 V

VGS


95

The IDS -VDS characteristics are shown in figure 4.48. The characteristics have a parabolic dependence on VGS and with minimum drain current of -0.135 mA/µm at VGS = -3.3V. The transfer characteristic is shown in figure 4.49, for drain voltage of -0.5V. The threshold voltage for the proposed device is about -0.55V, which is near the value of the threshold voltage of the low voltage pMOSFET.

Figure 4.48 : ID -VDS output characteristics of pLDMOS for the optimum design case

Figure 4.49 : The transfer characteristics of pLDMOS

4.7.2 Thermal characteristics

The drain current and drain temperature variation at VGS = -3 V, as a function of VDS are shown in figure 4.50a.

Figure 4.50 : (a) Drain current and drain temperature variation at VGS =-3 V, and (b) The temperature distribution at VGS =-3 V and VDS = -100 V


96

The reduction of ID with increasing VDS is illustrated in the figure. This reduction is due to the decrease in the carriers' mobilities with the increase temperature, so, the device exhibits negative temperature coefficient. At VDS = -100V, the temperature at the drain is equal to 360 K.

The temperature distribution at VGS = -3 V and VDS = -100 V, is shown in figure 4.50b. The maximum values appear in the drift region in the high electric field zone. The thermal ID -VDS characteristics are shown in figure 4.51.

Figure 4.51 : Thermal ID -VDS characteristics of pLDMOS

4.7.3 AC effects in pLDMOS

Our goal in this section is the understanding of the variations of the capacitances of the pLDMOS. Physical effects are analyzed and discussed using 2D numerical simulations, which provide useful insights.

Figure 4.52, shows the variation of CGS as a function of VGS. This dependence is similar to

the one obtained for a low voltage MOS transistor. It can be easily seen the transition from the depletion to inversion occurs around VGS = -0.6V, which is the same value of VTH. Unlike the case of a classical MOS transistor, these devices present totally different variations for the CGD capacitance. Moreover, CGD capacitance is more important than the rest of other capacitances below the threshold see figure 4.52, due to the charge accumulation on the drift side as it was explained before .

Figure 4.52: CGS and CDS dependence on VGS

CGS (F/µm)

CGD (F/µm)


97

4.8 Conclusion

New devices structures with recently developed novel device concepts are developed. The devices of interest are implemented in 0.35µm BiCMOS technology, which is STMicroelectronics technology-like. The developed LDMOSFETS are developed by slight modifications of the base 0.35µm BiCMOS technology. Extra two masks are used for the body and the drift regions formation with slightly added thermal budget and without resorting to high-tilt implants. The breakdown voltage of the proposed nLDMOS does not depend on the epitaxial layer thickness as in the conventional RESURF LDMOS, so the proposed device is suitable for integration with low voltage CMOS with shallow epitaxial layers. A pLDMOS is designed in the same optimized epitaxial layer of the nLDMOS.

These HV devices are simulated and optimized with advanced TCAD tools to investigate the physical phenomena and electrical characteristics. We have utilized commercial device simulators ISE and SENTAURUS-TCAD. The simulators provide facility for performing simulation in both 2D and 3D. The software gives a convenient framework to design, organize, and automatically run complete TCAD simulation projects. The specific ON-resistance (RON,SP), and the OFF-state breakdown voltage (BV) of the proposed devices are 1.5 mΩ.cm2 and 62V, respectively for the nLDMOS and 3.0 mΩ.cm2 and 160V, respectively for the pLDMOS. So, the devices can typically be operated around 42V supply voltage, which is suitable for the future automotive applications. The TCAD numerical simulations are used to obtain the DC and AC characteristics of the proposed devices. The maximum drain current obtained in the simulation at absolute gate voltage of 3.3V is 0.42 mA/µm for nLDMOS and 0.135 mA/µm for pLDMOS.


98

CHAPTER 5

Modeling of LDMOS

Chapter 5: Modeling of LDMOS

100


101

5.1 Introduction

For the development of power semiconductor device models, several effects have to be considered with high priority since they dominate the static and dynamic device characteristics. These effects are not described correctly by standard device models (or they are not included at all) because their influence on low-power devices is less important or neglectable [90-94]. So, better investigation of the physics of the HV devices and clear understanding of the special effects (see chapter 3) is needed.

The modeling of the lateral structures came into play as these devices were integrated in standard technologies. Remarkable progress in the modeling field conducted to geometrical approximations of the drift zone (regional approach) [95], which seems to be the most promising approach.

In the first part of this chapter an approach for physically modeling the intrinsic MOS part and the drift region is presented. The effects of velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel are considered. The device charges are calculated and integrated to provide analytical expressions of the currents.

The second part of the chapter presents the implementation of the analytical model using MATLAB and MAPLE programs. The electrical approximations that have to be taken into account to build the DC model are also explained. With the help of the proposed analytical model, a Spice model is developed. The model parameters are extracted using the ICCAP and ISExtract extraction tools. The Spice model is compared to the simulation results provided by ISE-TCAD tools [96-99].

In the last part of the chapter, an interface circuit, to convert 0/3.3 V to 0/42 V, suitable for

the future automotive applications is proposed. 5.2 Analytical modeling of LDMOS

Some critical points are encountered in the attempt to analytical model a HV LDMOSFET. This is mainly related to the fact that a typical HV LDMOSFET structure is made of intrinsic MOS part and the extension of the drain, the architecture of which dictates the high voltage capabilities (see figures 5.1 and 5.2).

The drift region of the device is divided into two different parts. The first zone – a depleted area in which the carriers are injected by the intrinsic MOSFET – and the second zone – the non-depleted area at the drain side [48, 100-103]. 5.2.1 Channel region model The model is derived based on the following basic assumptions:

1. The laterally non-uniform channel (P-body) doping density can be approximated as a simple exponential function,

2. The gradual channel approximation (GCA) is valid, 3. The surface potential of graded-channel varies linearly with position, and 4. A simple relationship between the inversion charge density Qn and the local

potential )(xsψ .


102

The non-uniform doping density along the channel can be approximated as an exponential

function )/(exp)( 0 chAA LxNxN η−= , where NA0 is the concentration near the source and η is the doping gradient, chosen to be )/(ln 0 DA NN , so that NA (Lch) = ND [102, 104-110]. We use a piecewise-continuous electron velocity model [111, 112].

satsatxneff

xneff vvvE

Ev ≤

+= ,

)2/(1 µµ

= vsat, otherwise

(5.1)

Where Ex is the longitudinal electric field, vsat (≈ 107 cm/s) is the saturated drift velocity,

and)(1

0

THGS

nneff VV −+

=θ

µµ , where μn0 is the low field mobility,θ is the fitting parameter that

defines the transverse-field dependence. 5.2.1.1 Threshold voltage

The threshold-voltage is defined as the gate-voltage at which the semiconductor surface is

at the onset of strong inversion. Hence the concentration near the source is higher than the concentration near the drain, so the semiconductor surface near the drain is inverted before that near the source. So, to obtain an expression of VTH, we use the bulk doping concentration at the source side NA0.

Figure 5.1: The schematic cross-section of the RESURF LDMOS

Figure 5.2: Drift region functional partition [48]

Lacc

VGS-VFBdr VK VK1

Intrinsic

MOS

Zone 1 Zone 2

Ldep

VK (ΨSL) VD

VG VG

VK1 (ΨD) Analytical

Drift Resistance

VB I

VB II


103

,4

2 0

ox

FAsFFBTH C

NqVV

φεφ ++=

(5.2)

Where Fφ is the Fermi-potential ( Fφ =i

A

nN

qKT 0ln )

5.2.1.2 Channel current

The quasi-static channel current is described by nch WvQI −= (W is the device width and

Qn is the inversion charge density) from source to drain, and by using doxn CC

dvdQ

+= , the

Channel current in the linear region is [108,114-117]:

KKdoxFdTGSox

Kchsatneffch

neffch

VVCCCVVC

VLvLW

I

].).(5.0)..().([

.])2(1[

00 +−+−

+−=

φη

µµ

(5.3)

Where VK is the intrinsic drain voltage. oxoxox tC ε= is the capacitance of the of the oxide

layer with permittivity oxε and thickness oxt . dC is the average depletion capacitance which assumed to be invariant along the channel.

)2

1(0k

Fdd V

CCηφ

−= , where,

)4( 00 FAsd NqC φε−= ,

(5.4)

In saturation, the current is saturated due to the electron velocity saturation at the source

end of the channel. In general, however velocity saturation at the source and the drain side both can occur depending on the channel region doping gradient and the channel length.

If the channel is very long or the doping gradient is very small, the electron velocity saturates at the drain end of the channel. If the gradient is very high, the inverted electron concentration is much higher at the drain end than the source end and the velocity will saturate there. Generally, to get an expression for the saturation current, the following differential equation is used:

0=∂∂

= KsatK VVK

ch

VI

(5.5)

Where VKsat is the value of the intrinsic drain voltage at the onset of current saturation.

0

0 )..().(

dox

FdTGSoxKsat CC

CVVCV

++−

=φη

(5.6)

Substituting equation (5.6) into equation (5.3), one get;


104

Yes No

Yes No

Zone I Rdep

Zone II Rdr

JFET pinch-off

Zone I It=Ib+Iacc

Zone II Rdr

Zone II It=Ib

Zone III Rdr

Nonaccumulated case

Accumulated case

Zone I It=Ib+Iacc

)()]..().(.[5.0

.])2(1[2

0

20

dox

FdTGSox

Ksatchsatneffch

neffchsat

CCCVVC

VLvLW

I

++−

+−=

φη

µµ

(5.7)

This saturation current is general and independent on the location at which v = vsat (source side or K-point). 5.3 Drift region model

The flow chart of the drift region modeling methodology, which represents the various cases, is shown in figure 5.3:

Figure 5.3: Modeling flow chart

The model is splitted into two cases:

Case 1: The accumulated case, VG -VFBdr > VK . Case 2: The non-accumulated case, VG -VFBdr < VK .

Where VFBdr is the flat band voltage, VG is the gate voltage, VK is the surface potential of the intrinsic MOS drain, and (VG -VFBdr) is the limit of the accumulation layer. 5.3.1 The accumulated case, VG -VFBdr > VK 5.3.1.1 Case of VGS-VFBdr < VK1 Zone I : The accumulation charge can be computed by using simple capacitance equivalence [48, 104, 107, 117]. Qacc =-Cox .(VGS -VFBdr - ψs) (5.8) Where Cox is the oxide capacitance, sψ is the surface potential. The integration of the accumulation charge with the position leads to the current component given by the accumulation layer.

VGS-VFBdr >VK

VGS-VFBdr >VK1


105

.vWQI accacc −= (5.9)

Where v is the carrier velocity, defined as in equation (5.1).

.)2/(1 satxaneff

xaneffaccacc vE

EWQI

µµ

+−= (5.10)

Wheredx

dE s

xψ

= , and µaneff is the effective electron mobility in the accumulation region.

sVV

V sFBdrG

satacc

KFBdrGaneff

oxaneffaccacc dVV

vLVVV

CWLI FBdrG

Kψψ

µ

µ∫

− −−−−

+= )(

.2)(1[2

..

(5.11)

][]

.2)(1[.2

.KFBdrG

satacc

KFBdrGaneffacc

oxaneffacc VVV

vLVVVL

CWI −−

−−+

=⇒µ

µ

(5.12)

The second type of charge present in zoneI is the drift charge. The drift charge concentration is approximated constant for the drift zone. Qb=-q.Ndr.ypath (5.13) Where ypath is the depth of the current path. As for the accumulation current, the integration of the drift charge provides the expression for the drift current.

.vWQI bb −= (5.14) Where v is the carrier velocity, defined in equation (5.1).

sVV

V path

satacc

KFBdrGaneff

aneffaccb dy

vLVVV

qWLI FBdrG

Kψ

µ

µ∫

−

−−+

=]

.2)(1[2

. (5.15)

][]

.2)(1[2

tan.KFBdrG

satacc

KFBdrGaneff

draneffb VVV

vLVVV

NqWI −−

−−+

=⇒µ

αµ

(5.16)

Where tan α is the slope of the current path at the K-point.

bacct III += (5.17) Where It is the total current through the drift region. Zone II: Zone II represented by a current It=Ib


106

][]

.2)(1[)(

tan....1 FBdrGK

satacc

KFBdrGaccdep

accdrb VVV

vLVVVLd

LNqWI −−−−

+−=

µ

αµ

(5.18)

Zone III: Zone III represented by a drift resistance Rdr as shown in the following. The drain current penetrates in the semiconductor to a depth referred here as Zdr. The drain current equation can be written in the drift zone as follows [118]:

drdr WvQI −= (5.19) Where Qdr is the drift region charge density, which is uniform Qdr = qnZdr, ndr=Ndr, where Ndr is the drift region doping concentration, and v is the carrier velocity which is defined in equation (5.1).

)2/(1 satxn

xndrdrdr vE

EZWqNIµ

µ+

= ,where dx

xdVEx)(

= (5.20)

By integrating the above current relation over the drift region, an expression for the current

in the drift region is obtained as follows:

dxxdV

vIZWqNI n

sat

drdrdrdr

)(]2

[ µ−=

∫∫Ψ

−=⇒D

Ddr

V

nsat

drdrdr

Ldr xdV

vIZWqNdxI )(]

2[ µ

)(]2

)([ DDndrdr

sat

DDndrdr VZWqN

vVLI Ψ−=

Ψ−+⇒ µ

µ

).(]

.2)(

1[DD

drsat

DDndr

ndrdrdr V

LvVL

ZWqNI Ψ−Ψ−

+=⇒

µµ

(5.21)

As, ndrdr

drsat

DDndr

dr

DDdr ZWqN

LvVL

IVR

µ

µ ].2

)(1[)(

Ψ−+

=Ψ−

=

satdrdr

DD

drdrn

drdr vZWqN

VZWNq

LR2

)( Ψ−+=⇒

µ (5.22)

Where, Ldr=L-ddep, and, Zdr=TDrift-Zdep

We notice that the expression of the drift resistance consists of two terms, the first one

represents the drift resistance at low voltage conditions Rd0 , and the second term represents the drift region resistance due to high voltage and current conditions Rdvsat. Rdr=Rd0+Rdvsat


107

5.3.1.2 Case of VGS-VFBdr > VK1 Zone I:

satdep

KKaneffdep

KFBdrGKFBdrGoxaneffacc

vdVVd

VVVVVVCWI

.2)(1[.2

])()[(.

1

221

−+

−−−−−−=

µ

µ

(5.23)

And,

][]

.2)(1[2

tan...1

1KK

satdep

KK

accdrb VV

vdVV

LNqWI −−

+=

µ

αµ

(5.24)

Zone II : Zone II represented by a drift resistance Rdr. 5.3.2 The non-accumulated case, VG -VFBdr < VK

This area is modeled as a depletion resistance, which is associated with the so called JFET pinch-off. The starting point is Poisson's equation.

sdxdE

ερ

= (5.25)

Where E is the electric field and ρ is the charge density.

sdxsd

ερψ

=−2

2, ρ=qNdr (5.26)

sψ is the potential function of position, which depends only on the lateral position. After the

double integration of equation (5.26) between the limits ΨSL and ΨD the following expression is obtained for the potential,

SLdeps

dr

dep

SLD

s

drs Ψxd

εqN

dΨΨx

εqN(x)ψ +

+

−+=

222 (5.27)

To link the potential variation with the position on the resistance of the depleted area, the

simple formulation for the mobile charge can be used in conjunction with the conductance of a depleted zone.

=

kTqnxn s

oψexp)( (5.28)


108

WTnqde

Ro

sd kT

q

dep

dep

s

µψ

ψ

∫= 0 (5.29)

Zone II : Zone II represented by a drift resistance Rdr. 5.3.3 Dynamic behaviour To the previously determined static model, we have added capacitive elements accounting for the dynamic behaviour of the transistor. • The drain-source capacitance can be considered as a junction transition capacitance:

m

j

DS

jds

VV

CC

−

=

1

0 (5.30)

Cj0 is the zero-bias capacitance, Vj is the diffusion voltage of the junction and m is the junction graduality factor. • The gate-source capacitance Cgs derives from the contributions of the poly gate towards the n+ source diffusion and the source metallization. This capacitance does not practically depend on the bias conditions.

ox

osnoxgs t

AC +≅ε

(5.31)

Where osnA + is the area of overlap of the gate electrode over n+ source.

• The device input capacitance is mainly dominated by the gate-drain capacitance Cgk1. In the linear region of operation, an accumulation layer exists under the oxide in the drift region. This results in Cgk1 equal to the oxide capacitance :

ox

oaccnoxgk t

AC +≅ε

1 (5.32)

Where oaccnA + is the area of overlap of the gate electrode over n+ accumulation layer.

As the drain bias increases and the device enters saturation, a depletion layer is formed under the oxide in the drift region resulting in Cgk1 equal to a depletion capacitance in series with an oxide capacitance, similar to a MOS capacitor:

ox

accox

ox

oaccnoxox t

WLtAC εε

=≅ +


109

accGK

drsidep WL

VqNC

21

1

221

≅

ε

oxdepgk CCC111

1+= (5.33)

oxdrsi

GK

accgk CqNV

WLC1

221 2

1

1

1+

=

ε

drsi

GKox

accoxgK

qNVC

WLCC

ε22

1 11

+

= (5.34)

5.4 The proposed subcircuit model

Based on the analytical model discussions in the previous section and the flow chart of figure 5.3, a suggested subcircuit model of the proposed nLDMOS is shown in figure 5.4, [119-123]. Spice elementary elements (i.e. resistor, capacitors, and dependent current sources) are used in the implementation of the model. A two way switch is used to switch between the accumulated and the non-accumulated cases of the model. This model can be implemented using the analog behavioural blocks (ABM) available in Spice, but exhibits conversion problems.

Wscr

Idep.

IntrinsicMOSG

S

K

Rdr VDD

It

K1

1

2

Cgk

Cgs

Figure 5.4: The proposed subcircuit LDMOS model

5.5 Simulation of the analytical model

As a preparation for Spice implementation, the analytical model was simulated using Matlab and Maple programs. Before proceeding, the physical key constants and relations are stated below: o εo =8.84×10-12 F/cm o εox =3.9 o εs =11.7 o q =1.602176487×10-19 C o K =1.38×10-23 J/K o Temp = 300 K


110

VK (V)

I D (A

/µm

)

o ni =1.482×1010 cm-3 o VFbinv = -0.95 V o VFBdr = -0.2 V o vsat = 4.5×107 cm/sec o Vther = 0.025875 V o Lacc = 0.4×10-4 cm o Lch =1.0×10-4 cm o Cox = 4.5435×10-7 F/cm2 o Ndr = 9.5×1015 cm-3 o T = 1.8×10-4 cm o W = 1.0×10-4 cm o NA0 = 9.5×1017 cm-3 o ФF = 0.46513 V o Ldr = 6.0×10-4 cm o Pwell = 1.5×1017 cm-3 o Tpwell = 2.15×10-4 cm o Ls =1.65×10-4 cm o µdrift =1025 cm2/V.sec

By using the above key constants the threshold voltage of the device is equal to 0.576V. This value is the same as the extracted Spice one as will be explained latter in this chapter. The capacitances Cgs and Cgk1 are equal to 6.3E-15 F and 1.8E-15 F, which are approximately the same as those obtained from TCAD simulation (see figure 4.43). 5.5.1 The intrinsic MOS characteristics

The ID -VK characteristics of the intrinsic MOSFET are shown in figure 5.5. The comparison of these characteristics with results of the TCAD simulations is illustrated in figure 5.6. It is clear that, the value of VK at ID = 0 is about 0.4V. This value is the built-in voltage of the P-body/N-drift junction, which must be taken into consideration when comparing the TCAD results with the model.

0 0.5 1 1.5 2 2.5 3 3.5 40

0.5

1

1.5

2

2.5

3

3.5

4

4.5x 10

-4

Figure 5.5 : Analytical output characteristics of the intrinsic MOSFET

It is observed that, the model approximately follows the behaviour of the TCAD simulated device, as VGS is increased.


111

I D (A

/µm

)

0.0E+00

5.0E-051.0E-04

1.5E-04

2.0E-042.5E-04

3.0E-04

3.5E-044.0E-04

4.5E-04

0.0 1.0 2.0 3.0 4.0

The deviation of the analytical model from the TCAD simulation is due to the injection of carries in the drift region and the accumulation layer formation under the gate oxide. These phenomena are not taken into account in the analytical model, as their addition complicates the model.

Figure 5.6 : Comparison of the model simulation (Red dashed curves), and the TCAD results (Black solid curves)

5.5.2 The accumulated resistance (Racc) of the LDMOSFET

( ) satoxKFBdrGaneffox

accacc vCWVVVCW

LR 12

+−−

=µ

(5.35)

The accumulation resistance is a result of the accumulation of the majority carriers

(electrons) under the thin gate oxide in the drift region, when VGS - VFBdr > VK. This resistance is important in obtaining an overall equivalent resistance for the drift region. Equation 5.35 is plotted as a function of VGS and VK in figure 5.7.

Figure 5.7: The accumulated resistance as a function of VGS and VK

It is observed from figure 5.7, that Racc is proportional to VK and inversely proportional to VGS.

VK (V)


112

5.5.3 The total drift resistance (Rdrift) of the LDMOSFET

We can represent the total drift region which extended from the intrinsic drain to the drain terminal in the ON-state, by a resistance Rdrift.

( )Gaccsatdrdr

KD

drdrn

drdrift V

vZWqNVV

ZWNqL

R θµ

+

−+= 1

2)( (5.36)

This resistance is plotted at VGS = 2V, as a function of VDS and VK in figure 5.8. The

denominator ( )Gacc Vθ+1 is added to the expression of Rdr to take the effect of accumulation layer into consideration. As VGS increases, the accumulation resistance decreases and hence the total drift resistance decreases.

Figure 5.8: The total drift resistance as a function of VDS and VK at VGS =2V

Hence, the drift resistance is the dominant part of the device ON-resistance. So, RON can be

estimated from figure 5.8, which is the value of Rdrift at VDS → 0, (RON ≈ 21 kΩ at VGS =2V, see device characteristics in figure 4.39). With the help of Rdrift, the analytical model of the LDMOS can be represented simply by an intrinsic MOS connected with a resistance, as shown in figure 5.9.

Intrinsic MOS

G

S

KRDrift VDD

Figure 5.9: Approximate analytical static model of LDMOS


113

5.6 Implementation of the model into Spice

Although recent simulators, such as SABER, may offer much more capabilities to implement mathematical models than the well-known Spice and Spice-related circuit simulators, these programs are very expensive and are available only for workstations. On the other hand, Spice is a good value circuit simulator running on personal computers and is nowadays widely used by circuit designers in power electronics [124,125].

In the previous chapter, nLDMOS and pLDMOS transistors are designed and implemented

in 0.35μm BiCMOS technology. The device/process key parameters of the transistors are optimized to achieve the required electrical characteristics, which are minimum RON,SP and BV > 42 V, to be used in automotive applications [116].

The analytical model can be represented approximately by a low voltage transistor and a

voltage controlled resistor, as shown in figure 5.9. The voltage dependent resistor can be implemented by using ABM building blocks available in spice [126-129]. But, the integration of these blocks with the Spice model of the low voltage MOSFET exhibits conversion problems.

We use level 3 MOS Spice model to implement the low voltage MOSFETs and the

intrinsic MOS part of LDMOS. ICCAP and ISExtract tools are used to extract the Spice model parameters by using the results of the TCAD simulations as the input to these tools (as measured data) [130-138].

The level 3 MOS Spice model used is a simple one with small number of parameters compared to BSIM models. Its parameters are easy to extract by using the extraction tools. The ID -VDS characteristics and ID -VGS characteristics are used to extract the model parameters, with the source tied to the bulk. 5.6.1 Spice model parameters of the low voltage MOSFETs

The Spice model parameters of the low voltage MOSFETs implemented in 0.35μm

BiCMOS technology are extracted and represented in figure 5.10.

5.6.2 Spice model parameters of the high voltage LMOSFETs

The Spice models are used to obtain the electrical characteristics of a symmetrical low voltage MOSFETs. But they are not suitable for unsymmetrical high voltage MOS transistors like LDMOS. So, to use these models for LDMOS, a simple methodology is suggested. First, the Spice parameters of the intrinsic MOS part of the transistor are extracted, and then the Spice parameter RD is modified to take the effect of the drift resistance into consideration. The extracted model parameters are shown in figure 5.11, [133,138-144].

The widths of the transistors can be modified to achieve symmetrical characteristics of

both p-type MOSFETs and n-type MOSFETs. The electrical characteristics of the circuit are obtained by using ORCAD simulator.

The comparison of the TCAD simulations and the Spice model simulation is shown in

figures 5.12 and 5.13 for both nLDMOS and pLDMOS. The accuracy at room temperature is less than 5% for the whole voltage domain.


114

Figure 5.10: The Spice model parameters of low voltage MOSFETs

Figure 5.11: The Spice model parameters of LDMOSFETs

It is required now to design an interface circuit to convert the low logic level 0/3.3 V to

high voltage level 0/42 V, suitable for the future automotive applications.

.model nMOS NMOS (LEVEL= 3 + UO = 5.829856e+02

+ VTO= 5.362076e-01 + TOX= 7.600n

+ NSUB= 1.5E+17 + VMAX= 2.854458e+05

+ CJ= 5.0e-04 + MJ = 0.5

+ CJSW = 5.0e-10 + MJSW= 0.33

+ CGDO= 6.0E-09 + CGSO = 6.0E-09 + CGBO = 6.0E-09

+ PB = 1 + FC = 0.5

+ XJ= 200n + DELTA= 2.255185e-02

+ THETA= 0.08 + ETA = 0

+ KAPPA= 0.6)

.model pMOS PMOS (LEVEL 3 + UO = 95.7

+ VTO = -5.593849e-01 + TOX = 7.600n

+ NSUB = 1.00E+17 + VMAX = 3.067345e+04

+ CJ = 100.6u + MJ = 500.5m

+ CJSW = 50.30p + MJSW = 500.5m + CGDO = 8.0E-09 + CGSO = 8.0E-09 + CGBO = 8.0E-09

+ PB = 982.3m + FC = 500.0m + XJ = 200.00n

+ DELTA = 3.291260e-02 + THETA = 36.9m

+ ETA = 100.0m + KAPPA = 0.01)

.model nLDMOS NMOS (level 3 + RD =21.0k + UO =432.0 + VTO = 532.2m + TOX =7.600n + NSUB = 9.50E+17 + VMAX=4.50E+05 +CGDO = 6.00E-09 +CGSO = 1.50E-09 +CGBO = 1.50E-09 + CJ= 5.0e-04 + MJ =500.0m + MJSW = 330.0m + PB = 800.0m + FC =500.0m + XJ = 200.00n + THETA = 0.08 + KAPPA = 0.005)

.model pLDMOS PMOS (LEVEL 3 +UO = 140.0 +VTO =-459.4m +TOX = 7.600n +VMAX = 75.0k +RD = 45.0k +XJ =200n +NSUB =1.2e18 +THETA =0.03 +KAPPA =0.5 +CGDO = 8.0E-09 +CGSO = 2.0E-09 +CGBO = 2.0E-09 +CJ = 7.285722E-4 +PB = 0.96443 +MJ = 0.5 + CJSW = 2.955161E-10 +MJSW = 0.3184873)

.model nMOS NMOS (LEVEL= 3 + UO = 5.829856e+02 + VTO= 5.362076e-01 + TOX= 7.600n + NSUB= 1.5E+17 + VMAX= 2.854458e+05 + CJ= 5.0e-04 + MJ = 0.5 + CJSW = 5.0e-10 + MJSW= 0.33 + CGDO= 6.0E-09 + CGSO = 6.0E-09 + CGBO = 6.0E-09 + PB = 1 + FC = 0.5 + XJ= 200n + DELTA= 2.255185e-02 + THETA= 0.08 + ETA = 0 + KAPPA= 0.6)

.model pMOS PMOS (LEVEL 3 + UO = 95.7 + VTO = -5.593849e-01 + TOX = 7.600n + NSUB = 1.00E+17 + VMAX = 3.067345e+04 + CJ = 100.6u + MJ = 500.5m + CJSW = 50.30p + MJSW = 500.5m + CGDO = 8.0E-09 + CGSO = 8.0E-09 + CGBO = 8.0E-09 + PB = 982.3m + FC = 500.0m + XJ = 200.00n + DELTA = 3.291260e-02 + THETA = 36.9m + ETA = 100.0m + KAPPA = 0.01)


115

0.0E+00

5.0E-05

1.0E-04

1.5E-04

2.0E-04

2.5E-04

3.0E-04

3.5E-04

4.0E-04

4.5E-04

0 10 20 30 40 50 60

I D (A

/µm

)

VDS (V)

I D (A

/µm

)

Figure 5.12: Comparison of the TCAD simulation (Black solid curves) and the Spice model simulation (Red dashed curves) for nLDMOS

-1.6E-04

-1.4E-04

-1.2E-04

-1.0E-04

-8.0E-05

-6.0E-05

-4.0E-05

-2.0E-05

0.0E+00-100 -80 -60 -40 -20 0

Figure 5.13: Comparison of the TCAD simulation (Black solid curves) and the Spice model simulation (Red

dashed curves) for pLDMOS

5.6.3 The interface circuit

The aim of the interface circuit is the conversion of 0/3.3 V low logic voltage to 0/42 V high level voltage. We must check that the voltage across each transistor must be smaller than its breakdown voltage.

The circuit schematic is shown in figure 5.14 [145-149]. M9 and M10 constitute the

cLDMOS. Transistors M3 to M8 constitute level shift circuit, causes VG of M9 to be (VDDH-VDDL)/VDDH but VG of M10 is 0/VDDL. M1 and M2 is a CMOS inverter. In the simulation, a square input voltage (f = 20 MHz, 2 ns-long rise and fall ramp time, 3.3 V peak voltage) is applied on the gate of the CMOS inverter (M1 and M2). The circuit operates as follows: When Vin = 0V,

M1 is OFF and M2 is ON, the inverter output is VDDL, causes M8 and M10 to be ON, but M7 becomes OFF. ID (M8) = ID (M6), this drain current discharges the charge of

VDS (V)


116

M6, causes the drain voltage of M6 to decrease. As VD (M6) = VG (M3), the transistor M3 is ON with VDS =0 V. So, VD (M3) = VG (M9) = VDDH, causes M9 to be OFF, and the output becomes equal to 0V.

When Vin = VDDL,

M2 is OFF and M1 is ON, the inverter output is 0 V, causes M8 and M10 to be OFF, but M7 becomes ON. ID (M7) =ID (M4), this drain current discharges the charge of M4, causes the drain voltage of M4 to decrease. As VD (M4) = VG (M9), the transistor M9 is ON with VDS = 0 V. So, the output becomes equal to VDDH.

Figure 5.14: The circuit schematic of the interface circuit

The input and output waveforms are shown in figure 5.15.

Figure 5.15: The input and output waveforms of the interface circuit


117

5.7 Conclusion

A methodology for physically modeling the intrinsic MOS part and the drift region are presented. The effects of velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel are considered. The analytical model is implemented using MATLAB and MAPLE programs. With the help of the proposed analytical model, a Spice model is developed. We use level 3 MOS Spice model to implement the low voltage MOSFETs and the intrinsic MOS part of LDMOS. ICCAP and ISExtract tools are used to extract the Spice model parameters by using the results of the TCAD simulations as the input to these tools (as measured data).

The Spice model used is a simple one with small number of parameters compared to BSIM

models. Its parameters are easy to extract by using the extraction tools. The ID -VDS characteristics and ID -VGS characteristics are used to extract the model parameters, with the source tied to the bulk. The comparison of the TCAD simulations and the Spice model simulation for both nLDMOS and pLDMOS at room temperature shows accuracy less than 5% for the whole voltage domain. An interface circuit to convert the low logic level 0/3.3 V to high voltage level 0/42 V, suitable for the future automotive applications is proposed.


118

CHAPTER 6

Substrate Coupling in Smart Power Integration

Chapter 6: Substrate Coupling in Smart Power Integration

120


121

6.1 Introduction

In this chapter, two technologies are proposed to implement the smart power integrated circuits. The first one is the planar integration using the deep trench isolation (DTI) technique, and the other one is the new stacked 3D-integration using through-silicon vias (TSVs). Hence the chapter is divided into two parts; in each part we study the impact of substrate perturbations due to the HV digital signal on the performance of the low voltage MOS devices.

Part I: Smart Power Integration using Deep trench isolation technique 6.2 Deep trench isolation technology

In smart power ICs, there are substantial improvements in performance and reliability, and

reduction in cost compared to discrete approach. The savings come from the elimination of the many packages needed to house the individual chips. However, crosstalks between power devices as well as interaction between power and low-voltage devices were the most important hurdles [150, 151].

The objective of this part of the chapter is to introduce the deep trench isolation (DTI) scheme for high voltage isolation. Deep trench based processes have been integrated previously in CMOS architectures to suppress inter-well parasites and CMOS thyristor latchup. This isolation scheme is used nowadays to reduce the isolation distance between power devices as well as between power device and low-voltage CMOS devices and hence to reduce the total chip area drastically compared to technologies with a standard junction isolation scheme [152-154].

Although SOI platforms are very effective in electrical isolation and chip area reduction,

the design complexity, higher wafer cost and lower heat removal capability limit the use of these technologies. The deep trench high-voltage isolation is a low-cost alternative to SOI in realizing significant analog shrink. This type of isolation is suitable for the smart power automotive ICs [155, 156].

In this chapter, the impact of DTI scheme on the performance of both the HV LDMOS and

the LV CMOS devices is discussed. Also, the electrical impact of the (0.0/42.0V) dynamic signal of the future automotive applications on the CMOS parts is studied. 6.3 Deep trench isolation structure

During the development phase of the deep trench, severe silicon stress situations leading to defects within the silicon material are faced. An extensive process is required in order to get finally the complete structure free of defects. The filler material combination (oxide / polysilicon) is chosen for this defectivity purpose [157].

A high quality thermal oxide liner is grown along the side-walls of the deep trench. A

polysilicon stress-relief layer is deposited so that it fills the deep trench and is recessed below the silicon surface. The polysilicon has a nearly perfect conformal deposition, that is, both step coverage and bottom coverage are 100% [158, 159].


122

However, when two Nepi regions are placed adjacent with a deep trench separation as shown in figure 6.1, punch-through under the deep trench becomes a concern. This can be avoided in P- substrate with punch-through retardation implants (P+ Boron implant) or simply by increasing the depth of the trench significantly.

Figure 6.1: The deep trench isolation structure

6.4 LDMOSFETs performance with deep trench isolation

In figure 6.2, an nLDMOS and pLDMOS devices isolated with DTI are shown, which

constructs a complementary LDMOS (cLDMOS). An in-depth investigation was done with the help of TCAD simulations in order to fully describe the functionality of the deep trench isolation structure.

Figure 6.2: The structure of cLDMOS with deep trench isolation

6.4.1 OFF-state performance

Leakage current levels of nLDMOS and pLDMOS are very low with deep trench isolation and are not different from junction leakage without deep trench, indicating that there is no additional leakage due to deep trench presence as illustrated in figures 6.3a and 6.3b. The deep trench oxide thickness is sufficient to sustain a breakdown voltage from N-epi to substrate of more than 300V, which is greater than the breakdown voltage of both devices.

As shown in figure 6.3 the leakage currents for nLDMOS and pLDMOS are in the order of

1.0E-14 A/µm and 1.0E-19 A/µm, respectively. These values of leakage currents are very small compared to the values of the drain currents. It is clear from the figure that, the OFF-


123

state breakdown and the currents of the drain and the bulk are approximately unchanged with the presence of trench isolation.

(a) (b) Figure 6.3: The drain and bulk currents for (a) nLDMOS, and (b) pLDMOS, without trench isolation (dashed

curves), and with trench isolation (solid curves) The potential and electric field distributions in the OFF state for both nLDMOS and

pLDMOS are shown in figures 6.4 and 6.5. The deep trench does not affect the distribution of the electric field, which is approximately distributed uniformly over the drift region of each device.

(a) (b)

Figure 6.4: (a) Potential distribution, and (b) Electric field distribution, in nLDMOS

(a) (b)

Figure 6.5: (a) Potential distribution, and (b) Electric field distribution, in pLDMOS.


124

6.4.2 ON-state performance The ON-state characteristics are not changed with the use of the deep trench isolation. The

ON-state characteristics of both nLDMOS and pLDMOS at |VGS | =3 V, are shown in figure 6.6.

(a) (b)

Figure 6.6: The drain currents of (a) nLDMOS, and (b) pLDMOS, at |VGS | =3 V, without trench isolation (dashed curve), and with trench isolation (solid curve)

6.5 Parasitics suppression in 2D smart power ICs with deep trench

Minority carrier diffusion is a main problem in smart power ICs where underground conditions on the output driver stage can lead to significant electron current injection into the substrate. Negative voltages (down to -1.5V) occur in power stages due to inductive loads switching during normal operation (motor control in automotive applications), cause the injection of minority carriers into the substrate, leading to their collection by sensitive N-wells in the pLDMOS device or in the CMOS devices, which in turn causes potential failures of their functionalities.

A simplified cross-section, containing the cLDMOS, CMOS, and the parasitic NPN BJT is

shown in figure 6.7. In this structure, The CMOS is simplified to have the source contacts of the MOS devices only.

Figure 6.7 : Simplified cross-section, showing the cLDMOS, the CMOS, and the parasitic NPN transistor


125

It is illustrated from the figure that the N+ source contact of the nMOS and the N+ source-body contact of the nLDMOS are tied to ground, while the P+ source contact of the pMOS is connected to VDDL (3.3V) and the P+ source-body contact of the pLDMOS is connected to VDDH (42.0V), which is the new automotive battery voltage.

Due to the negative bias applied to the drain of the cLDMOS, the N-epi /P-substrate diode

becomes forward biased and induces a huge current. Most of the current is drained towards the source (Sn), through the intrinsic body diode. The remaining part of the injected current (IE) flows into the substrate, and can be collected by any reverse biased junction.

The N-region of the pLDMOS at VDDH acts as a collector of the lateral parasitic NPN

transistor with current IC1, as shown in figure 6.7. Other N-regions on a positive potential VDDL, e.g. those of the controlling circuitry, also collect the minority carriers with current IC2, which can disturb the functionality of its components.

In BiCMOS technology, all devices share the same epitaxial layer, which leads to cross-

talk between power devices as well as between power and low-voltage CMOS devices. The injection collected ratio α, which defined as the ratio of the collected current IC to the injected current IE , ( EC II=α ) reaches about 0.35. But, when using the deep trench isolation, this ratio is reduced by a factor between 3 and 8.5.

Insight investigations are done with a TCAD device simulator because a circuit simulator

does not take into consideration minority carriers. The simulations are carried out with a voltage of -2V applied on the drain of the cLDMOS and all the other contacts are grounded, as it is difficult to characterize the structure of figure 6.7 with multi-potential levels (-2V, 0V, 3.3V, 42.0V) in TCAD because of the convergence problems.

The injection collected ratio (α) of the most sensitive devices as a function of the trench

length (LDTI) in two cases, with and without P+ implant are shown in figures 6.8a, and b.

0.04

0.06

0.08

0.10

0.12

7 8 9 10LDTI (μm)

α1 =

IC

1 /

I E

With P+Without P+

0.035

0.040

0.045

0.050

7 8 9 10LDTI (μm)

α2

= I

C2

/IE

With P+Without P+

(a) (b)

Figure 6.8: The injection collected ratio of (a) pLDMOS, and (b) pMOS in two cases with and without P+ For the first case: trench isolation without P+ implant, the injection collected ratio α1

decreases with the increase of LDTI for LDTI ≤ 9µm as shown in figure 6.8a. For the same range values of LDTI, α2 is increased as illustrated in figure 6.8b. For LDTI = 10µm, the situation is reversed. This means that the amount of the deflected carriers changes as a function of the trench length and the distance between the emitter and the collector regions.


126

For the second case: trench isolation with P+ implant, the injection collected ratio α1 decreases with the increase of LDTI for the whole range and it is reduced by more than 23 % compared to the case without P+, as shown in figure 6.8a. α2 is nearly constant as illustrated in figure 6.8b. As a conclusion, this highly doped implant region reduces the life time of the minority carriers and hence reduces the collected carriers of the sensitive devices.

The negative substrate potential shift caused by the injected minority carriers has been

simulated for trench length of 8µm and for two cases: with and without P+ implant. It is illustrated from figure 6.9 that, the potential distribution and hence the electric field distribution are strong functions of P+ implant region.

Without the high implant region, the potential contours are crowded in the sensitive devices and this increase the electric field at these regions which in turn increase the collected minority carriers. In the other case with the presence of the high P+ implant region, the potential contours are reduced and hence reduces the collected current.

(a) (b)

Figure 6.9 : The potential contours distributions in case of (a) without P+, and (b) with P+ implant 6.6 HV dynamic signal impact on CMOS devices

To describe the HV dynamic signal impact on the CMOS parts through the substrate

perturbations, we first must describe the different injection mechanisms in a digital circuit. Most CMOS digital gates can be reduced into CMOS inverters. Figure 6.10 shows a CMOS inverter and its different sources of substrate noise [160].

Figure 6.10 : Substrate noise injection mechanisms in a digital inverter


127

The substrate coupling is through the parasitic capacitances of the MOSFET. First, the drain depletion (b) capacitance of each MOS transmits voltage variations into the substrate. In the case of an inverter, the output voltage is directly coupled to the substrate through the drain depletion capacitance of the nMOS and the pMOS. Additionally, the gate electrode is coupled to the bulk through the gate oxide (c) and the channel capacitance.

Another noise generator is the well known impact ionization (d). When a MOS transistor

is biased in the saturation regime, a high electric field develops in the depleted region of the channel near the drain. This high field generates hot carriers that can dissipate their energy by creating some electron-hole pairs. For an nMOS, the holes created are swept to the substrate. Other minor noise sources are described in different developments like gate induced drain leakage, photon-induced current and diode leakage current.

All carriers created by the injectors are propagated through the substrate, which has to be

quantified. Silicon material is characterized by a cutting frequency πεσ

2=cf where σ is the conductivity and ε the permittivity. With high resistivity substrate (> 10 Ω.cm), silicon can be considered as purely ohmic for signal frequency below 10 GHz [161]. This propagation could vary the body voltage, which varies in turn the MOS threshold voltage according to the following equation:

)22.(...2

fsbfox

ATOT V

CNq

VV Φ−+Φ−+=ε

(6.1)

Several methods exist to analyze the substrate propagation that is commonly considered as

propagation within finite conducting medium. The main ones are the following: solving the Poisson’s equation numerically with Green’s equations and boundary element method, or extracting an RC network model of the substrate from a 3D meshing: the finite element method. In this chapter, we will use the TCAD numerical simulations to quantify the coupling mechanism.

The MOS transistor is plugged on its static mode (VGS = VDS = 1.8 V) for the nMOS and

the static mode (VGS = VDS = -0.5V) for the pMOS, which are the biasing conditions for the convergence simulated structures. A square voltage (f = 200 MHz, 200 ps-long rise and fall ramp time, 42 V peak voltage) is then applied on the drain of cLDMOS which is represented by N+ electrode in the Nepi region. The saturation drain current IDSAT and the local body potential Vbody, located in between the conduction channel at 0.5µm under the gate oxide/silicon interface, are extracted during the transient analysis. This position enables to quantify the finest electrical disturbances that may modify the electrical behaviour of the transistors. We use a 100µm-substrate thickness with its backend connected to ground. 6.6.1 Impact on nMOS

The 2D cross-section of the simulated structure is shown in figure 6.11. The potential contours distributions are shown in figure 6.12, it is observed that all the potential lines distributed across the deep trench and Nepi/Psub junction space charge region far from the active area of the nMOS, so we expect that the effect of the applied dynamic signal is limited and negligible.


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Figure 6.11 : The 2D structure of the nMOS with DTI

Figure 6.12 : The Potential distribution of the nMOS structure with DTI

The waveforms of the saturation drain and the bulk currents are shown in figure 6.13a and

b. The signal coupling is through the parasitic capacitances of Nepi/Psub diode and the DT and the resistive network of the substrate this system acts as a differentiator for the dynamic signal applied on the drain electrode of the cLDMOS.

(a) (b)

Figure 6.13 : (a) The saturation drain current, and (b) the bulk electrode current due to 0.0/42.0V square signal applied on the cLDMOS drain for LDTI = 8µm

LDTI

LS


129

This fact is clearly illustrated through the waveform of the bulk current in figure 6.13b. The variation in the bulk current is about 65 pA/µm, which can be neglected with respect to the value of the saturation drain current. For the drain current in figure 6.13a, there is a ringing effect due to the capacitance coupling, but the variation is very small in the range of 0.04 %, which can be neglected. Also, the waveform of the body voltage has no variations.

6.6.1.1 Effect of DTI length (LDTI)

In figure 6.14, the percentage of the average variation in the drain current and the variation

of the bulk current are shown as a function of the trench length (LDTI). It is illustrated that increasing LDTI reduces the variations on saturation current (from more than 4E-2 % to less than 1E-2 %) because of increasing the base width of the parasitic BJT consisting of the Nepi (the drift region of nLDMOS) as an emitter region, the (Psub + Pwell +PBL) as a base region and the N+ source/drain of the nMOS as a collector. By increasing the base width of the parasitic BJT, the minority carriers transit time decreases and hence the collected carriers are decreased.

1.0E-5

1.0E-2

2.0E-2

3.0E-2

4.0E-2

5.0E-2

8 9 10

LDTI (µm)

ΔID

sat (

A/µ

m) %

5.0E-11

6.0E-11

7.0E-11

8.0E-11

7 8 9 10

LDTI (µm)

ΔIB

(A/µ

m)

(a) (b)

Figure 6.14 : (a) The saturation drain current, and (b) the bulk current, as a function of the deep trench length for LS = 3µm

The variation in the bulk current does not depend on the BJT effect; it depends on the

reverse conditions of the (Nepi/Psub) diode. So, the variation value is independent on the trench length as shown in figure 6.14b. 6.6.1.2 Effect of DTI spacing (LS)

The layout parameter LS (keep-away zone) may impact the coupling as illustrated in figure

6.15. It obviously seems that the keep-away zone has an impact on the coupling mechanism, especially for the bulk current. As LS increases, the coupling resistance increases and hence the collected currents are decreased. 6.6.2 Impact on pMOS

The 2D cross-section of the simulated structure is shown in figure 6.16. The potential

contours distribution in the ON-state is shown in figure 6.17, it is observed that all the potential lines distributed across the deep trench and Nepi/Psub junction space charge region far from the active area of the pMOS.


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1.0E-2

1.5E-2

2.0E-2

2.5E-2

3.0E-2

3.5E-2

4.0E-2

4.5E-2

5.0E-2

2 3 4 6

LS (µm)

ΔID

sat (

A/µ

m) %

1E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-09

1E-08

2 3 4 6

LS (µm)

ΔIB

(A/µ

m)

(a) (b)

Figure 6.15 : (a) The saturation drain current, and (b) the bulk current, as a function of the keep away zone length for LDTI = 8µm

Figure 6.16: The 2D structure of the pMOS with DTI

Figure 6.17 : The Potential distribution of the pMOS structure with DTI

The waveforms of the saturation drain current; the bulk current and the bulk voltage are

shown in figure 6.18 a, b and c. There are two parasitic devices, the first one is the parasitic BJT which is consists of Nepi/ Psub/ Nwell and the second one is the thyristor which is consists

LDTI

LS


131

of the four regions Nepi/ Psub/ Nwell / N+ drain. The parasitic BJT affects both the bulk voltage and the bulk current and the parasitic thyristor affects the drain current.

The large variation in the bulk current is explained by huge amount of the minority carriers collected by the large collector area. But, in the case of the drain current, the collected area is small, so the variation is small. Also, we observe spikes in the drain current switching waveform; they are due to the thyristor latchup phenomenon. 6.6.2.1 Effect of DTI length (LDTI)

It is observed from figure 6.19, that the drain and bulk currents and the bulk voltage variations increase with the trench length. As the trench length increases, the effective doping of the base region of the parasitic devices decreases and this in turn enhances the transit coefficient and thus the collected currents.

(a) (b)

(c)

Figure 6.18: (a) The saturation drain current, (b) the bulk electrode current, and (c) the bulk voltage due to 0.0/42.0V square signal applied on the cLDMOS drain for LDTI =8µm

6.6.2.2 Effect of DTI spacing (LS) From figure 6.20, we observe that, the variations of the electrical parameters of the pMOS

have insignificant change with the keep away zone length compared to the trench length effect.


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6

7

8

9

10

11

7 8 9 10

LDTI (µm)

ΔID

sat (

A/µ

m) %

2E-5

3E-5

4E-5

5E-5

7 8 9 10

LDTI (µm)

ΔIB

(A/µ

m)

(a) (b)

5

5.5

6

6.5

7

7 8 9 10

LDTI (µm)

ΔV

body

(V) %

(c)

Figure 6.19: (a) The saturation drain current, (b) the bulk electrode current, and (c) the bulk voltage as a function of trench length

7

7.5

8

8.5

9

9.5

3 4 6

LS (µm)

ΔID

sat (

A/µ

m) %

1E-05

1E-04

2 3 4 6

LS (µm)

ΔIB

(A/µ

m)

(a) (b)

6

6.5

7

2 3 4 6

LS (µm)

ΔVbo

dy (V

) %

(c)

Figure 6.20: (a) The saturation drain current, (b) the bulk electrode current, and (c) the bulk voltage as a function of DTI spacing


133

6.6.3 Impact on CMOS sensitive regions The 2D cross-section of the simulated structure is shown in figure 6.21. The potential

contours distributions in the ON-state are shown in figure 6.22, it is observed that all the potential lines distributed across the deep trench and Nepi/Psub junction space charge region far from the active area of the CMOS.

Figure 6.21: The 2D structure of the CMOS with DTI

The variations of the electrode currents are very small and can be neglected; this comes

from the existence of the Pwell which acts as a guard ring which in turn decreases the variations. So, the dynamic variations can be tolerated under specific design rules.

Figure 6.22 : The Potential distribution in the CMOS structure with DTI

6.6.3.1 The electro-thermal simulation

Using the electro-thermal analysis and with considering the bulk electrode is at 300 K (heat-sink at the bulk), the temperature waveform in the CMOS with DTI is shown in figure 6.23. We observe that the temperature is unchanged throughout the device.


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Figure 6.23 : The temperature waveform in the CMOS structure with DTI

6.7 Mixed-mode CMOS-substrate coupling simulation

The aim of this section is to evaluate the impact of the (0.0/42.0V) HV output signal from the cLDMOS drain on the operation of the CMOS inverter. To achieve this, basic simulations are performed using the SPICE models of the CMOS devices, which are previously extracted by means of the ICCAP extraction program and the finite element method (FEM) for the bulk regions of the devices. The used CMOS devices have threshold voltages of 0.65V for nMOS and -0.6V for pMOS. A (0.0/42.0V) square signal is applied to the cLDMOS drain noted vDdMOS and (0.0/1.2V) on the inverter input noted vin at 200MHz frequency of both. A load capacitor of 300pF is plugged at the inverter output. The CMOS output current is taken as an indicator for the substrate perturbations.

6.7.1 Simulation with floating nMOS bulk-electrode

The CMOS inverter bulk electrodes are connected to the active regions contacts to study

the sensitivity of the CMOS inverter electrical behaviour due to the fluctuations in the substrate potential as a result of the effect of the (0.0/42.0V) HV digital signal vDdMOS. In order to simplify the study, the pMOS bulk and source electrodes are shorted and only the impact on the nMOS is supposed as shown in figure 6.24.

Figure 6.24 : The Potential distribution in the CMOS structure with DTI when the nMOS

bulk electrode is floating


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The potential distribution in the CMOS structure with DTI for vin = 0.0/1.2V and vDdMOS = 0.0/42.0V is shown in figure 6.25a. It is observed that all the potential contours distributed across the deep trench and Nepi/Psub junction space charge region far from the active area of the CMOS devices. The waveforms of the cLDMOS drain, CMOS input and output voltages and the output current wave form (the current through the load capacitor) are shown in figure 6.25b. It is cleared from the figure that the current is switching w.r.t the CMOS input waveform and there is no effect of the digital HV output of the cLDMOS.

(a) (b)

Figure 6.25 : (a) The Potential distribution, and (b) The voltages and output-current waveforms for vin = 0.0/1.2V and vDdMOS = 0.0/42.0V, with floating nMOS bulk electrode

6.7.2 Simulation with floating pMOS bulk-electrode

The simulated structure is shown in figure 6.26. In this structure, the bulk and source electrodes of the nMOS are shorted and the impact on the pMOS is supposed.

Figure 6.26 : The Potential distribution in the CMOS structure with DTI when the pMOS

bulk electrode is floating


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In figure 6.27a, the potential distribution in the CMOS structure with DTI is shown for the same values of vin and vDdMOS in case of floating pMOS bulk contact. All the potential contours distributed across the deep trench and Nepi/Psub junction space charge region far from the active area of the CMOS devices. The waveforms of the cLDMOS drain, CMOS input and output voltages and the output current wave form are shown in figure 6.27b. It is cleared from the figure that the current is switching w.r.t the CMOS input waveform and there is no effect for the digital HV output of the cLDMOS.

We also observe that the output current switching pulse is vanished in the falling of the

CMOS input signal (when the pMOS in ON), this is due to the increase of the pMOS threshold voltage which in turn decrease the drain current.

(a) (b)

Figure 6.27 : (a) The Potential distribution, and (b) The voltages and output-current waveforms for vin = 0.0/1.2V and vDdMOS = 0.0/42.0V for floating pMOS bulk contact

Part II: Smart Power Integration using stacked 3D- technology 6.8 From 2D planar integration to 3D integration

In the previous part, we discussed the 2D integration of the HV devices with the low voltage CMOS devices, and explained briefly the static and dynamic coupling of this type of 2D planar smart power integration. In this technology, it is difficult to achieve the best performances of all the HV and LV devices mounted on the chip, due to their conflicting requirements as stated in chapter 4.

In recent years, there is an emerging technology which is the Three-dimensional (3D)

integration. This technology uses through-silicon-vias (TSVs) and re-distribution Layers (RDLs) to interconnect multiple active circuit layers. 3D integration offers significant improvements over two-dimensional (2D) integrated circuits (ICs) on performance, functionality, and integration density. By reducing the length of global interconnects significantly, 3D integration promises a solution to the severe delay problems that are being, and will be, encountered as process geometries shrink. Furthermore, 3D integration also provides new architectures for sophisticated ICs and facilitates the integration of


137

heterogeneous materials, devices, and signals, enabling the realization of extended system-on-a-chip (SoC) as shown in figure 6.28 [160, 162].

Figure 6.28: The cost and performance comparison among the various technologies

Speaking at the 2006 IEEE International Electron Devices Meeting (IEDM), Dr. Chang-

Gyu Hwang, president and CEO of Samsung Electronics, stated that “…rapid adoption of 3-D integration technology seems to be essential and, thankfully, unavoidable.” He believes that the industry paradigm will shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D silicon-based technologies in highly integrated systems. Indeed, 3D integration is recognized as an enabling technology for future ICs and low-cost micro/ nano/electro-opto/bio heterogeneous systems.

The ITRS roadmap shows 3D integration as a key technique to overcome the so-called

“wiring crisis”. In addition to the enabling of further improvement of transistor integration densities (“More Moore”), 3D integration is a well-accepted approach for so-called “More than Moore” applications. In general, this technology provides a path for continued improvement in performance, power, cost and size at the system level without relying upon conventional CMOS scaling alone. 6.8.1 3D ICs with through silicon (TSV) or interplane vias

Interplane vias offer the greatest possible reduction in wire length with vertical integration

and it is less costly than today’s state-of-the-art for mixed technologies products, monolithically integrated systems-on-a-chip (2D SoC). In addition, each plane of a 3D system can be processed separately, decreasing the overall manufacturing time. As each IC of the 3D stack is fabricated individually, the yield for each individual IC can be high. A broad spectrum of fabrication techniques for 3D ICs has been developed. Initially, CMOS or SOI wafers are processed separately, producing the physical planes of the 3D stack, while a certain amount of active area is reserved for the through silicon vias. The interplane vias are etched and filled with metal, such as tungsten (W) or copper (Cu), or even low-resistance polysilicon.

The formation of the through silicon or interplane vias is an important issue in the design

of high-performance 3D ICs. This fabrication stage includes the opening of deep trenches through the interlayer dielectric (ILD) and the metal and device layers, passivation of the trench sidewalls from the metal layers and conductive substrate (for CMOS circuits), and filling the opening with a conductive material to electrically connect the planes of the 3-D system. An example of a heterogeneous 3D system with through-silicon vias (TSV) is shown


138

in figure 6.30. The system is a stack of power IC plane, digital IC plane, analog IC plane, and RF IC plane.

Figure 6.29: An example of a heterogeneous 3D system-on-chip

6.9 3D Smart Power integration

TSV appears to be one of the greatest technology challenges brought by 3D integration and RDL features large metal lines implemented on the backside of the thinned active stratum. Both structures leading to electrical parasitic coupling and critical substrate noise on neighboring active devices. This coupling might be restrictive for design capabilities and needs to be quantified as a function of layout and technology parameters and TSV/RDL isolation oxide thicknesses. This will lead to define tuneable 3D-specific design rules that will ensure reliable circuit design according to the application choice. Perhaps, we could use previously defined DTIs as TSVs.

Two and three-dimensional TCAD-based simulation of TSV or RDL induced coupling – is

investigated on nMOSFET, pMOSFET, and the sensitive regions of the CMOS inverter. The considered region is bounded by a doted ellipse as shown in figure 6.30.

Figure 6.30: TSV and RDL – based 3D integration

Sensors Antenna

I/O Pad Array

Heat Sink Substrate


139

3D integration can be implemented with various device technologies. We focus on 0.35 µm bulk BiCMOS devices integrated with TSV and RDL. Silicon substrate is thinned in the range of 5 to 20 µm (TSUB). Only electrical coupling phenomena occurring within the thinned stratum are considered, all other integration process steps do not impact our methodology. This study can be applied to a majority of case. Simulated MOSFET has a channel length is 1 µm in order to avoid short-channel effects.

The saturation and leakage drain currents demonstrate rather accurate performance for this

range of channel length. TSV and RDL are respectively considered as intra bulk and backside electrodes – independent from each other and isolated from the thinned substrate with an appropriate oxide layer. TSV and RDL isolation oxide thicknesses are two important technology parameters. They are respectively noted as TOXTSV and TOXRDL.

In this work, we propose to observe how a square signal applied independently on these

two electrodes may impact the electrical characteristics of the nMOS and pMOS transistors, respectively. In order to understand how the substrate coupling occurs within the structure, the three technology parameters previously described as TSUB, TOXTSV and TOXRDL, and a layout parameter, LS are investigated in the simulation methodology.

The MOS transistor is plugged on its static mode (VGS = VDS = 1.8 V) for the nMOS and

the static mode (VGS = VDS = -1.2 V) for the pMOS, which are the biasing conditions for the convergence simulated structure. A square voltage (f = 200 MHz, 200 ps-long rise and fall ramp time, 42.0 V peak voltage) is then applied on the TSV or on the RDL. The saturation drain current IDSAT and the local body potential Vbody, located in the conduction channel at 0.5µm under the gate oxide/silicon interface, are extracted during the transient analysis. This position enables to quantify the finest electrical disturbances that may modify the electrical behaviour of the transistors. 6.9.1 Impact of TSV and RDL on nMOS The 2D cross-section of the simulated structure is shown in figure 6.31.

Figure 6.31: The 2D structure of the thinned stratum with nMOS


140

6.9.1.1 The impact of TSV (RDL is floating) The potential contours distribution is shown in figure 6.32. It is observed that all the

potential lines distributed across the space charge region far from the active area of the nMOS; so we expect that the effect of the dynamic signal applied on the TSV is limited and negligible.

The waveforms of the saturation drain current and the bulk current are shown in figure 6.33 a and b. The signal coupling is through the TSV parasitic distributed capacitances and the substrate impedance this system acts as a differentiator for the dynamic signal applied on the TSV electrode. This fact is clearly illustrated through the waveform of the bulk current in figure 33b. The variation in the bulk current is about 5nA/µm, which is effective with respect to the value of this, current but can be neglected with respect to the value of the saturation drain current. For the drain current in figure 33a, there is a relaxed effect due to the capacitance coupling, but the variation is very small in the range of 0.01 %, which can be neglected.

The effect of the technology parameters TSUB, TOXTSV and TOXRDL, and a layout parameter,

LS are investigated in the following figures.

Figure 6.32: Potential distribution for RDL floating for TSUB =10µm and TOXTSV =0.05µm

(a) (b)

Figure 6.33: (a) The saturation drain current and (b) the bulk electrode current due to 0.0/42.0V square signal on the TSV for TSUB=10µm and TOXTSV =0.05µm

In figure 6.34, the percentages of the dynamic variation in the saturation drain current as a

function of the substrate thickness for two different TSV oxide thicknesses. It is shown that a


141

thicker oxide for TSV isolation reduces significantly variations on saturation current (5.0e-3 % to 2.5e-4 %) because of the decrease of TSV oxide capacitance.

Figure 6.34: The saturation drain current as a function of the substrate thickness for different TSV oxide

thicknesses for LS = 3.0µm and TOXRDL =0.5µm The dynamic variation in case of 5µm substrate is not included because there is no

variation is observed in this case. This is due to increasing the coupling resistance and consequently the TSV coupling decreases. As previously stated, the coupling mechanism depends mainly on the bulk conductance, the TSV distributed capacitances and the MOSFET parasitic capacitances.

The bulk current IB is an important tool to measure the coupling, this is shown in figure 6.35. It is reported that the substrate thickness has a rather low impact on dynamic variations of the bulk current for thickness in the range of 5 to 20 µm. The current is decreased from 5e-9 to 2.5e-9 A/µm with increasing the TOXTSV from 0.05µm to 0.5µm.

Figure 6.35: (a) The bulk current as a function of the substrate thickness for different TSV oxide thicknesses

for LS =3.0µm and TOXRDL =0.5µm

The layout parameter LS (so called keep-away zone) may impact the coupling as illustrated in figure 6.36. It seems obvious that keep-away zone, does not have enough impact to decrease the coupling, compared to the influence of technology parameters. The fact is TSV-induced coupling occurs all along the TSV, so that substrate noise propagates at the same time through the low-resistivity doped well, and through the high-resistivity bulk silicon.


142

6.9.1.2 The impact of RDL (TSV is floating)

The distribution of the potential lines is shown in figure 6.37. The potential contours are distributed across the RDL oxide and the depletion region produced from the repulsion of the substrate majority carriers and the potential in the active area of the nMOS is small enough to impact the characteristics of the device. Impact of RDL-induced substrate coupling is reported on figure 6.37. There is no effect of RDL isolation thickness on variations of saturation drain current. Compared to previous TSV study, RDL-induced coupling seems to be less substantial as the bulk resistance increases with thicker silicon substrate.

(a) (b)

Figure 6.36: (a) The drain current and (b) the bulk current as a function of the TSV spacing in the ON and OFF states for TSUB=10µm, TOXTSV =0.05µm and TOXRDL =0.5µm

In conclusion, in nMOS the coupling is through a reversed biased P-N junction (Nepi /Pwell),

so the current variations are very small.

Figure 6.37: Potential distribution for TSV floating for TSUB=10µm, TOXTSV =0.05µm, and TOXRDL =0.5µm

6.9.1.3 Impact of TSV and RDL

It was explained how TSV and RDL structures produce substrate noise independently and

what typical response on active devices is. Considering the TSV is connected to the RDL line meaning that the same signal is applied on both structures - their respective coupling noise


143

can be added to obtain the global substrate noise produced by 3D architecture. The global response on nMOS saturation drain current and bulk current is depicted on figure 6.38a and b. for equivalent oxide thicknesses of TSV of 0.05µm and RDL of 0.5µm.

Figure 6.38: Potential distribution for TSUB=10µm and TOXTSV =0.05µm

(a) (b)

Figure 6.39: (a) The saturation drain current and (b) the bulk electrode current due to 0.0/42.0V square signal on the TSV and RDL for TSUB=10µm and TOXTSV =0.05µm

By comparing the variations in the electrical quantities due to the TSV with RDL floating

in figure 6.33 and the variations in figure 6.39 due to both TSV and RDL, one can conclude that, the variations are due to TSV impact. 6.9.2 Impact of TSV and RDL on pMOS The 2D cross-section of the simulated structure is shown in figure 6.40. 6.9.2.1 The impact of TSV (RDL is floating)

The potential contours distribution is shown in figure 6.41, it is observed that all the

potential lines distributed across the space charge region in the substrate produced from the repulsion of the substrate majority carriers. This potential is negative and the potential lines of


144

the 0.0/42.0V TSV signal are applied across the TSV oxide. So, the TSV oxide thickness must be chosen to support the maximum applied voltage.

Figure 6.40: The 2D structure of the thinned stratum with pMOS

The waveforms of the saturation drain current; the bulk current and the bulk voltage are

shown in figure 6.42a, b and c. Due to the direct coupling between the active area of the pMOS and the epitaxial layer, the variations in the electrical quantities are significant as shown in the figure.

Figure 6.41: Potential distribution for RDL floating for TSUB=10µm and TOXTSV =0.05µm

The effect of the technology parameters TSUB, TOXTSV and TOXRDL, and a layout parameter,

LS are investigated in the following figures. From figures 6.43-6.48 the variations on the saturation drain current IDSAT, the bulk current and the body potential Vbody are extracted during transient analysis as a function of LS. It is observed that potential and current variations follow the same behaviour and the impact of TSV decreases with increasing the keep-away zone length.

The substrate has a significant effect on the body voltage and the bulk and the drain

currents as illustrated in the figures. The coupling is a function of the bulk conductance and the TSV distributed capacitances.


145

(a) (b)

(c)

Figure 6.42: (a) The saturation drain current , (b) the bulk electrode current, and (c) the body voltage due to 0.0/42.0V transient signal on the TSV for TSUB=10µm and TOXTSV = 0.05µm and LS = 3.0µm

Figure 6.43: The saturation drain current as a function of the TSV spacing at various TSV oxide thicknesses

for TSUB =10µm, TOXTSV = 0.05µm and TOXRDL =0.5µm

Figure 6.44: The bulk voltage as a function of the TSV spacing for different TSV oxide thicknesses for

TSUB =10µm, TOXTSV =0.05µm and TOXRDL = 0.5µm


146

Figure 6.45: The bulk current as a function of the TSV spacing for different TSV oxide thicknesses for

TSUB=10µm, TOXTSV =0.05µm and TOXRDL =0.5µm

Figure 6.46: The saturation drain current as a function of the substrate thickness at various TSV oxide

thicknesses for LS= 3.0µm, TOXTSV = 0.05µm and TOXRDL =0.5µm

Figure 6.47: The bulk current as a function of the substrate thickness at various TSV oxide thicknesses for

LS = 3.0µm, TOXTSV =0.05µm and TOXRDL = 0.5µm

Figure 6.48: The bulk voltage as a function of the substrate thickness at various TSV oxide thicknesses for

LS= 3.0µm, TOXTSV =0.05µm and TOXRDL =0.5µm


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6.9.2.2 The impact of RDL

The distribution of the potential lines is shown in figure 6.49. The potential contours are distributed across the RDL oxide and the depletion region produced from the repulsion of the substrate majority carriers and the potential in the active area of the pMOS is small enough to impact the characteristics of the device.

Figure 6.49: Potential distribution for TSV floating for TSUB=10µm, TOXTSV =0.05µm and TOXRDL =0.5µm There is no effect of RDL isolation thickness on variations of saturation drain current for

TSUB >5µm. The waveform of the drain current is shown in figure 6.50. Compared to previous TSV study, RDL-induced coupling seems to be less substantial as the bulk resistance increases with thicker silicon substrate. In conclusion, in pMOS the coupling is direct through Nepi and Nwell, so there are significant variations in the ON and OFF biasing conditions. For TSUB > 5µm, the effect of RDL is neglected.

Figure 6.50: Body-voltage for RDL 0.5µm ON case TSUB =5µm

6.9.2.3 Impact of TSV and RDL

It was explained how TSV and RDL structures produce substrate noise independently and

what is typical response on active devices. Considering the TSV is connected to the RDL line meaning that the same signal is applied on both structures - their respective coupling noise can be added to obtain the global substrate noise produced by 3D architecture. The potential distribution is shown in figure 6.51 and the global response on pMOS saturation drain current


148

and bulk current is depicted on figure 6.52a, b and c for equivalent oxide thicknesses of TSV of 0.05µm and RDL of 0.5µm.

Figure 6.51: Potential distribution for TSUB=10µm TOXTSV =0.05µm

(a) (b)

(c)

Figure 6.52: (a) The saturation drain current, (b) the bulk electrode current, and (c) the body voltage due to 0.0/42.0V square signal on the TSV and RDL for TSUB=10µm TOXTSV =0.05µm

By comparing the variations in the electrical quantities due to the TSV with RDL floating

in figure 6.42 and the variations in figure 6.52 due to both TSV and RDL, one can conclude that, the variations are due to TSV for substrate thickness large enough (TSUB > 5µm).


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6.9.3 Impact of TSV and RDL on CMOS

The simulated structure is shown in figure 6.53, and the potential distributions in CMOS active regions for floating RDL and floating TSV are shown in figure 6.54a and b.

Figure 6.53: The CMOS sensitive regions

(a) (b)

Figure 6.54: The CMOS potential distribution for (a) floating RDL, and (b) floating TSV In case of CMOS, the floor planning is very important. The Pwell region, which is the

active area of the nMOS, must be implanted beside the TSV to act as a guard-ring for the Nwell which is the active area of the pMOS.

6.10 TSV-CMOS mixed mode Coupling

Our concept in this section comes from the fact that; when the MOS bulk-electrode is

floating, the bulk potential becomes a function of the substrate perturbations and this affects the value of the threshold voltage which in turn varies the MOS drain current. Also, the switching of the MOS drain current due to an applied square signal is a strong function of the MOS and the bulk capacitances. So, the aim of this section is using the CMOS output current as an indicator to determine the source of the bulk variation: the CMOS input voltage or the TSV HV signal and hence evaluate the impact of the TSV on the CMOS inverter. The used


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CMOS devices are previously implemented using the standard layers of the 0.35µm BiCMOS technology delivered by ST Microelectronics and with threshold voltages of 0.65V for nMOS and -0.6V for pMOS.

To achieve this aim, basic simulations are performed using the SPICE models for the

CMOS devices and the finite element method (FEM) for the bulk regions of the devices and this mixed-mode simulation is performed using TCAD program packages. In the mixed mode simulation, we use the Spice model parameters which are extracted by means of the ICCAP extraction program.

In the simulations, the CMOS inverter bulk electrodes are connected to the active

regions contacts with a load capacitor of 300pF is plugged at the inverter output and a frequency of 200MHz is used for the applied square signals. A supply voltage (V+) of 1.2V and a CMOS input voltage (vin) of (0.0/1.2V) are chosen for the simulation conversion problems. 6.10.1 2D TSV-CMOS mixed mode Coupling

In this sub-section, the 2D structure of the active regions of the CMOS is considered to

study the effect of the position of TSV (near the nMOS or the pMOS) on the body of low voltage MOS devices.

6.10.1.1 The TSV in the nMOS side

The 2D structure is shown in figure 6.55, with the TSV is placed near the nMOS device

with TOXTSV = 0.5µm and V+ =1.2V. In this structure, the pMOS bulk and source electrodes are shorted and only the impact on the nMOS is supposed as shown in figure.

Figure 6.55: The 2D structure of TSV-CMOS with floating nMOS bulk contact

The potential distribution in the TSV-CMOS structure is shown in figure 6.56a. It is clearly

observed that nearly half of the TSV voltage is dropped across the TSV oxide and the other half across the depleted region in the substrate and there is a few potential contours are


151

observed in the active regions of the MOS devices. The waveforms of the TSV, CMOS input and output voltages and the output current wave form (the current through the load capacitor) are shown in figure 6.56b. It is cleared from the figure that the current is switching w.r.t the CMOS input waveform and there is no effect of the digital HV signal of the TSV.

(a) (b)

Figure 6.56: (a) The Potential distribution, and (b) The voltages and output-current waveforms for vin = 1.2V and vTSV = 42.0V, with TSV located in the nMOS side

6.10.1.2 The TSV in the pMOS side

In this case, the TSV is placed near the pMOS device. In this structure, the TSV coupling is studied in two cases; one when the bulk contact of the nMOS is floating and the other case when the bulk contact of the pMOS is floating.

6.10.1.2.1 The bulk contact of the nMOS is floating

The 2D structure is shown in figure 6.57 for the case of floating nMOS bulk contact.

Figure 6.57: The structure of TSV-CMOS with floating nMOS bulk contact


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The potential distribution in the TSV-CMOS structure is shown in figure 6.58a. In this case, approximately all the TSV voltage is applied on the TSV-oxide and nearly no potential contours in the substrate and the active regions of the devices, so, it is very important to implement the TSV with oxide-thickness sufficient to support the applied voltage. The waveforms of the TSV, CMOS input and output voltages and the output current wave form are shown in figure 6.58b. It is cleared from the figure that the current is switching w.r.t the CMOS input waveform and there is no effect of the digital HV TSV.

(a) (b)

Figure 6.58: (a) The Potential distribution, and (b) The voltages and output-current waveforms for vin =0.0/1.2V and vTSV = 0.0/42.0V, with TSV located in the pMOS side and with floating nMOS bulk contact

6.10.1.2.2 The bulk contact of the pMOS is floating

The 2D structure of this case is shown in figure 6.59. The potential distribution is applied

on the TSV-oxide as shown in figure 6.60a. In this case, approximately all the TSV voltage is applied on the TSV-oxide.

Figure 6.59: The structure of TSV-CMOS with floating pMOS bulk contact


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The waveforms of the TSV, CMOS input and output voltages and the output current wave form are shown in figure 6.60b. It is clearly observed that, the CMOS output-voltage and current are strong functions of the vTSV signal (as illustrated from the output current spikes at switching instants of the TSV square signal). This means that, there is a strong impact for the TSV on the bulk region of the pMOS and this impact increases with increasing the peak value of the TSV square signal. So, in smart power ICs, if the TSV is placed near the pMOS transistor, the TSV signal has a strong impact on the performance of the low voltage control circuits.

(a) (b)

Figure 6.60: (a) The Potential distribution, and (b) The voltages and output-current waveforms for vin = 0.0/1.2V and vTSV = 0.0/42.0V, with TSV located in the pMOS side and with floating pMOS bulk contact

6.10.1.2.3 Effect of P+ guard-ring

To protect the low voltage structure from impact of the TSV HV signal, we use P+ guard-

ring. This region is implemented using the same mask of the nMOS Pwell active area and with the same doping level. So, there is no extra cost for the implementation of the guard regions. The structure of TSV-CMOS with floating pMOS bulk contact and with P+ guard-ring is shown in figure 6.61.

Figure 6.61: The structure of TSV-CMOS with floating pMOS bulk contact and with P+ guard-ring


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The Potential distribution in the TSV-CMOS structure is shown in figure 6.62a. The waveforms of the TSV, CMOS input and output voltages and the output current wave form are shown in figure 6.62b. It is illustrated from the figure that, in steady-state the current is switching w.r.t the CMOS input waveform and there is no effect of the TSV applied square signal. In conclusion, only the CMOS input signal has an effect on the CMOS performance.

(a) (b)

Figure 6.62: (a) The Potential distribution, and (b) The voltages and output-current waveforms for vin = 1.2V and vTSV = 42.0V

The question now is that: is the 2D structure (omitting the third dimension) sufficient to

simulate the substrate-coupling due to the impact of the TSV or we must use the 3D structure?

6.10.2 3D TSV-CMOS mixed mode Coupling The 3D structure is shown in figure 6.63. We use the simulator Sentaurus [163]; which is a

software package based on finite element method (FEM), to perform this mixed-mode simulation with the bulk regions connected to the SPICE models of the CMOS devices.

Figure 6.63: 3D Cross-section of TSV-CMOS mixed mode coupling

The TSV has a cylindrical shape filled with copper and with oxide thickness TOXTSV =

0.5µm as shown in the figure. In order to simplify the study, only the coupling between the


155

TSV and the nMOS is supposed. The nMOS transistor is placed near the TSV as illustrated in the figure. A Y-cut cross-section potential distribution is shown in figure 6.64a, for vin = 0.0/1.2V and vTSV = 0.0/42.0V.

The waveforms of the TSV, CMOS input and output voltages and the output current wave

form (the current through the load capacitor) are shown in figure 6.64b. It is cleared from the figure that the current is switching w.r.t the CMOS input waveform and there is no effect of the digital HV of the TSV.

(a) (b)

Figure 6.64: (a) Y- cut potential distribution, and (b) The voltages and output-current waveforms at vin = 0.0/1.2V and vTSV = 0.0/42.0V

Comparing the 2D TSV-CMOS results in figure 6.56 and 3D TSV-CMOS results in figure

6.64, we observe that, the 3D output current has larger peak value and smaller rise and fall times. This is because the area of coupling in 3D is large and hence the current increases and the coupling capacitances decrease which in turn decrease the time constant. Hence, the 3D structure is preferred as all the parasitic effects can be, a priori, taken into account and the results of simulation can touch with a high degree the real case. But a lot of CPU running time is needed which can be compensated by using multi-processors computer with high memory. Moreover, in 3D, it is hard to visualize mesh obtuse angles, for instance; so, many trials should be needed to obtain a “good” solution.

Now, it seems necessary to analyse the TSV/device also in an electromagnetic point of

view, because of the high frequency parasitic phenomena involved in complex circuits. We begin hereafter by the via.

6.11 Electromagnetic impact of TSV in RF range

The track of this section is to use a Finite Difference Time domain (FDTD) method which resolves the two equations of Maxwell relative to the fields' curls - the electric field E, and the magnetic excitation H, based on the pioneering paper of Yee [164]. We do a relatively in-depth study of some via: via with two striplines. For that, we use the simulator Sentaurus and the FDTD method for the electromagnetic field.


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6.11.1 The Finite-Difference Time-Domain (FDTD): brief recall

Mawxell’s equations relative to the vertical fields, considering media as perfect (Homogeneous, Linear and Isotropic) are:

tH

E∂

∂⋅−=×∇

µ

(1)

EtE

H

σε +∂∂

⋅=×∇

(2)

Where µ denotes the permeability, ε the permittivity, and σ the electric conductivity.

Although there are different ways to solve Maxwell’ equations numerically, the FDTD is one of the most suitable schemes for the purpose of analyzing 3-D structures. Yees’s pioneering approach [164, 165] uses centred differences to approximate space and time derivatives. The region being modeled is represented by two interleaved grids, one containing the edges of the electric field and the other containing the edges of the magnetic one. Time derivatives are not computed at the same time-frame, but at different interlaced intervals. Each unknown field component depends only on previously-calculated components of the dual kind: two sets of equations are thus recovered, each set being composed of independent equations, this so-called “leapfrog” algorithm. This algorithm makes the set of linear equations easy to handle and solve sequentially. For instance the curl relative to the H-field can be approximated as:

( )zzle

nz

nzixixiyiy

EJt

EEdy

HH

dx

HH

,

12

1:21:2

1:21:

+∆

−⋅=

−−

− +−+−+ε

(3)

( )zzle EJ ,

can be evaluated at the instant (n+½).∆t using a semi-implicit approximation :

[ ]

+= +++ n

znz

nzle

nzle EEJJ 12

1

,2

1

, 21

(4)

A stability criterion is written as:

∆t ≤

222

1111

zyxc

∆+

∆+

∆

(5)

Where c is the propagation speed in the medium and ∆x, ∆y and ∆z are the cell

minimum spaces in the FDTD grid. Finally, the computation domain is chosen large enough to have possibly two ports on stripline(s) sufficiently far away from the via discontinuity. The space grid size must be such that over one increment the electromagnetic field does not change too much; this means that, to have meaningful results, the linear dimension of the grid must be only a fraction of the wave length.


157

6.11.2 Via structure

For the purpose of this study, FDTD simulations have been carried-out on a realistic pattern (one via filled with tungsten, flanked with two copper strip lines) with a Gaussian pulse excitation of 1V peak. From the EM study, parameters such as dispersion ones can be computed. First, parallelepiped TSV have been considered (figure 6.65). It is completely filled with tungsten and embedded in silicon- substrate. Two-ports S-parameters simulation is performed and electrical parameters such as the self inductance value and the electrical resistance can be extracted from the Z-matrix considering Z12 and Z21 terms, for instance.

(a)

(b)

Figure 65: System via and striplines: (a) 3D-structure, and (b) Cut along the X-axis

The geometrical characteristics of the structure are: Via:

o Width : 4 µm o Height : 30 µm

For each stripline: o Width : 4 µm o Thickness : 1 µm o Lenght : 100 µm


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Silicon substrate: o Thickness : 60µm o Length : 200 µm o Width : 100 µm

We perform transient simulations for each stripline without being connected to the via, for

extraction of incident pulses, and, for instance, characteristic impedance, propagation constants. Other simulation procedures for the striplines connected to the via, with each port excited, are needed for extraction of scattered pulses. We can, follow the propagation of the fields, specially across the via itself; the transient electric wave travelling is represented in figure 66 from left to right and the voltages at the probe points (figure 65b) are observed at the two ports, for the transient regime in figure 67. The pulse is quite well transmitted to the stripline; we observe also important oscillations at very high frequency indicating RLC cavity behaviour. The so-called S-parameters are shown in figure 68, indicating a quasi transmission of the signals. The simulator can handle such a complex structure.

Figure 66 : Electric field map, transient regime

Another point of interest is to study ground bounces induced par parasitic electromagnetic

waves. In figure 69 another configuration is presented: the same via but the striplines orthogonal. The difference appears essentially at the output port (see figure 70), compared to the striplines aligned (figure 67). In the aligned case, the system acts as a single short strip line: a negative reflected wave appears at the output, but in the orthogonal case, the negative


159

reflected wave does not appear. It does not seem interesting to bend more the structure (> 90°, until 180°), as the cross-talk will be enhanced.

Figure 67: Voltage at different probe points : excitation : pulse on Port0 (see figure 65b)

Figure 68: Transmission parameters : S12 and S21

Figure 69: System via and striplines bended at 90°


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Figure 70: Voltage at different probe points : excitation : pulse on Port0 (see figure 69)

6.12 Conclusion

Two technologies are proposed to implement the smart power integrated circuits. The first one is the planar integration using the deep trench isolation (DTI) technique, and the other one is the new stacked 3D-integration using through-silicon vias (TSVs).

In the first technology, an isolation mechanism, is suggested using a deep trench filled with

silicon dioxide and undoped polysilicon. The polysilicon has a nearly perfect conformal deposition, that is, both step coverage and bottom coverage are 100%. By using this kind of isolation technique, the injection collected ratio α is reduced by a factor between 3 and 8.5, and the dynamic variations of the currents and the voltages of the CMOS parts due to a (0/42V) signal can be tolerated under specific design rules. This isolation scheme is suitable for the automotive harsh environment. The OFF-state and ON-state characteristics are not changed with the use of the deep trench isolation.

Stacked 3D integration technique; which is the second proposed technology, offers

significant improvements over two-dimensional (2D) integrated circuits (ICs) on performance, functionality, and integration density. 3D integration promises a solution to the so called “wiring crisis” problem. This new 3D technology is used to stack the HV LDMOS devices and the low voltage digital and analog CMOS parts. Two and three-dimensional TCAD-based simulation of TSV or RDL induced coupling – is investigated on nMOSFET, pMOSFET, and the sensitive regions of the CMOS inverter. The impact of the TSV on the CMOS inverter operation is performed using mixed mode simulation (SPICE models for the CMOS devices and the finite element method (FEM) for the bulk regions of the devices).This impact is dependent on the layout and the position of the TSV.

On another hand, we begin to study for the sake of future studies on stacked devices in 3D

circuits, in the radiofrequency range, the propagation of electromagnetic waves along some interconnections with discontinuities. This study is done in the time domain: a Finite-Difference Time-Domain method is applied to the analysis of some via flanked by two striplines, all being embedded in silicon. Electric and magnetic field distributions, transmission and reflexion parameters, and pulse propagations along transverse via are presented. In this frequency range, inductive and thermal effects should be taken into account.

General Conclusions and Future work

General Conclusions and Furure work

162


163

7.1 General Conclusions Smart power integrated circuits (ICs), which monolithically integrate low-loss power

devices and control circuitry, have attracted much attention in wide variety of applications. These ICs improve the reliability, reduce the volume and weight, and increase the efficiency of a system. Considerable effort has been put into the development of smart power devices for automotive electronics, computer peripheral appliances, and portable equipments.

Commonly used smart power devices are the lateral double diffused MOS transistors (LDMOSFETs) implemented in bulk silicon or SOI (Silicon on Insulator). The main issues in the development of these devices are to obtain the best trade-off between specific ON-resistance RON,SP (RON × area), and breakdown voltage BV, and to shrink the feature size without degrading device characteristics. In conclusion, we would like to underline some contributions of this work in the field of designing smart power integrated circuits:

• New device structures with recently built novel device concepts are developed. The proposed devices are implemented in a 0.35µm BiCMOS technology, which is ST Microelectronics technology-like.

• A comprehensive study of the physical effects that take place in the HV devices is

done. The effect of the junction curvature on the breakdown voltage is explained. The factors that affect the safe operating area (SOA) of the device are discussed. Moreover, an analytical treatment of the REduced SURface Field (RESURF) principle is done.

• The intrinsic drain voltage concept (K-point voltage, VK) is proposed and its variation

is explained and related to the charge variation and the physical effects inside the device. The K-point voltage is used as a tool to investigate the saturation mechanisms of LDMOS. Once again, the correlation between the capacitances variation and the intrinsic drain voltage VK is demonstrated.

• The proposed LDMOSFETS are developed by slight modifications of the base

0.35µm BiCMOS technology. Extra two masks are used for the body and the drift regions formation with slightly added thermal budget and without resorting to high-tilt implants.

• The breakdown voltage of the proposed nLDMOS does not depend on the epitaxial

layer thickness as in the conventional RESURF LDMOS, so the proposed device is suitable for integration with low voltage CMOS with shallow epitaxial layers. A pLDMOS is designed in the same optimized epitaxial layer of the nLDMOS.

• The proposed devices are simulated with advanced TCAD tools to investigate the

physical phenomena and electrical characteristics. We have utilized commercial device simulators ISE and SENTAURUS-TCAD (GENESISe). The simulators provide facility for performing simulation in both 2D and 3D. The software gives a convenient framework to design, organize, and automatically run complete TCAD simulation projects. It provides a graphical user interface (GUI) to drive a variety of simulations, and visualization tools, and to automate the execution of fully parameterized projects.


164

• The modeling of the lateral structures came into play as these devices were integrated in standard technologies. Remarkable progress in the modeling field conducted to geometrical approximations for the drift zone (regional approach) seems to be the most promising approach.

• In the fifth chapter, a methodology for physically modeling the intrinsic MOS part and

the drift region is presented. The effects of velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel are considered. The analytical model is implemented using MATLAB and MAPLE programs. The electrical approximations that have to be taken into account to build the DC model are also explained.

• With the help of the proposed analytical model, a Spice model is developed. The

model parameters are extracted using a system that links the ICCAP extraction tool with the ISE-TCAD tools. An interface circuit is proposed, to convert low logic level voltage to high level voltage, suitable for the future automotive applications.

• An isolation mechanism, between the high voltage LDMOS devices as well as

between LDMOS devices and the low voltage CMOS is suggested using a deep trench filled with coating silicon dioxide and undoped polysilicon. Good electrical isolation is obtained using this kind of isolation technique. This mechanism is suitable in the automotive harsh environment.

• Stacked 3D integration technique, offers significant improvements over two-

dimensional (2D) integrated circuits (ICs) on performance, functionality, and integration density. 3D integration promises a solution to the so called “wiring crisis” problem. Furthermore, 3D integration also provides new architectures for sophisticated ICs and facilitates the integration of heterogeneous materials, devices. This new 3D technology is used to stack the HV LDMOS devices and the low voltage digital and analog CMOS parts.

• Two and three-dimensional TCAD-based simulation of TSV or RDL induced

coupling – is investigated on nMOSFET, pMOSFET, and the sensitive regions of the CMOS inverter. The impact of the TSV on the CMOS inverter operation is performed using mixed mode simulation (SPICE models for the CMOS devices and the finite element method (FEM) for the bulk regions of the devices).This impact is dependent on the layout and the position of the TSV.

• Three-dimensional simulation is preferred (with caution) in studying the substrate

coupling in the smart power integrated circuits specially when using the new 3D stacked integration technology as it can touch with a high degree the real case. But a lot of CPU running time is needed which can be compensated by using multi-processors computer with high memory. Moreover, in 3D, it is hard to visualize mesh obtuse angles, for instance; so, many trials should be needed to obtain a “good” solution.

• Stating that a whole Electro-Magnetic approach is a key goal in the very high

frequency domains, we apply a FDTD method (finite-difference time-domain) to two striplines separated by a via. Results of transient EM simulations have been analyzed


165

based on transmission/reflection coefficients, via FFTs which can be taken as post processing.

7.2 Future work

The work contained in this thesis naturally suggests continuations of researches and developments in some critical directions:

• This study may help the designers of the HV devices to produce high quality lateral MOS devices. The complete understanding of the effects specific to a HV device is the key to obtain an optimized design.

• Improving the thesis’s analytical model by including the special physical effects that

take place in the LDMOS device like accumulation layer injection.

• Studying the substrate coupling in the 3D stacked technology due to all types of signals, analog or digital (low voltage and high voltage).

• Developing a model of the substrate coupling and comparing the model results with

those obtained from the TCAD tools as well as future experiments for various integration schemes.

• A further study is planned in order to modify either TSV shape (square, hexagonal ...)

or configuration, to improve the overall performances of TSVs. As the TSV will not be used alone in an application, global chain (several levels of TSV, interconnect, bump, etc.) will be also simulated in order to provide guidelines in terms of connection.

• Taking the effects of inductive and thermal phenomena into account when developing

a model for the TSV-substrate coupling in the radio-frequency range.


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[4] M.Abou-elatta, C.Gontrand, A.Zekry, “cLDMOS in 0.35µm BiCMOS technology with Deep Trench Isolation suitable for Smart Power Integration”, Proc. JNRDM Montpellier, France, 7-9 June 2010.

[5] M.Abou-elatta, C.Gontrand, A.Zekry, “Complementary LDMOSFET in 0.35µm BiCMOS technology-characterisation and modeling”, IEEE Proc. International Symposium on Industrial Electronics (ISIE), pp. 736-741, Italy, 4-7 July 2010.

[6] M.Abou-elatta, C.Gontrand, A.Zekry, “Design of Complementary LDMOS in 0.35µm BiCMOS technology for Smart Power Automotive Applications”, European Journal of Applied Physics (EPJ AP), Accepted, 2010.

[7] C. Gontrand, O. Valorge, F. Calmon, J. Verdier, M. Abouelatta-Ebrahim, C. Andrei, J. Nunez –Perez, M. Lakhdara, S. Latreche and P. Dautriche, “Heterogeneous Circuits Insights through Substrate Coupling: Noises and Parasites”, Nova Science Publisher, Inc., Hauppauge, USA, 2010, in press.

[8] M.Abouelatta-Ebrahim, R. Dahmani, O. Valorge, F. Calmon and C.Gontrand, “Insights into 3-Dimensional Radiofrequency Circuits Connections”, Microelectronics Journal, 2010, in press.

FOLIO ADMINISTRATIF

THESE SOUTENUE DEVANT L'INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON

NOM : ABOU El –ATTA EBRAHIM DATE de SOUTENANCE : 17/12/10 (avec précision du nom de jeune fille, le cas échéant) Prénoms : Mohamed Titre : Intégration de composants de puissance LDMOS compatibles BiCMOS pour les systèmes Intelligents; couplages substrat. NATURE : Doctorat Numéro d'ordre : 2010-ISAL-O119 Ecole doctorale : EEA Spécialité : Dispositifs de l’Electronique Intégrée Cote B.I.U. - Lyon : T 50/210/19 / et bis CLASSE : RESUME: La technologie « Smart PIC (Power Integrated Circuits) » devrait avoir un impact sur tous les domaines dans lesquels des dispositifs semi-conducteurs de puissance discrets sont actuellement utilisés. Elle est censée créer des applications basées sur les nouvelles fonctionnalités de contrôle/commande intelligentes. Une meilleure étude des dispositifs haute tension (HT) et une compréhension claire des effets spéciaux sont alors nécessaires: effet de la courbure de jonction sur la tension de claquage, principe de réduction du champ en surface (RESURF),… Les dispositifs LDMOS (p et n) développés sont optimisés grâce à des outils avancés de TCAD. Ainsi, ces composants peuvent généralement être utilisés pour une tension d'alimentation de 42V, valeur adaptée aux applications futures de l'automobile. Ces dernières années, est apparue une technologie: l’intégration trois dimensions (3D). Cette dernière utilise des via traversant le silicium (Through-Silicon-Via: TSV) et des couches de redistribution (ReDistribution Layers: RDL), pour interconnecter plusieurs couches de circuits actifs, empilées. L'impact du TSV sur le fonctionnement de l’inverseur CMOS est mis en exergue en utilisant la simulation en mode mixte (modèles SPICE - lois nodales - pour les dispositifs CMOS et la méthode des éléments finis (MEF) pour les régions substrat de ces dispositifs. Finalement, nous initions une étude physique prospective sur les dispositifs empilés dans les circuits 3D, dans la gamme des radiofréquences; en l’occurrence, on scrute la propagation des ondes électromagnétiques le long de certaines interconnections pouvant présenter des discontinuités. Une méthode aux différences (FDTD: Time Domain Finite Differences) est appliquée à l'analyse de certains via, flanqués, par exemple, de deux « striplines », le tout enfoui dans le silicium. La distribution du champ électrique et magnétique, les paramètres de transmission et de réflexion, et la propagation des impulsions le long d’un via sont extraits. MOTS-CLES Smart Power, LDMOS, Simulation, TCAD, Circuits 2D et 3D -Via traversant (TSV) -, Démonstrateur Interface: 3,3V/42V. Laboratoire (s) de recherche : INL : UMR CNRS 5270 Directeur de thèse: Christian GONTRAND Président de jury : Catherine BRU Composition du jury : BRU Catherine, CALMON Francis, GONTRAND Christian, MILLAN Jose, SANCHEZ Jean-Louis, ZEKRY AbdelHalim, CHANTE Jean-Pierre (invite).

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Intégration de composants de puissance LDMOS compatibles …theses.insa-lyon.fr/publication/2010ISAL0119/these.pdf · 2016-01-11 · claquage (la jonction la plus sensible au fort