Introduction ToCMOS Image Sensor Design

2

CCD vs. CMOS

Charge-Coupled Device Image Sensor Higher Quality Lower Dark Current Lower Noise Higher Dynamic Range (because of higher VDD)

CMOS image sensor Easier to Integrate with Periphery Lower Power Dissipation Higher Speed (Higher Frame Rate)

3

Outline

Introduction Basic Architecture Photo-Sensing Operation Design Characteristics

Logarithmic Sensor High Dynamic-Range Sensor Digital Pixel Sensor (DPS)

4

Architecture Of CMOS Image Sensor

imagesensorarray

CDS(correlated double sampling)

Multiplexor

Analog-to-DigitalConverter

decoderand

controller

8-bit digital outputclock enable

pixel

5

Resolution

Resolution CIF (352x288 ~ 10 ), VGA (640x480 ~ 30 ) SVGA (800x600 ~ 48 ), XGA (1024x768 ~ 79 )

Typical pixel size 0.35 m process (7.5mx7.5m) 0.25 m process (5mx5m) 0.18 m process (3mx3m)

6

3-Transistor Sensor Cell

Operation of a cell (1) Reset (2) Integration

CDS

MUX

ADC

Con.

A sensor cell

reset

RS

columnline

sourcefollowerVDD VDD

RS: row select

photodiode

X

Iph

7

The Operation Of A Cell

XReset

Time1 ms

weak illumination

strongerillumination

Voltageat

node X

AB

CD

E

integration time

8

Photo-Electrical Characteristic

Illumination (Lux)

analogoutput

after CDS(volt)

1

1.2

1.4

1.6

1.8

2.0

Saturation region

5000 2500010000 20000150000

DR: Dynamic Range

Linearregion

9

Scanning Operation

CDS

MUX

ADC

Con.

Row 1

Row 2

Row 3

Last row

..

.

Integration time

Reset Signal For Each Row

10

Sensor Characteristics

Quality ofCMOS Image Sensor

ResolutionPixel TypePixel SizeFill Factor

ADC overhead

Q.E.(Quantum Efficiency)

Conversion Gain

Configuration Responsivity TransferFunction Noise

SensitivitySaturation LevelDynamic Range

Dark SignalTemporal noise

Fixed-Pattern Noise

11

Pixel Layout

PhotodiodePhotodiode

ResetReset

VddVdd OutputOutput

nn++

P-substrate is grounded

FOXFOX FOXFOX

A A

Reset-Ring isolates diode from FOX Helps reduce the dark current

Cross-Sectional ViewTop View

X

x

RSRS

12

Fill Factor

The ratio between the light sensitive pixel area and the total pixel area.

Total pixel area:5m x 5m

Fill factor 40%

PhotoSensing

Area

13

Signal Path: Light To Digital Code

reset

columnline

VDD VDD

X

n+n+

P-substrate

Light Source (Lux)

Electrons

Analog Voltage (V)

Digital Code (8-bit)

Quantum Efficiency(e- / photon)

Conversion Gain

Analog-To-Digital Conversion

RS

14

Sensor Characteristics

Quality ofCMOS Image Sensor

ResolutionPixel TypePixel SizeFill Factor

ADC overhead

Q.E.(Quantum Efficiency)

Conversion Gain

Configuration Responsivity TransferFunction Noise

SensitivitySaturation LevelDynamic Range

Dark SignalTemporal noise

Fixed-Pattern Noise

15

Sensitivity

V

Reset

Output

Tint Light intensity (lx)

Volta

ge D

rop

(V/s

)Slope = sensitivity

( V / lx-s)

Sensitivity is the ratio of voltage response to the photo energy illuminated.

16

Dark Current

Dark current is the photo-detector leakage current under no illumination.

Dark signalResetReset

OutputOutput

TTintint

nn++LOCOSLOCOS

pp--subsub

17

Noise of CMOS Imager

Temporal noise : Thermal noise ~ reset, readout. Shot noise, 1/f noise ~ integration. Substrate noise ~ readout.

Spatial noise : Fixed pattern noise ~ process non-uniformity.

18

Fixed-Pattern Noise

FPN is the spatial variations at pixel outputs Due to the device parameter variations (non-uniformity)

Pixel FPNPixel FPN Column FPNColumn FPN

19

Cell Array and CDS

reset

RS

CDS CDS CDS CDS

Column-parallel Correlated Double Sampling (CDS) Circuitry

20

CDS (Correlated Double Sampling)

Goal: To eliminate the Fixed-Pattern Noise (FPN) due to pixel mismatch

time

voltage

integration phaseReset

Vx

V = Vx Vreset V = 0 Vreset Vx

pixeloutput

CDSoutput

SH SEL

CLC2

C1 resetRSCLSH

vreset

21

CCD vs. CMOS

Charge-Coupled Device Image Sensor Higher Quality Lower Dark Current Lower Noise Higher Dynamic Range (because of higher VDD)

CMOS image sensor Easier to Integrate with Periphery Lower Power Dissipation Higher Speed (Higher Frame Rate)

22

Optimization of Transfer Curve

(Step 1) Logarithmic Output Response (Step 2) Dynamic Range Enhancement

Illumination (Lux)

Output(volt)

enhanceresponse

underlow-light

Illumination (Lux)

Output(volt)

23

Logarithmic Sensor (1/2)

24

Logarithmic Sensor (2/2)

Linear ADC multi-resolution ADC

25

Optimization Of Transfer Curve

(Step 1) Logarithmic Output Response (Step 2) Dynamic Range Enhancement

Illumination (Lux)

Output(volt)

enhanceresponse

underhigh-light

Illumination (Lux)

Output(volt)

higherdynamic

range

26

High Dynamic-Range Image

Original High-Dynamic-Range

27

Outline

Introduction Logarithmic Sensor

Logarithmic Sensor Cell Multi-Resolution ADC

High Dynamic-Range Sensor Digital Pixel Sensor (DPS)

28

Logarithmic Sensor Cell

columnline

photodiode

X

VDD VDD

Iph

Circled transistor is in sub-threshold region:

Vx = VDD ln (Iph/I0)

Main Problems:(1) mismatches harder to resolve(2) small output swing

29

Low-Cost Nearly Logarithmic Sensor

(1) Pixel-Level Logarithm much larger pixel(2) Chip-Level Logarithm via multi-resolution ADC

Illumination (Lux)

CDS output code

Illumination (Lux)

x =

outputcode

analog inputto ADC

255

30

Multi-Resolution ADC

Linear ADC

Multi-Resolution ADC

31

Spectrum of ADC

Speed

Accuracy

integrating

SuccessiveApproximation

Flash ADC,Pipelined ADC

8~10 bits

3 M-sample/s

32

The Problem of ADC

Digital Code0 1684 12

Input: Given an analog voltage, say 0.35Output: What is the digital output code?

Analog Voltage

0 V 1 V0.5 V0.25 V 0.75 V

0.35 V

33

Successive Approximation (SA)

Narrow down the possible code ranges step-by-step

0 V 1 V0.5 V0.25 V 0.75 V

0 V 1 V0.5 V0.25 V 0.75 V

0 V 1 V0.5 V0.25 V 0.75 V

0 V 1 V0.5 V0.25 V 0.75 V

Output bit

D3=0

D2=1

D1=0

D0=1

Final output code for 0.35 V is D3 D2 D1 D0 = 0101

pivot

pivot

pivot0.35

0.35

0.35

0.35

pivot

34

Naive Architecture

com-parator

10-bitDAC

S/H

clk

Vin

controllogic

10-bitSAR

clk

Linear ADC

10-bitcode

8-bit

10-bit

1024 x 8mapping

table

Table lookup

8-bitcode

AnalogPivot Voltage

35

Interleaved Architecture

com-parator

10-bitDAC

S/Hclk

Vin

controllogic

8-bitSAR

clk

256 x 10mapping

table8-bitcode

Advantages:(1) conversion time is reduced from 11 to 9 cycles(2) table size is reduced to ~ 1/4

8-bit

10-bit

36

Modified Successive Approximation

Digital Code

Analog Pivot Value012

6

345

7

0.5V (110)2

1st pivot

3rd pivot2nd pivot

8

1 V

0.5V

37

Chip Layout

CDSBuf

Periphery

Con-troller

176 x 144 SensorArray

ADCBIST

BIST: Built-In Self-Test

38

Outline

Introduction Logarithmic Sensor High Dynamic-Range Sensor

(1) Well Capacity Adjusting (2) Conditional Reset (3) Two-Frame Composition

Digital Pixel Sensor (DPS)

39

A High Dynamic-Range Sensor Cell

Vout

Ref: Steven Decker et. al., A 256x256 CMOS Imaging Array WithWide Dynamic Range Pixels and Column-Parallel Digital Output,

IEEE Journal of Solid-State Circuits, Vol. 33, No. 12, Dec. 1998.

ColumnlineVDD VDD

Iph

X

RS

ChargeSense

Diffusion

b(t)v1

High Dynamic Range is achieved by dynamic reset

40

Cross-Section View

n+ n+ n+ n+n+

photo-diode

chargespill gate

lateraloverflow gate

chargesense

Diffusion

VDD

rowselect

columnoutput

p-substrate

(1) Rest is now called lateral overflow gate(2) Another charge spill gate is added

41

Well Capacity Adjusting (WCA)

n+ n+ n+ n+n+ VDD

Cross-Section

0V

5V

potential

1V

b(t)

Spill gate

Overflowgate

drain

The well capacity at is controlled by b(t)

42

Transfer Function of WCA

Overflow barrier

time Light illumination

Charge atsense diffusion

x

time

b(t)

Control Signalb(t)

43

Outline

Introduction Logarithmic Sensor High Dynamic-Range Sensor

(1) Well Capacity Adjusting (2) Conditional Reset (3) Two-Frame Composition

Digital Pixel Sensor (DPS)

44

Conditional Reset

Ref: Sung-Hyun Yang, Kyoung-Rok Cho, High Dynamic Range CMOS Image Sensor with Conditional Reset. IEEE 2002.

High Dynamic Range was achieved by (1) Multiple Sampling (2) Conditional Reset

x

A pixel is reset again wheneverits value is lower than a referencevoltage at certain sample points.

x

45

A Sensor Cell with Conditional Reset

Light

VDD

RowSelect

C-Reset(Vsample > Vref)

ColumnLine

VDDPixel

Reset

The pixel is conditionally reset whenC-reset and Row-Select are both on

46

Extend Dynamic Range By N Times

T 2T 4T 8T

Integrationtime

I2I4I8I

PixelVoltage

1st 2nd 4th

3T 5T 6T 7T

Normal integration period is 8T

Information to be recorded: The first conditional reset.

3rd 5th 6th 8th7th

47

Examples: Pixel Response

Integrationtime

PixelVoltage

Integrationtime

PixelVoltage

Vref

Vref

T 2T 4T 8T3T 5T 6T 7T

T 2T 4T 8T3T 5T 6T 7T

Final output = (V1) * 8/2 = 4V1

V1

Final output = (V2) * 8/2 = 4V2

V2

48

Outline

Introduction Logarithmic Sensor High Dynamic-Range Sensor

(1) Well Capacity Adjusting (2) Conditional Reset (3) Two-Frame Composition

Digital Pixel Sensor (DPS)

49

Effect of Integration Time

Light intensity

Pixe

l out

put

Curve 1: (longer integration time)

Curve 2: (shorter integration time)

DR of curve 2

DR of curve 1

DR: dynamic range

50

Logarithmic Responses

Light intensity

Pixe

l out

put

Low-Frame

High-Frame

51

Two-Frame Composition

An Image is composed of two frames Low Frame (focuses on low-light part) High Frame (focuses high-light part)

Low-frame value x High-frame value y

+ =

Final value z

Sensitive to dark objectsAnd also responsive to bright objects

Sensitive to dark objects Responsive to bright object

52

Composition Rule

Low-frame value x High-frame value y

+ =

Final value z

Composition Rule y81x

87z +=

Low-frame hi0 255

Code Range Distribution

223

53

Composite Image

Ref: O. Schrey, J. Huppertz, G. Filimonovie, A. Bumann, W. Brockherde, B.J. Hosticka A 1k x 1k High Dynamic Range CMOS Image Sensor with on-chip Programmable Region-of-Interest readout. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 7, JULY 2002.

High-frameLow-frame Composed

54

Outline

Introduction Logarithmic Sensor High Dynamic-Range Sensor Digital Pixel Sensor (DPS)

55

Digital Pixel Sensor (DPS)

Granularity of ADC Chip Level Column Level Pixel Level, (I.e., one ADC per pixel)

Digital Pixel Sensor Digital Pixel Output Snap-shot image acquisition (High Speed) Scalable Lower Power Immune to the read-out noise (or column FPN)

ADC 8-bitmemory

Digital Pixel

DigitalOutput

56

Pixel Schematic for DPS

* 3.3V thick-oxidetransistors

storage

Stuart Kleinfelder, SukHwan Lim, Xinqiao Liu, and Abbas El Gamal, A 10000 Frames/sCMOS Digital Pixel Sensor, IEEE Journal of Solid-State, Vol. 36, pp. 2049-2059, Dec. 2001.

57

Low-Cost ADC

Counter value is loaded into memorywhen ramp meets pixel value

Pixel value

58

Operation Sequences

Reset Integrate ADC Read

Single Sampling:

Reset Integrate ADC Read

Digital Correlated Double Sampling:

ADC Read

Multiple Sampling (To Enhance Dynamic Range):

Reset Integrate ADC ReadADC ReadIntegrate

Integrate ADC ReadADC ReadIntegraten

59

Effect of Digital CDS

Fixed-Pattern Noise

Without Digital CDS With Digital CDS

The integration time is set to 1 ms

60

Characteristics Of A DPS Chip

nMOS Photo-GatePhoto-Detector

37No. of Transistors/Pixel

3.8 millionNumber of Transistors

64-bit (167MHz)Readout Architecture

> 1.33 GB/sMax Output Data Rate

> 10,000 frames/sMax. Frame Rate

15%Sensor Fill Factor

9.4 x 9.4 umPixel Size

> 1 G-pixels/sMax. Pixel Rate

352 x 288 pixels (CIF)Array Size

5x5 mmDie Size

0.18um 5-metal CMOSTechnology

61

Conclusions

CIS (CMOS Image Sensor) over CCD Ease of integration with periphery Lower power dissipation

CIS Optimization Just like human eyes Logarithmic Sensitivity High Dynamic Range (50dB 70dB 90dB) Low-Noise and High Speed via DPS