J. Schuderer, U. Drofenik, B. Agostini, F. Brem, F. Mohn ... - JuergenSchuderer_submitted... · © ABB Group November 14, 2013 | Slide 1 Challenges and new approaches for power module’s

ABB Group November 14, 2013 | Slide 1

Challenges and new approaches for power modules next generation packaging technology

J. Schuderer, U. Drofenik, B. Agostini, F. Brem, F. Mohn, F. Canales, ABB CHCRC, iMAPS Workshop, Nov 7, 2013

Challenges and new approaches for power modules Content

November 14, 2013 | Slide 2 ABB

MV power packages review

design

reliability issues & wear-out

robustness issues

New requirements & SiC system case study

Packaging research needs


MV power module design

MV power module design High power IGBT modules


IGBT insulated IGBT press pack

Traction and industrial drives applications

AlSiC baseplate, AlN DCB

Isolation up to 10.2kVrms

1.7 - 6.5kV, up to 3600A

Other modules up to 1.7kV: EconoPak,

PrimePack, SkiM, SkiiP,

Transmission & distribution applications with

series connections & redundancy

Individual spring contacts for uniform pressure

Short-circuit failure mode (SCFM) capability

2.5 and 4.5kV, up to 2000A

Other press packs: IGBT capsules

MV power module design Thyristor press packs (bipolar discrete)


Discrete bipolar devices (Thyristors, Diodes)

remain the most economic solution for many

high-power applications (T&D, industry)

Available up to 8.5kV and up to 6.1kA for 6

devices

Press Pack design features

pressure loaded (~15MPa) dry & bonded

contacts with Mo strain buffers

double-side cooling

inherent SCFM

hermetic housing

low-inductance gate connection (IGCT)

clearance and creepage distances up to

10kV


Power package reliability issues

Power package reliability issues Introduction


Reliability issues: Wear-out and degradation at the end of the

hazard function bathtub curve

General root cause for power package wear-out (ever present

power electronic stressors):

temperature cycling

high temperature storage

Review of

wear-out failure mode

wear-out failure mechanism

typical lifetime values

demonstrated and proposed improvement strategies

Note: references are documented at the end of the presentation.

Review on power package failure mechanisms Chip-related wear-out under thermal cycling


Failure mode Illustration Mechanisms Typ. values Improvements Illustration

Wirebond lift-off

& heel crack

Bond wire fracture or

lift-off due to wire

flexural fatigue and

themomechanical

(TM) stress

Nf = 100k,

Tcycle = 40-

100C,

tcycle = 5s [2]

- Polymeric coating

- Ribbon

- Cu & Al coated Cu

- Metal foil buffer

- Mo top plate

- Cu clips & flex foil

- Galvanic Cu

Die attach

fatigue

TM stress/strain field

during cycling

solder fracture &

delamination

Nf = 60k,

Tcycle = 40-

100C,

tcycle = 60s [2]

- x 10-100 DT =60C

for LTB [4]

- x 10-100 DT = 60C

for TLP [4]

- Au/Ge, /Si, /Sn [5]

Al metallization

reconstruction

Al/Si CTE mismatch

stress beyond

elastic limits Al

gets porous (grain

bound. deformation)

increase in losses

Tj >> 110C [1],

2.5 x resistivity

increase after

50k pulses,

5ms, 250A/cm2

[7]

- Ni coating [6]

- Polyimide [1]

- Mechanically

stronger

metallization

Dry contact

fretting corrosion

(Thyristor)

Al/Mo resistance incr.

by breaking oxide

films hot spots,

current filamentation

& breakdown

Nf = 50k,

Tcycle = 30 -

120C

tcycle = 5s

- Surface plating and

interface materials

(Rh, Ro, Ag, )

- Wafer bonding

(LTB, Si/Al brazing)

[6] [6]

[3]

[1]

Review on power package failure mechanisms Substrate-related wear-out under thermal cycling


Failure mode Illustration Mechanisms Typ. values Improvements Illustration

Substrate bond

large area solder

crack and fatigue

Same mechanism as

die attach (can be

more stress due to

larger lateral

dimension)

Nf = 30k,

Tcycle = 20-

80C,

tcycle > 1h [2]

- Avoid too thin

solder by spacers

- SnSb solder

(solid sol. str.),

- SAC solders

(precipitation str.)

Substrate & chip

brittle crack

- High TM stress ind.

chip & substr. cracks

breakdown, lift-off

- Cracks below US

welding of terminals

Nf = 500,

-50 190C

DBC AlN/Cu [8]

Si3N4 DBC superior

to AlN and Al2O3 [8]

Power terminal

lift-off

CTE mismatch and

pull-force lead to

terminal solder crack &

delamination

(Not known to

authors)

- Stress relief

(flexible terminal)

- Ultrasonic

welding

TIM dry-out and

pump-out

Polymer matrix gets

fluid at high-T, filler

remains (dry-out),

TIM pushed out by

thermal movements

(pump-out)

(Not known to

authors)

Optimized bow,

gels, foils, pre-

applied phase

change materials,

carbons, liquid

metal, integr. cooler

Sn5Sb

2000 cycles,

-50 190C

[8] [8]

[9]


Power package robustness issues

Power package robustness issues Introduction


Robustness issues: Issues due to insufficient margin against

stresses under various operation conditions.

Considered root causes for package robustness failure

voltage loads & field stresses

switching transients

surge currents

Review of

failure mechanism

typical withstand value

demonstrated and proposed improvement strategies

Review on power package robustness issues Insulation


Issue Illustration Mechanisms Typ. values Improvements Illustration

Partial

discharges at

substrate

metallization

edges

Surface discharges

along gel interfaces &

internal discharges in

voids

10.2/6.9/5.1kV

test for traction

applications

(6.5kV IGBT)

- High-strength layer

- Field grading (cap.,

res., nonlinear) [11]

- Etching of braze

protrusions

JT insulation &

interface leakage

currents

- Humidity enhanced

JT degradation

(oxidation, charges,

delamination) [12]

- Insufficient JT

cooling for Thyristor

- 6.5kV,

~1.5mm

- 8.5kV PCT,

~2mm

Passivation layers to

saturate dangling

bonds and to drain

trapped charges

(SIPOS, DLC)

High-T

encapsulation

withstand

Gel degradation,

ruptures and integrity

(hardness, oxidation,

weight loss)

Silicone gel:

~175C

- New gels up to

225C [13]

- Tg > 250C mold

compounds [14]

- Conformal coatings

(eg., Parylene, PI)

[12]

[14]

[11] [10]

Review on power package robustness issues Switching transients


Issue Illustration Mechanisms Values Improvements Illustration

Induced over-

voltages &

ringing by

commutation

loop stray

inductance

= leads to device over-voltages

( de-rating) and to

resonances ( EMC

issues & losses)

2D layouts

today:

Ls = 10-

50nH

- Snubbers & RC/RL

damping of oscil.

- Parallel commutation

cells (HBs) with strip-

line interconnections

- SoC, SiP, chip in

polymer & 3D

integration, eg. [15]

Uneven

current

sharing

Losses, asynchron. &

oscillations by induced

voltage noise on gate

due to cross coupling

and imbalance due to

impedance mismatch

2D layouts

today:

~ 1V/nHGE

per 1kA/ms

- Auxiliary emitter

- Symmetric substrate

impedance, busbar,

and terminal design

- Low-Ls strip-line gate

& power circuit [18]

Unwanted

leakage

currents by

dU/dt

= leads to EMC compliance issues and

leakage losses

2D layouts

today:

~ 10V/ns

- Low-permittivity

insulation

- 3D concepts with

minimum footprint

[17]

[16]

[19]

[18] ctrl

pwr

Review on power package robustness issues Surge current and end-of-life


Issue Illustration Mechanisms Typ. Values Improvements Illustration

Surge current

(device active

over-current

in fwd direct.)

Device metal. & w/b

over-heating by

inrush currents, fault

currents and short-

term operation points

HiPak IGBT

x 8 In, 10ms

StakPak IGBT:

x 16 In, 10ms

Thyristor:

x 15 In, 10ms

- IGBT: Thick metal.,

Cu w/b, planar

emitter contacts

with improved Zth - Thyristor: Improved

Zth via bonding

EoL SCFM

(device failed,

needs to

support Inom

for series

connections)

Wirebond melting,

evaporation & arcing

Blocking failure of

wirebonded 100A

chip leads to arcing

at ~1kA, 10ms

- IGBT: StakPak

SCFM formation,

2kA: 10 ms, ~10J,

~0.1mW

- Thyristor: Low

ohmic SC (liquid Si

channel) [22]

EoL

explosion

withstand of

over-currents

(eg. parallel

connections)

Massive local over-

current in blocking

direction leads to

device evaporation,

arcing & explosion.

- IGBT StakPak:

x 20 In, 10ms

- Thyristor:

> x 10 In, 10ms

- Pressure contacts

- External explosion

proof boxes [24]

- Arc protection by

package internal

shields (Thyristor)

- Fuses

Al

Mo

Si

Pb

[20] [21]

[23]

[24]


New requirements and power module implications

New requirements & power module implications Trends towards higher package performance


Higher current & loss density

Reduce costs, weight & volume

Higher switching transients

WBG devices

Shrink magnetics by higher switching frequency

Higher package E-field stresses

WBG devices with up to 10 x critical field (SiC)

Shrinked packages for low parasitics and reduced costs

Higher load cycle reliability

Exploit max. Tj for load-cycle intensive applications (eg, traction)

WBG high-T operation

Higher surge and EoL withstand

Increasing power ratings in T&D

Withstand against new environmental stressors

New applications off-shore, outdoor, on-vehicle, subsea, etc.

0

100

200

300

400

500

600

Si SiC 1/4

Module cost

Cooler cost

New requirements & power module implications SiC cases study: f varied, Tj = 120C


1kV, 200kW, 3p-2L inverter optimized for cost & efficiency under

variation of package design (chip area, # chips, # substrates,

heat sink) by statistical optimization approach.

For the given converter system, SiC costs need to drop by factor

~4 to a cost/mm2 ratio of SiC/Si ~13 (switch) and ~7 (diode) to

reach cost parity at 20kHz (w/o any shrinked magnetics!).

Efficiency will be 2% pts higher, heatsink volume/cost will be

3 x lower, and reliability will be similar (Tj = 120C).

0

1

2

3

4

5

6

7

8

9

10

0 5 10 15 20 25

Co

nve

rte

r c

ost

rati

o S

iC/S

i

f [kHz]

SiC cost today

SiC cost 1/4

97

97.5

98

98.5

99

99.5

100

0 5 10 15 20 25

Eff

icie

nc

y [%

]

f [kHz]

Si

SiC

0

5

10

15

20

25

30

35

0 5 10 15 20 25

He

at

sin

k v

olu

me

[d

m3

]

f [kHz]

Si

SiC

f = 20kHz

material cost only

25%

of

Si are

a

New requirements & power module implications SiC case study: Tj varied, f = 16kHz


SiC operational cost & volume benefit saturate at Tj ~ 150-180C

(since SiC efficiency also drops with Tj)

3 x lower cooler volume and 2% higher efficiency pts. stay constant

across the investigated Tj range.

But - reliability drops by factor 50 by changing from Tj = 120 to 180C.

For the given converter system, high-T operation > 200C is not

recommended for the MOSFET (SiC bipolar devices might perform

differently).

97

97.5

98

98.5

99

99.5

100

50 100 150 200

Eff

icie

nc

y [%

]

Tj [C]

Si

SiC

0

10

20

30

40

50

60

50 100 150 200

He

ats

ink

vo

lum

e [d

m3

]

Tj [C]

Si

SiC

0

0.2

0.4

0.6

0.8

1

50 100 150 200

Ma

teri

al &

1y

r o

pe

r. c

ost

SiC

/Si

Tj [C]

SiC cost today

SiC cost 1/4

material + 1yr cost of energy


Conclusions: Packaging research needs

Challenges and new approaches for power modules Research needs

Confidential ABB Group 27 Feb 2013

Si IGBT Power Module Si Thyristor Press Pack SiC Packages

Bonding: TLP process

robustness & large area

bonding, LTB low cost

approaches & further

reduced p & T

6-inch devices: Large area

bonding, symmetric current

distribution, low-inductance

gate control

Resonances: technology to

damp and synchronize critical

resonances & transients

Topside: Planar emitter

bond & metallization for

improved reliability,

surge current & cooling;

improved JT passivation

Dry contacts: Fretting

corrosion lifetime models

and optimization of

materials & platings

Encapsulation materials

and coatings for Tj = 175 -

200C

Topside SCFM: Low-

cost emitter contact /

IGBT module with SCFM

capability

Low-cost: Plastic housings

in combination with novel

passivation and planar JT

approaches

Hard switching: 3D integr.

designs & materials for

conflicting requirements on

Ls, Cs, insulation, current

capability, cooling, reliability

and low-cost assembly.

Co

nti

nu

ou

s

imp

rove

me

nt

Inn

ova

tio

n,

bre

ak

thro

ug

h

Challenges and new approaches for power modules Acknowledgements


Chunlei Liu

Didier Cottet

Gernot Riedel

Slavo Kicin

Samuel Hartmann

Challenges and new approaches for power modules References

[1] M. Ciappa, Selected failure mechanisms of

modern power modules, Microelectronics

Reliability 42 (2002) 653667.

[2] ABB Application Note, Load-cycling

capability of HiPakTM IGBT modules.

[3] FP. McCluskey Failure Mechanisms in

Power Electronics, March 2013.

[4] K. Guth et al, New assembly and

interconnect technologies for power modules,

CIPS 2012.

[5] A. Schletz,Die attach for SiC devices

operated at elevated temperature, ISiCPEAW

2011.

[6] T. Nishimura et al, Improving Reliability of

IGBT Surface Electrode for High Tj Operation,

ISPSD2011.

[7] E. Marcault et al, Impact of source

metallization ageing on thermo-mechanical

characteristics of a vertical smart power device,

ISPSD2011.

[8] S. Kicin, Assessment of selected materials

and assembly technologies for power electronics

modules with the capability to operate at high

temperatures, EPE'13 ECCE Europe.

[9] Bergquist GapPad.

[10] JH. Fabian et al, Analysis of Insulation

Failure Modes in High Power IGBT Modules,

Industry Applications Conference, 2005.

[11] L. Donzel et al, Nonlinear Resistive Electric

Field Control for Power Electronic Modules,

IEEE Trans. on Diel. and Electrical Insul., Vol.

19, pp. 955-959, 2012.

[12] C. Zorn et al, Feuchtetest mit hoher

Spannungsbelastung an Halbleitermodulen,

41. Halbleiter-Kolloquium, Freiburg,

30.10.2012.

[13] Gel supplier roadmap information.

[14] KF. Becker Polymere fr das Packaging

bei erhhten Temperaturen, SMT 2010

Tutorial.

[15] eg., JP. PopoviGerber, Integration-driven enhanced packaging, ECPE Tutorial

Power Electronics Packaging, March 2013.

[16] E. Hoehne, Ultra Low Inductance

Package for SiC & GaN, ECPE SiC and GaN

Forum 2013 Munich.

[17] Infineon "Blade" packaging technology.

[18] adapted from R. Bayerer, Future Module

Concepts: Contruction and Internal Parasitics,

ECPE Workshop Future Trends for Power

Semiconductors, 27.01.2012.

[19] T. Daj, "Real-time degradation monitoring

and lifetime estimation of 3D integratedbond-

wire-less double-sided cooled power switch

technologies, EPE'13 ECCE Europe.

[20] U Scheuermann, Failure Mechanisms,

ECPE Tutorial Power Electronic Packaging,

March 2013.

[21] T. Stockmeier et al, SKiN: Double side

sintering technology for new packages,

ISPSD 2011.

[22] Patent US 6,426,561 B1.

[23] S Gunturi et al, Innovative Metal

System for IGBT Press Pack Modules,

ISPSD, April 2003.

[24] M Billmann, Explosion Proof Housings

for Wire Bonded IGBT Modules in HVDC

application, ECPE Workshop Advanced

Multilevel Converter Systems, 2010.

[25] JP. PopoviGerber, Packaging Materials, ECPE Tutorial Power Electronics

Packaging, March 2013.

[26] http://www.coolpolymers.com.

[27] http://www.electronics-

cooling.com/2003/05/an-introduction-to-

pulsating-heat-pipes/.

[28] Parker, Two-Phase Evaporative

Precision Cooling Systems.

[29] http://www.electronics-

cooling.com/2005/11/advances-in-high-

performance-cooling-for-electronics/.

[30] IBM, http://www.zurich.ibm.com/st/

cooling/convective.html.

[31] Immersion cooling with 3M Novec fluids,

http://spark.3m.com/blog/?p=1422.

[32] Danfoss ShowerPower.

[33] JW. Kolar et al, "Influence of the

Modulation Method on the Conduction and

Switching Losses of a PWM Converter

System", IEEE Trans. on Industry Applicat.,

vol.27, no.6, pp.1063-1075, 1991.


Documents

J. Schuderer, U. Drofenik, B. Agostini, F. Brem, F. Mohn ... - JuergenSchuderer_submitted... · © ABB Group November 14, 2013 | Slide 1 Challenges and new approaches for power module’s