11 8-4 Enabling Shallow Trench Isolation for O.lpm Technologies and Beyond

C.-P. Chang, S.F. Shive*, S.C. Kuehne", Y. Ma', H . Vuong, F.H. Baumann, M. Bude, E.J. Lloyd, C.S. Pai, M.A. Abdelgadi?, R.Dail*, C.T. Llu, K.P. Cheung, J.I. Colonell, W.Y.C. Lai, J.F. Miner, H . Vaidya', R.C. Liu, J.T. Clemens

Bell Laboratories, Lucenl Technologies, 600 Mounlain Ave., Murray Hill NJ 07974 "Bell Laboratories, Lucent Technologies, 9333 S. John Young Parkway, Orlando FL 32819

Introduction Shallow trench isolation (STI) has become the standard isolation structure for submicron silicon CMOS technologies [1,2]. However, following the trend of device scaling, the isolation for future generations will have minimum width of about 130nm for 0.lpm technologies and l00nm for 0.07pm technologies (Fig. 1). It is highly desirable to extend the current STI stmcture [3], widely adapted in manufacturing, to those dimensions, hut many issues become difficult to resolve. In this work, we will show that with a novel enabler - high temperature re-oxidation (HTR) for comer rounding [4] and by properly addressing the issues of trench fill, comer profiles, tub implants, channel width loss, reverse narrow channel effect (KNCE). defect density and junction leakage, the basic STI stmcture can he extended to O.lpm and beyond.

Trench Fill and Aspect Ratio Considering the implication on channel doping profiles, trench depth of 2200nm is still expected in the future, despite the downward trend of supply voltage and junction depth. With increasing aspect ratio (AR), the trench fill becomes challenging, even for highdensity plasma (HDP) oxide. Higher sputter-to-deposit ratio HDP oxide provides better trench fill capability, hut it also facets nitride, the CMP (chemical-mechanical polishing) stop (Fig. 2a). An optimized, multi-step deposition can fill trenches of AR up to 4.0 (3.6 for consistent fill without any weak spots) with nitride facet c20nm in open trenches (Fig. 2b and 2c). For future-generation isolation, the presence of liner oxide (oxidation of trench surfaces before trench fill) has a large impact on aspect ratio (Fig. 3). Therefore, the need for trench fill dictates that only minimal liner oxide may he allowed.

Corner Profiles Trench-comer rounding is one of the most critical aspects of isolation design. Liner oxidation is often not effective, even with sufficient thickness (230nm). Liner oxidation at 11000°C produces facets with overhang, while higher temperature (1 150%) oxidation produces large facets, oxide pinch-off at hottom comers (Si 4 1 I>) and thicker sidewall oxide (4 IO>), which makes trench fill more difficult (Fig. 4). Liner oxidation is also used to repair damage due to trench etching and provide buffer for HDP (Fig. sa). However, an HTR step [4] provides all the solutions: rounding top comers without affecting bottom comers, repairing silicon damage from previous steps and densification of the HDP oxide. Figure 5h shows the TEM of a trench without liner oxidation hut with 1100°C HTR after STI CMP.

Channel Width and RNCE Although the loss of channel width (delta-W) from processing can he in principle compensated by lithography, the difficulty in printing narrower openings makes it impractical. Therefore, it is also critical to keep de1ta-W small for future- generation isolation. The combination of HTK and minimal or no liner oxidation can achieve that goal (Fig. 6). The most important reason for corner rounding is to suppress RNCE.

This is achieved with HTR regardless of the amount of liner oxidation, and in fact, thinner liner oxide is slightly better (Fig. 7). The reason for RNCE suppression is evident in Figure 8, showing comer rounding and thicker comer oxide with HTR.

Retrograde Tub Implant With resist thickness > I Spm (needed for high-energy implant) and shrinking n+/p+ separation, 0-degree implants are essential for retrograde tubs. However, depending on wafer size and implanter, the implant angle actually varies across the wafer, up to 1 2 degrees. The key is to reduce channeling at 0-degree with sufficiently thick screen oxide to maintain uniform tub doping profiles across the wafer. For boron (p-tub), a screen oxide of 5nm is sufficient. However, Figure 9 shows the differences in n-tub doping profiles between 0-degree and 2-degree implants, and screen oxide 12nm is required for acceptable variability.

Defect Density and Junction Leakage It was widely reported that STI process, depending on thermal cycles, trench-fill material, aspect ratio and sidewall profiles, may induce silicon defects, degrade gate oxide and cause high junction leakage [5,6]. This issue will be even more critical in the future due to higher stress observed with narrower trenches [7]. We studied the trend of various parameters and found that higher-temperature, thicker sacrificiallscreen oxide has a positive impact on defect density and TDDB, regardless ofthermal cycles (Fig. 10). In terms ofjunction leakage, STI with liner oxide is more robust, hut the presence of dichlorethylene (DCE) in HTR process keeps junction leakage under control even without liner oxide (Fig. I I ) , possibly by reducing stress during re-oxidation. Although isolation voltage degrades slightly with decreasing trench depth, the junction leakage is not affected (Fig. 12).

Conclusion With HTR, the current STI structure can he extended to 0.lpm technologies and beyond (Fig. 13). A set of reasonable parameters will he 200 - 300nm trench depth, 0 - 5nm liner oxide, HDP oxide, HTR (with DCE) producing ,30nm rounding and sacrificiallscreen oxide 212nm.

Acknowledgment We would like to thank the personnel of Murray Hill and Orlando facilities for wafer processing and characterizations, especially C.B. Case, F.P. Klemens, J. Frackoviak, A. Timko, L. Trimhle, M. Oh, J. Liu, G. Gibson, A. Maury, M. Baker, W. Mansfield and J.T.C. Lee.

References [I] A.H. Perera et al., IEDM Tech. Digest, p. 679 (1995) [2] A. Chatterjee et al., Sym. on VLSI Tech., p. 156 (1996) [3] M. Nandakumaret al., IEDM Tech. Digest, p. 133 (1998) [4] C.4' Chang et al., IEDM Tech. Digest, p. 661 (1997) [ 5 ] I. Damiano et al., Sym. on VLSI Tech., p. 212 (1998) [6] T.-K. Kim et al., IEDM Tech. Digest, p. 145 (1998) [7] T. Kuroi et al., IEDM Tech. Digest, p. 141 (1998) [8] G. Hohler, Nucl. Instr. Meth. 896, p. 155 (1995)

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