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デザイン例デザイン例 は、アルテラ製品にすぐに使用できる HDL コード・サンプルです。提供されているデザイン例には、C コードと SOPC Builder を使用するエンベデッド・プロセッサ・デザイン、VHDL あるいは Verilog を使用したデジタル・シグナル・プロセシング（DSP）、 インタフェース・プロトコル、および外部メモリ・インタフェースのデザインが含まれています。 デザイン・エントリー/ツール例 は、デザイン・エントリー・プロセスを支援します。デザイン・エントリー/ツール例には、基本ロジック・ブロック、スクリプティング、ゲート・レベル・タ イミング・シミュレーション・ツール、およびデバッグのインスタンス作成のサンプルが含まれています。また、Quartus® Prime のファンクション例も提供しています。各種デザイン・エントリー手法の詳細情報は、Quartus Prime 開発ソフトウェア内のヘルプ・ファイルをご覧ください。 MAX 10 FPGA デバイス・ファミリー向けのデザイン例および開発キットは、新しい Design Store で提供しています。

All Design Examples• All Design Examples • DSP • Embedded Processors • Interface Protocols • External Memory Interfaces • Peripherals • Verification • SoC Design Examples

Product Name Ordering Code

Documentation URL Product URL

PCI Target Memory Example for PCI MegaCore Functions - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-pci-target-memory.html

PCI Target Termination Examples for pci_mt32 and pci_t32 MegaCore Functions - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-pci-target-retry.html

Verilog HDL: Interfacing 400-MHz QDR II+ SRAM in a Stratix IV FPGA

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-

Product Name Ordering Code

Documentation URL Product URL

stratix-iv-18-bit-qdrii-uniphy.html

Implementing OFDM Modulation and Demodulation - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/vhdl/vhd-cyclic-prefix-insertion-ofdm.html

Achieving Unity Gain in Block-Floating-Point IFFT+FFT Pair - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-cascaded-fft-ifft.html

POS-PHY Level 4 (SPI-4.2) External PLL Sharing Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-external-pll-merging.html

Verilog: FFT With 32K-Point Transform Length - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-fft-32k.html

Verilog: Coefficients Reload Design Example for FIR Compiler - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-fir-coefficient.html

PCI Master Memory Example for pci_mt32 MegaCore Function - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-pci-master-memory.html

HiSPi Imager Connectivity Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/exm-hispi.html

RapidIO: Customized Implementation using Avalon-ST Pass-Through Interface - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/exm-avalon-st-interface.html

TSE: Instantiate TSE with External ALTGX / ALTLVDSexm-instantiate-tse-altgx-altlvds

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/exm-

Product Name Ordering Code

Documentation URL Product URL

instantiate-tse-altgx-altlvds.html

Multi-channel Farrow Filter Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-farrow-filter.html

Polyphase Modulation With Aliasing for Data Up-Conversion - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-polyphase-modulation.html

Reconfigurable Decimation Filter Design Example Using DSP Builder Advanced Blockset

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-reconfigurable-decimation-filter.html

Run-Time Reconfigurable Scaler Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-scaler-vip.html

Sigma-Delta Converter - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-sigma-delta-converter.html

Variable Integer Rate Decimation Filter Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-variable-rate-decimator.html

Memory Test - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/exm-c-memory.html

RapidIO: Maintenance Master to System Maintenance Slave Bridge - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/exm-master-slave-bridge.html

Constraint RGMII Interface of Triple Speed Ethernet with the External PHY Delay Feature

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/exm-tse-

Product Name Ordering Code

Documentation URL Product URL

rgmii-phy.html

TSE: Implement Reset Sequence in TSE Using ALTGX as Transceiver - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/imp-reset-seq-in-tse-altgx.html

Accelerated FIR with Built-In Direct Memory Access Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-accelerated-fir.html

Altia Red Touch Screen HMI for D/AVE - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-altia-demo.html

Avalon Memory-Mapped Master Templates - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html

Board Diagnostic - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-board_diagnostic.html

Checksum Hardware Accelerator Design Example

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-checksum-

Product Name Ordering Code

Documentation URL Product URL

acc.html

Nios II CRC Acceleration Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-crc-acceleration.html

Nios II Custom Instruction Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-custom-instruction.html

Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-debug-signaltap.html

Debugging with System Console over TCP/IP (SCTCP) Design Example

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-debug-sys-console-tcpip.html

Product Name Ordering Code

Documentation URL Product URL

Application Selector Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-demo-loader.html

HAL Device Drivers Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-developing-hal-drivers.html

Nios II Ethernet Acceleration Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-ethernet-acceleration.html

Fast Nios II Hardware Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-fast_nios2_hardware.html

Hello MicroC/OS-II - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-hello_micro.html

Nios II High-Performance Example with Bridges

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/

Product Name Ordering Code

Documentation URL Product URL

embedded/nios-ii/exm-high-perf-bridge.html

IMAGEM Technology Solution Demos - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-imagem-taquin-game.html

Using CIC Decimation Filter with Multi-channel Support - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-cic-decimation-filter.html

CIC Interpolation Filter with Multi-Channel Data Support - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-cic-filter.html

Designing Digital Down Conversion SystemsUsing CIC and FIR Filters - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-digital-down-conv-cic-fir.html

SPI Slave to Avalon Master Bridge Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-spi-bridge.html

D/AVE Graphics Accelerator Demo From TES - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-tes-demo.html

Using Tightly Coupled Memory with Nios II Processor

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-tightly-coupled-

mem.html

Triple Speed Ethernet Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-tse-sgdma.html

Using NicheStack TCP/IP Stack – Nios II Edition - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-using-nichestack.html

Vectored Interrupt Controller - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-vectored-interrupt-controller.html

Micriµm µC/GUI Demo - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-micrium-uc_gui.html

MicroC/OS-II RTOS with the Nios II Processor

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/

embedded/nios-ii/exm-microc-osii-tutorial.html

MicroC/OS-II Mutex Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-micro_mutex.html

Nios II Processor with Memory Management Unit Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-mmu.html

Nios II Multiprocessor Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-multi-nios2-hardware.html

Nios II Ethernet Standard Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-net-std-de.html

Nios II 3C120 Microprocessor System with LCD Controller

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-

examples/intellectual-property/embedded/nios-ii/exm-nios-lcd-3c120.html

Nios II 3C25 Microprocessor System with LCD Controller - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-nios-lcd-3c25.html

Memory Protection Unit (MPU) - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-niosii-mpu.html

Network Time Protocol Client Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-ntp.html

Profiling Nios II Systems Design Example - - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-profiling-de.html

Avalon Verification IP Suite Design Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/simulation/exm-avalon-verification-ip.html

Nios II 低消費電力デザイン例 - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-low-power-nios2.html

Nios II コンパクト・コンフィギュレー ション・デザイン例 - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-nios-compact.html

Nios II エンベデッド・プロセッサ・デ ザインのシミュレーション - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-simulating-niosii.html

プラネットウェブの SpectraWorks GUI のデモ - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-planetweb-spectraworks.html

Web サーバーのデザイン例 - - /content/altera-www/global/ja_jp/index/support/support-resources/design-

examples/intellectual-property/embedded/nios-ii/exm-micro_tutorial.html

MicroC/OS-II メッセージ･ボックス - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-micro_msgbox.html

Nios II システム・アーキテクチャ・デ ザイン - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-system-architect.html

シンプル･ソケット･サーバのデザイン例 - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-hello_world.html

プラネットウェブの SpectraWorks Digital Photo Frame

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-planetweb-photoframe.html

カウント・バイナリ - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-hello_free.html

Nios II ハードウェア開発デザイン例 - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-hardware-tutorial.html

C2H コンパイラのマンデルブロー・デ ザイン例

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-c2h-mandelbrot.html

NiosII ブート方法の応用 - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-alt-boot-methods.html

リード・オンリー Zip ファイル・システ ム - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/exm-c-readonly.html

Verilog HDL: Microcontroller I/O Expander - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver_microcontroller-io_expander.html

Product Name Ordering Code

Documentation URL Product URL

プロバイダー

Provider URL

Supported

Implementing OFDM Modulation and Demodulation

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/vhdl/vhd-cyclic-prefix-insertion-ofdm.html

Altera - -

Achieving Unity Gain in Block-Floating-Point IFFT+FFT Pair

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-cascaded-fft-ifft.html

Altera - -

Verilog: FFT With 32K-Point Transform Length

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-

Altera - -

Product Name Ordering Code

Documentation URL Product URL

プロバイダー

Provider URL

Supported

fft-32k.html

Verilog: Coefficients Reload Design Example for FIR Compiler

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-fir-coefficient.html

Altera - -

Multi-channel Farrow Filter Design Example

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-farrow-filter.html

Altera - -

Polyphase Modulation With Aliasing for Data Up-Conversion

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-polyphase-modulation.html

Altera - -

Reconfigurable Decimation Filter Design Example Using DSP Builder Advanced Blockset

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-reconfigurable-decimation-filter.html

Altera - -

Run-Time Reconfigurable Scaler Design Example

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-scaler-vip.html

Altera - Stratix II, Cyclone II

Sigma-Delta Converter - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-sigma-delta-converter.html

Altera - -

Variable Integer Rate Decimation Filter Design Example

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-variable-rate-decimator.html

Altera - -

Accelerated FIR with Built-In Direct Memory Access Example

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-accelerated-fir.html

Altera - Cyclone III, Stratix II

Product Name Ordering Code

Documentation URL Product URL

プロバイダー

Provider URL

Supported

Checksum Hardware Accelerator Design Example

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-checksum-acc.html

Altera - Cyclone III

Using CIC Decimation Filter with Multi-channel Support

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/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-cic-decimation-filter.html

Altera - -

CIC Interpolation Filter with Multi-Channel Data Support

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-cic-filter.html

Altera - -

Designing Digital Down Conversion SystemsUsing CIC and FIR Filters

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/dsp/exm-digital-down-conv-cic-fir.html

Altera - -

C2H コンパイラの マンデルブロー・デザイン例

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-c2h-mandelbrot.html

Altera - Cyclone III

Error Detection/Correction

Design ExamplesDevice

Targeted Development Kits Supported Qsys Compliant

Quartus II Version

Nios II: Checksum Hardware Accelerator

Cyclone III Nios II Embedded Evaluation

Kit (NEEK), Cyclone III Edition

- 10.0

Filters and Transforms

Design ExamplesDevice

Targeted Development Kits Supported Qsys Compliant

Quartus II Version

Achieving Unity Gain in Block Floating Point IFFT+FFT Pair

- - - 9.1

CIC Interpolation Filter With Multi-Channel Data Support

- - - -

Coefficient Reload Finite Impulse Response (FIR) Filter

- - - 9.1

Designing Digital Down Conversion Systems Using CIC and FIR Filters

- - - 7.1

Fast Fourier Transform (FFT) with 32K-Point Transform Length

- - - -

Multi-Channel Farrow Filter

- - - -

Nios II: Accelerated FIR with Built-In Direct Memory Access

Cyclone III , Stratix II

Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition,

Altera Embedded Systems Development Kit, Cyclone III

Edition, Nios II Development Kit, Stratix II Edition

- 9.0

Nios II: C2H Mandelbrot

Cyclone III

Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition,

Altera Embedded Systems Development Kit, Cyclone III

Edition

- 8.1

Reconfigurable Decimation Filter

- - - -

Run-Time Reconfigurable Scaler Design Example

Stratix II , Cyclone II - - 9.0

Sigma-Delta Converter - - - -

Using CIC Decimation - - - 7.2

Filter With Multi-Channel SupportVariable Rate Decimation Filter

- - - -

Modulation and Demodulation

Design ExamplesDevice

TargetedDevelopment Kits

SupportedQsys

CompliantQuartus II

Version

Implementing OFDM Modulation and Demodulation

- - - 7.2

Polyphase Modulation With Aliasing for Digital Up-Conversion

- - - -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

Memory Test - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/exm-c-memory.html

Altera -

Accelerated FIR with Built-In Direct Memory Access Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-accelerated-fir.html

Altera -

Altia Red Touch Screen HMI for D/AVE

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-altia-demo.html

Altia -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

Avalon Memory-Mapped Master Templates

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html

Altera -

Board Diagnostic - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-board_diagnostic.html

Altera -

Checksum Hardware Accelerator Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-checksum-acc.html

Altera -

Nios II CRC Acceleration Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-crc-acceleration.html

Altera -

Nios II Custom Instruction Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-custom-instruction.html

Altera -

Debugging Nios II Systems with the SignalTap II

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-

Altera -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

Embedded Logic Analyzer

property/embedded/nios-ii/exm-debug-signaltap.html

Debugging with System Console over TCP/IP (SCTCP) Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-debug-sys-console-tcpip.html

Altera -

Application Selector Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-demo-loader.html

Altera -

HAL Device Drivers Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-developing-hal-drivers.html

Altera -

Nios II Ethernet Acceleration Design Example

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-ethernet-acceleration.html

Altera -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

Fast Nios II Hardware Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-fast_nios2_hardware.html

Altera -

Hello MicroC/OS-II - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-hello_micro.html

Altera -

Nios II High-Performance Example with Bridges

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-high-perf-bridge.html

Altera -

IMAGEM Technology Solution Demos

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-imagem-taquin-game.html

Imagem Technology -

SPI Slave to Avalon Master Bridge Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-spi-bridge.html

Altera -

D/AVE Graphics Accelerator Demo From TES

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-

TES Electronics Solutions

http://www.tes-dst.com/support/

index.php/support-

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

property/embedded/nios-ii/exm-tes-demo.html

home/download-eval-kits/dave-2d

Using Tightly Coupled Memory with Nios II Processor

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-tightly-coupled-mem.html

Altera -

Triple Speed Ethernet Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-tse-sgdma.html

Altera -

Using NicheStack TCP/IP Stack – Nios II Edition

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-using-nichestack.html

Altera -

Vectored Interrupt Controller

- - /content/altera-www/global/ja_jp/index/support/support-resources/

Altera -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

design-examples/intellectual-property/embedded/nios-ii/exm-vectored-interrupt-controller.html

Micriµm µC/GUI Demo - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-micrium-uc_gui.html

Micrium -

MicroC/OS-II RTOS with the Nios II Processor

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-microc-osii-tutorial.html

Altera -

MicroC/OS-II Mutex Example - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-micro_mutex.html

Altera -

Nios II Processor with Memory Management Unit Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-mmu.html

Altera -

Nios II Multiprocessor Design Example

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-multi-nios2-hardware.html

Altera -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

Nios II Ethernet Standard Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-net-std-de.html

Altera -

Nios II 3C120 Microprocessor System with LCD Controller

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-nios-lcd-3c120.html

Altera -

Nios II 3C25 Microprocessor System with LCD Controller

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-nios-lcd-3c25.html

Altera -

Memory Protection Unit (MPU)

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-niosii-mpu.html

Altera -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

Network Time Protocol Client Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-ntp.html

Altera -

Profiling Nios II Systems Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-profiling-de.html

Altera -

Avalon Verification IP Suite Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/simulation/exm-avalon-verification-ip.html

Altera -

Nios II 低消費電 力デザイン例

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-

Altera -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

property/embedded/nios-ii/exm-low-power-nios2.html

Nios II コンパク ト・コンフィギュレーション・デザイン例

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-nios-compact.html

Altera -

Nios II エンベデ ッド・プロセッサ・デザインのシミュレーション

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-simulating-niosii.html

Altera -

プラネットウェブのSpectraWorks GUI のデモ

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-planetweb-spectraworks.html

PlanetWeb -

Web サーバーの デザイン例

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-micro_tutorial.html

Altera -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

MicroC/OS-II メ ッセージ･ボックス

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-micro_msgbox.html

Altera -

Nios II システム ・アーキテクチャ・デザイン

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-system-architect.html

Altera -

シンプル･ソケット･サーバのデザイン例

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-hello_world.html

Altera -

プラネットウェブの SpectraWorks Digital Photo Frame

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-planetweb-photoframe.html

PlanetWeb -

カウント・バイナリ - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-hello_free.html

Altera -

Nios II ハードウ ェア開発デザイン例

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-hardware-tutorial.html

Altera -

C2H コンパイラ のマンデルブロ

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-

Altera -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

ー・デザイン例 property/embedded/nios-ii/exm-c2h-mandelbrot.html

NiosII ブート方 法の応用 - -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-alt-boot-methods.html

Altera -

リード・オンリー Zip ファイル ・システム

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/exm-c-readonly.html

Altera -

Product Name

Ordering Code

Documentation URL Product URL

プロバイダー

Provider URL

Supported Devices

ハイエンド市場

PCI Target Memory Example for PCI MegaCore Functions

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-pci-target-memory.html

Altera - - interface_pci|interface

Product Name

Ordering Code

Documentation URL Product URL

プロバイダー

Provider URL

Supported Devices

ハイエンド市場

PCI Target Termination Examples for pci_mt32 and pci_t32 MegaCore Functions

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-pci-target-retry.html

Altera - - interface_pci|interface

POS-PHY Level 4 (SPI-4.2) External PLL Sharing Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-external-pll-merging.html

Altera - Stratix IV GX

interface_communications|interface

PCI Master Memory Example for pci_mt32 MegaCore Function

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-pci-master-memory.html

Altera - - interface_pci|interface

HiSPi Imager Connectivity Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/exm-hispi.html

- - - interface

Nios II Ethernet Acceleration Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-ethernet-acceleration.html

Altera - Stratix IV GX

embedded_3216bit|embedded|interface_ethernet|interface

SPI Slave to Avalon Master Bridge Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-spi-bridge.html

Altera - Cyclone III

interface_serial|interface|embedded_3216bit|embedded

Triple Speed Ethernet Design

- - /content/altera-www/global/ja_jp/index/support/support-resources/design-examples/

Altera - Cyclone III interface|embedded_3216bit|embedded|

Product Name

Ordering Code

Documentation URL Product URL

プロバイダー

Provider URL

Supported Devices

ハイエンド市場

Exampleintellectual-property/embedded/nios-ii/exm-tse-sgdma.html

interface_ethernet

Nios II Ethernet Standard Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-net-std-de.html

Altera -Cyclone III, Stratix IV GX

interface|embedded_3216bit|embedded|interface_ethernet

Web サーバ ーのデザイン例

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-micro_tutorial.html

Altera - Cyclone III

interface|embedded_3216bit|embedded|interface_ethernet

Product Name

Ordering Code

Documentation URL Product URL

プロバイダー

Provider URL

Supported Devices

ハイエンド市場

テクノロジ

Latest Version

Compatibility

Verilog HDL: Interfacing 400-MHz QDR II+ SRAM in a Stratix IV FPGA

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver-stratix-iv-18-bit-qdrii-uniphy.html

Altera - Stratix IV E

memory_external|memory_external_interfaces_qdrii|memory|memory_sram

-

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

Altia Red Touch Screen HMI for D/AVE

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-altia-demo.html

Altia -

IMAGEM Technology Solution Demos

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-imagem-taquin-game.html

Imagem Technology -

D/AVE Graphics Accelerator Demo From TES

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-tes-demo.html

TES Electronics Solutions

http://www.tes-dst.com/support/

index.php/support-home/download-eval-kits/dave-2d

Micriµm µC/GUI Demo

- - /content/altera-www/global/ja_jp/index/support/support-

Micrium -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

resources/design-examples/intellectual-property/embedded/nios-ii/exm-micrium-uc_gui.html

Nios II Multiprocessor Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-multi-nios2-hardware.html

Altera -

Nios II 3C120 Microprocessor System with LCD Controller

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-nios-lcd-3c120.html

Altera -

Nios II 3C25 Microprocessor System with LCD Controller

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-nios-lcd-3c25.html

Altera -

プラネットウェブのSpectraWorks GUI のデモ

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-planetweb-spectraworks.html

PlanetWeb -

プラネットウ - - /content/altera-www/global/ PlanetWeb -

Product Name Ordering Code

Documentation URL Product URL プロバイ

ダー Provider URL

ェブの SpectraWorks Digital Photo Frame

ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-planetweb-photoframe.html

Verilog HDL: Microcontroller I/O Expander

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/verilog/ver_microcontroller-io_expander.html

Altera -

Product Name

Ordering Code

Documentation URL Product URL

プロバイダー

Provider URL

Supported Devices

ハイエンド市場

Debugging with System Console over TCP/IP (SCTCP) Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-debug-sys-console-tcpip.html

Altera - Cyclone III

Avalon Verification IP Suite Design Example

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/design-software/simulation/exm-avalon-verification-ip.html

Altera - -

Product Name

Ordering Code

Documentation URL Product URL

プロバイダー

Provider URL

Supported Devices

ハイエンド市場

Nios II エ ンベデッド・プロセッサ・デザインのシミュレーション

- -

/content/altera-www/global/ja_jp/index/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-simulating-niosii.html

Altera - Stratix II

Altera's SoC series offers a balance of hardware performance, low power, form factor, and cost. Because the Altera® SoCs integrate many hard intellectual property (IP) blocks, you can lower your overall system cost, power, and design time.

The design examples provided target the following Altera development kits:

• Cyclone ® V SoC Development Kit • Arria ® V SoC Development Kit

Each design example is accompanied by a design archive and readme file. Instructions about importing the design archive, compiling the design software, running the executable, and the expected terminal output are all provided in the readme file for each design.

Other design examples can be found on the SoC RTOS and HWLIBs Support page as well as on Rocketboards.

Table 1: SoC Design ExamplesDesign Name Description File/

Webpage Readme

HPS DMAThis HWLIB design example demonstrates how the DMA APIs are used to initialize the DMA, perform memory to memory transfers, and zero to memory transfers.

Example-AV

Example-CV

Readme-AVReadme-CV

Error correction code

This HWLIB design example demonstrates the error correction code (ECC) APIs features for on-chip RAM, SD/MMC, quad serial peripheral interface (SPI), DMA and L2 cache. The example shows how to setup and enable ECC for each RAM, inject single/double bit errors and setup the interrupts for single/double bit error detections.

Example-AV

Example-CV

Readme-AVReadme-CV

GPIO This HWLIB design example demonstrates the usage of general-purpose input/output (GPIO) APIs to setup GPIO as output ports to drive HPS LEDs, and to setup GPIO as input

Example-AV

Example-CV

Readme-AV

ports for HPS push buttons. Readme-CV

I2C

This HWLIB design example demonstrates the usage of I2C APIs to perform master read/write and slave read/write. This example demonstrates I2C communication with LCD screen, EEPROM memory as well as communication between two I2C modules.

Example-AV

Example-CV

Readme-AV

Readme-CV

Quad SPI

This HWLIB design example demonstrates the usage of quad SPI APIs to perform reading and writing to the quad SPI with generic block I/O functions, perform data transactions using indirect mode and DMA mode. The example also demonstrates additional API features such as setting up MMU and caches.

Example-AV

Example-CV

Readme-AVReadme-CV

SD/MMCThis HWLIB design example demonstrates the usage of SD/MMC APIs to initialize SD/MMC card, read and write using block I/O functions.

Example-AV

Example-CV

Readme-AV

Readme-CV

TimerThis HWLIB design example demonstrates how to use the Timer APIs for free-running timer, one-shot timer, watchdog timer, and global timer measurements.

Example-AV

Example-CV

Readme-AV

Readme-CV

Quad SPI Porting

This HWLIB design example shows how the quad SPI APIs can be modified and ported to support more quad SPI flash devices.

Example-AVExample-CV

Readme-AVReadme-CV

UnhostedThis HWLIB design example shows how to use UART for printf output instead of semihosting. It also demonstrates how to boot a bare-metal program from a SD card.

Example-AVExample-CV

Readme-AVReadme-CV

SPIThis HWLIB design example demonstrates the usage of the SPI APIs to communicate between two SPI modules connected through the FPGA fabric.

Example-AV

Example-CV

Readme-AV

Readme-CV

HPS Peripheral Mapping to FPGA

This design example shows how to route the hard processor system (HPS) EMAC and I2C peripherals into the FPGA fabric and connect them to FPGA I/O.

Example Readme

Power Optimization

This HWLIB design example illustrates the use of WFI or WFE calls that put the calling processor core into clock gating mode to save power.

Example Readme

 

  関連リンク• アプリケーション・ノート • ユーザーガイド • IP コア・ポートフォリオ

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