Kiến Trúc Bộ Nhớ Máy Vi Tính

Kin trc b nh my vi tnhBi:

Ng Nh Khoa

Cc khi nim chung

Mt trong cc hot ng c bn ca my tnh l lu tr d liu dng nh phn. Cc dliu ny l cc chng trnh hoc s liu m Vi x l a ra hoc c vo tu theo yucu. B nh l cc thit b thc hin nhim v lu tr d liu ca my vi tnh.

Mi nh c xc nh bi mt a ch. Thng thng mi nh c dung lng l 1byte. Cc byte c ghp thnh t. Nhng my 16 bit s liu th t chc 2 byte/t, cncc my 32 bit s liu th di t gp i (4 byte/t).

Trt t cc byte trong t

C th l t phi sang tri (vi x l h Intel) hoc ngc li t tri sang phi (vi x lh Motorola). Trng hp d liu lu gi l s nguyn th hai cch sp xp trn khngc tr ngi g. Nhng khi d liu bao gm c s nguyn v c xu k t ... th c vn .

V d, xt mt bn ghi (h 7.1) gm c xu l tn nhn vin BILL GATE v trng l snguyn: tui 42. Xu kt thc bng cc byte 0 cui in kn ch trng ca t, cns nguyn th c thm vo cc byte phn c trng s cao hn. Do vy nu dch cchsp xp n sang cch kia ca xu ging nh ca s nguyn th s b nhm.

M pht hin li v sa sai

S cc v tr bit khc nhau trong hai t gi l khong cch Hamming. V d, trong hait: 10001001 v 10110001 c khong cch Hammming bng 3.

sa sai, bn cnh m s bit s liu ca t, ngi ta thm vo r bit d (redundant bits)v chiu di tng ca t l n : n = m + r

pht hin d bit li n, cn dng m c khong cch d+1. Tng t, sa li d bitn, cn dng m c khong cch 2d+1. V d, dng m bit parity thm vo byte s liu,m ny c khong cch bng 2, dng pht hin 1 bit sai, nhng khng sa c li.

Kin trc b nh my vi tnh

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Trong truyn 1 khi k t, mi k t c mt bit parity kim tra. cui mi khi, tatruyn thm mt k t l parity ca ton th bn tin, gi l longitudinal check (LRC).Pha thu s tnh LRC v so vi LRC nhn c kim tra li. Mt phng php na kim tra li khi truyn s liu l dng CRC (Cyclic redundance check), l mt athc nh phn d thu c khi chia a thc cc bit ca bn tin cho mt a thc quy nh.

M sa sai l m c 4 t di 10 bit nh sau:

0000000000, 0000011111, 1111100000, 1111111111. M ny c khong cch l 5, tcl n c th sa c cc li kp. V d nu ta nhn c t 0000000111, my thus bit rng t phi l 0000011111 (nu coi nh khng c nhiu hn mt li kp).Nhng nu mt li ba xy ra, bin 0000000000 thnh 0000000111 th ta khng sa lic.

sa li, ngi ta dng thut ton ca Hamming.

Kin trc tng th ca b nh

Xt mt cch tng th, b nh ca my tnh c kin trc theo cung bc (hierarchy) tridi t b nh ngoi n b nh trong v cui cng l n b nh m (cache) trong vngoi CPU.

Hieratchy ca b nh trong my vi tnh


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Qun l b nh (MMU, Memory Management Unit)

Cng vic qun l b nh ca my vi tnh ch yu l do b vi x l m nhim. Dncnh cn c DMAC (Direct Memory Acess Controller) cng tham gia qun l b nhtrong vic truyn s liu gia controller a vi b nh v lm ti b nh. nhngmy c Cache Memory th Cache Memory Controller thc hin cc cng vic truyn sliu gia Cache Memory v RAM.

khu vc trung tm ca my vi tnh (b vi x l, ROM, RAM, cc bus...), thc chtca vic qun l b nh l cc thanh ghi ca vi x l a ra cc a ch ca nh hocca cng I/O qua bus a ch, cng cc lnh iu khin/ trng thi khc v c vo/ vitra cc s liu ca cc nh y. Cc b phn bn ngoi VXL s gii m cc a ch vcc tn hiu iu khin/ trng thi tr vo cc byte/ t/ t kp... ca b nh thchin cc thao tc tng ng.

Cn t cc a tr i, vic qun l b nh l thc hin cc lnh co hn iu hnh lncc file (c a ch 3 chiu l C-H-S), c th l truyn s liu nh DMAC gia vng m(buffer) ca b iu khin a vi b nh RAM.

Cc b vi x l Intel t th h 286 tr i phn bit hai mode a ch: mode a ch thc(ch qun l 20 bit a ch vt l ca b nh) v mode a ch bo v (qun l ti 32 bita ch o nh cc thanh ghi n trong b vi x l).

cp di, tc cp ngoi vi, nh b iu khin a, b iu khin mn hnh, my in...cng c t chc b nh ring ca chng tin cho vic ct gi v x l vi cc c thring.

Cc b nh RAM-ROM v cc vng nh ca b nh ngoi (trn cc a), khc nhauv cch m ho cc bit, cch t chc, do c cch truy nhp cng khc nhau.

T chc b nh ca vi x l

B nh ca vi x l c th xem nh bao gm c b nh ROM v b nh RAM. B nhRAM ca vi x l chnh l cc thanh ghi (thanh ghi chung, thanh ghi ch s, thanh ghion, thanh ghi ngn xp, thanh ghi trng thi, thanh ghi c, cc b m s liu/ a ch/iu khin...). Cn b nh RAM l b phn gii m lnh pht ra cc vi lnh.

Nhm mc ch qun l c s lng a ch nh (o) nhiu hn s ng a ch cab vi x l v bo v cc vng nh ca cc nhim v khc nhau (task) v ca ht nhn(kernal) chng truy nhp khng hp php, cc vi x l c cc cch t chc c bit ccthanh ghi a ch (b phn phn trang, iu khin on ca cc nhim v).


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Cc b vi x l t th h 486 tr i cn c mt b nh Cache Memory vi kch thcnhiu Kbyte cha mng cc lnh v s liu ang thng dng ly t b nh RAM,nhm tng tc truy nhp.

tng tc tnh ton cc php ton du chm ng, trong cc b vi x l t 486 tri cn c b phn du chm ng (FPU, Floating Point Unit), b phn ny cng c ccthanh ghi FPU phc v ring cho n.

T chc b nh trong ca my vi tnh

B nh trong ca my tnh dng cha chng trnh v s liu ca phn chng trnhht nhn v cc nhim v. Mi byte c gn cho mt a ch v l v DMAC c thtruy nhp ti.

B nh RAM nhng my t 386 tr i c th c tch ring ra b nh m (cachememory), l RAM tnh vi thi gian truy nhp nhanh, c kch thc di 1Mb cni ngay vo bus ni b ca my tnh st ngay vi x l v c iu khin bi Cachecontroller. Phn cn li l DRAM, chm hn nhng r hn v c dung lng ln hn.Hnh 7.3 th hin s khi bn trong mt my 386.


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Phn trung tm my tnh AT 386

Trong s : Vi x l l 80386, ng x l ton l 80387, cache controller 82385 cni trc tip vi nhau thnh mt bus local. Cc ng a ch A2-A31 ca 386 ni trctip ti cc ng cng tn ca 82385DX, cc ng s liu D0-D31 ca 386 c nitrc tip ti cc ng s liu cng tn ca 387DX. Hn na, cc chn quy nh chu kbus D/C#, W/R# v M/IO# c ni trc tip ti cc chn tng ng ca 82385DX.

T bus local ca VXL, cc ng a ch c m ra bng cc cht a ch 8 bit 74373(khng v trong hnh). Cc ng s liu ca bus local c m hai chiu bng DataBuffer 82345.

System Controller 82346 l tri tim ca cc chipset 340. N ni ti bus local ca 386,bus m rng ISA, Data buffer 345, ISA Controller 344. N thc hin mt s chc nngsau:


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- Nhn xung ng h t bn ngoi pht nhp clock TURBO v clock chm hn.

- Lm trng ti bus (cc vic v DMA v lm ti b nh)

- Pht cc tn hiu a ch hng RAS v a ch ct CAS n cc dy nh ca ton b bnh DRAM trn MainBoard, pht tn hiu ghi vo RAM

- Pht tn hiu ready, tn hiu Reset CPU

- Giao tip gia ng x l vi CPU.

Controller ISA 82344 ni gia bus local ca CPU vi bus h thng lm cc chcnng giao tip vi CPU, system controller 346, data buffer 345, ROM, bus, cc thit bngoi vi nh sau:

- Nhn cc tn hiu BE0# - BE3# ca CPU, ROM8# v IOCHRDY t bus ISA sinhra cc tn hiu chn byte chn v byte l SA0# v SBHE#

- To cc tn hiu giao tip gia 344, 345 v 346.

- Cha khi iu khin ngoi vi Peripheral Control gm cc vi mch c tch hp cccao (VLSI) quen thuc: hai 82C59 (ngt), hai chip 82C37A (DMAC), vi mch nh thi82C54, thanh ghi a ch trang 74LS612, b driver cho loa, port B parallel I/O, ng hthi gian thc v b m lm ti b nh.

- Gii m a ch to ra cc tn hiu chn chip CS8042# cho controller bn phm 8042v ROMCS# cho php chn ROM BIOS.

Vi mch Peripheral Combo 82341 c ghp vo bus m rng ca bus ISA, n chacc VLSI thc hin mt s chc nng ca cc thit b ngoi vi sau y:

- Hai cng ni tip khng ng b 16C450

- Mt cng song song cho my in

- ng h thi gian thc

- RAM s tay, cc controller cho bn phm v chut.

- Interface cho a cng (tiu chun IDE).

Controller a mm 82077 c th iu khin ti 4 a mm cc loi 51/2 v 31/2.


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T chc b nh RAM ca my tnh

Xt trng hp my 386, n c 32 bit a ch, t 00000000H n FFFFFFFFH, ng vi4 GByte khng gian nh vt l. V quan im phn cng, ta chia khng gian thnh 4dy nh c lp nhau, l bank0 - bank3, mi bank kch thc 1 GByte. Chng cn cctn hiu Bank Enable BE0# ti BE3#. Trong hnh 7.4 sau, ta thy cc a ch A2 - A31c t song song vo tt c 4 bank nh. Cn mi bank nh ch cung cp 1 byte s liucho 32 ng s liu.

ch thc, 386 ch dng cc ng a ch A2 - A19 v 4 tn hiu BE# dng chnbank nh. Mi bank ch c 256 KByte.

T hnh 4 ta thy khng gian nh vt l c t chc thnh dy cc t kp (32bit). Do mmi t kp xp ng hng (aligned) bt u a ch bi s ca 4.

Dng t hp cc tn hiu BE# c th truy nhp c vo cc fmat khc nhau (byte, t,t kp) nh hnh 5. Vic truy nhp vo a ch u ca t kp c th cn 1 chu k bus(khi t kp xp ng hng) hoc 2 chu k bus (khi t kp xp lch hng, misaligned).

Interface gia VXL v b nh

S giao tip gia vi x l 386 vi b nh ch bo v c v trn hnh 7.6. Tathy rng giao tip bao gm cc vic:

- Gii m cc trng thi ca vi x l (ADS#, M/IO#, D/C#, W/R#) cp ra cc tn hiuiu khin bus (ALE#, MWTC#, MRDC#, OE# cho b nh, DT/R# v DEN#).

- Gii m 3 a ch cao nht (A29-A31) c c 8 tn hiu chn chip CE0# - CE7#,cho trng hp mi chip 1 bit, ri cht cc a ch A2-A28 v CE0# - CE7# a sangb nh.

- m truyn s liu hai chiu gia VXL v b nh c iu khin bi cc tn hiu chophp a ra s liu EN# v nh hng truyn DIR.

- T cc tn hiu BE0# - BE3# v MWTC# cp iu khin vit ln cc bank nh WEB0#- WEB3#.

- B nh cp cc tn hiu NA#, BS# v READY# cho VXL.

Gii m a ch v Latch a ch, m hai chiu s liu

B gii m a ch c th t trc hoc sau b cht (h 7a,b). Sau b cht a ch c khicn m ring cho a ch I/O. V d dng 4F244 c th sink c 64 mA (h 7c).


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gii m a ch ngi ta dng mch 74F138 vi 8 ng ra (hoc 74F139 hai mchgii m, mi mch c 4 ng ra). Trn hnh 7.8 ta thy 2 a ch cao nht dng giim ra 4 tn hiu chn chip CE0# - CE3#. Latch ta dng cc vi mch 74F373 (c thsink c 24 mA max). Chn ra 3 trng thi OC# ni t, cn chn CLK ca 373 ccp ALE# lc cn Latch a ch ra. Chn ra 3 trng thi OC# ni t, cn chn CLK ca373 c cp ALE# lc cn latch a ch ra.

Hnh 8 Gii m v latch a ch ca my 386.

m v truyn s liu hai chiu (hnh 7.9) cho bus s liu ca VXL (dng max 4mA)ta dng cc m 8 bit hai chiu 74F245 vi dng sink max l 64mA. Ta cng dng vimch 74F646 l cc m 2 chiu vi thanh ghi, n c th dng nh mt b m ngin hoc dng vi chc nng m - thanh ghi trong s liu truyn t bus ny vomt thanh ghi bn trong vi mt dy tn hiu iu khin, v t thanh ghi trong ra bus kiavi tn hiu iu khin khc.

Gii m trng thi bus VXL

VXL 386 cp trc tip ra ba tn hiu quy nh kiuy ca chu k nh hin hnh ca busl: Mem/IO#, Data/Control# v Write/Read#. Bng 7.1 ch ra 8 kiu ca chu k bus ca386. Ngoi ra, VXL cn cp AM, v tn hiu ADS# (Address Status) h xung mc 0 bo rng 3 tn hiu trn AM l bnh n hu hiu. hnh 7.6 ta thy mt mch logiciu khin bus, c dung gii m kiu ca chu k bus nhm cp ra cc iu khintng ng ti Mem/IO, Latch Address.

Controller bus c th c ch to bi cc PLA (Programable Logic Arrays), n l ccmch c nhiu li ra, mi li ra th i l nghch o ca tng cc tch cc li vo th j.

Cc PLA thng c ca ra ba trng thi (vi chn iu khin CE#). C loi cn c thanhghi D - Latch li ra.

Vic lp trnh PLA thc hin nh my, bng cch t chy nhng mi ni khng munc ti cc nt.

B phn Cache Memory v Controller Cache Memory

Mc d c dng cc thit b nh DRAM tc truy nhp ti 60nS, EPROM 120nS,... ,nhng n vn chm ngay c vi cc h my 386 zero-wait-state. V d 386 loi 25 MHz i hi nh c thi gian truy nhp nh hn 40nS. V vy ta vn phi a thm ccwait-state vo cc chu k bus truy nhp c nh.


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V vy ta a vo gia VXL v b nh trong chm, r tin mt vng nh SRAM cdung lng nh, thi gian truy nhp rt nhanh ci thin vn truy nhp b nh camy vi tnh. B phn gi l Cache Memory. B phn nh ny nhanh v c th ctruy nhp khng c chu k i.

Nh vy Cache Mem gi cc lnh v s liu m CPU ly t b nh chnh a v xl. V mi khi tm lnh hay s liu, CPU phi xc nh xem chng c ct trongCache cha; nu n tm thy trong Cache, ta gi l trng Cache, nu khng, gi l trt.

Hnh 7. l s b tr v tng tc gia VXL, Cache, b nh chnh trong trng hpthc hin mt roitine lp (loop).

Thng dng hai cch t chc cache. Cch th nht l dng cache trc tip (direct-mapped cache) vng nh c a ch offset trang nh cache 64KB (h 7. ). Cch th hail dng cache hai ng(two way set associative cache) theo ta chia trang nh cachethnh hai bank, mi bank 32 KByte. V vng nh cc trang ca b nh chnh c thc np sang bank A hoc bank B cu cache. Do t l cache trng s tng ln. (h 7.).

Thut ton i mi b phn nh cache thc cht l b phn ni dung nh lu khngc dng (least recent used, LRU) v thay vo bng ni dung mi cn dng. Thutton ny cng vi dng cache 2 ng cho php tng t l cache trng ln nhiu.

Cache Controler 82385 c thit k ni trc tip vi CPU 80386. N c th cdng ci t nhiu cu hnh khc cache nhau. Hnh 7. l kin trc ca mt h cachevi CPU 386, Cache Controller 82385, nh cache cng cc m s liu v a ch.

Ta thy cc ng a ch A2 - A31 v BE0# - BE3#, cc ng s liu D0 - D31, cctrng thi bus (M/IO#, D/C#, W/R#) do CPU cp cho Cache Controller v cc Buffera ch, s liu, iu khin, cn Controller cp mt s tn hiu iu khin ti b nhCache v ra bus local ca n.

Xt v d iu khin 32 KByte nh Cache theo hai phng php Cache trc tip vCache 2 ng hnh 7. . Cc tn hiu iu khin ca Cache Mem gm:

- CALEN (Cache Address Latch Enable) cp cho pin E ca Latch 373 cho nh cache.

- CT/R# (Cache Transmit/ Receive) iu khin truyn s liu DIR b nhn 245 trnbus s liu ca b nh cache.

- CS0# - CS3# (Cache chip select) dng chn chip cho bn vi mch SRAM.

- COEA#, COEB# (Cache Output Enable) v CWEA#, CWEB# (Cache Write Enable)dng cho chn OE# ca b nhn s liu 245v chn WE# ca SRAM.


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Ngoi ra cn c cc tn hiu do Controller cp l

- BACP (Bus Address Clock Pulse) to xung nhp cho cc mch Latch.

- BAOE (Bus Address Output Enable) iu khin pin OE# ca Latch.

- BT/R# (Bus Transmit/ Receive), DOE# (Data Ouput Enable) v LDSTB (Local DataStrobe) iu khin transceive s liu 646.

Nhng tn hiu giao tip gia Controller vi bus local ca n gm:

- BBE0# - BBE3# (Bus Byte Enable).

- BADS# (Bus Next Address Request)

- BLOCK# (Bus Lock), BHOLD, BHLDA(Bus Hold Acknowledge)

- FLUSH khi u xo nh Cache bi thit b ngoi.

- MISS (Cache Miss) ch ra rng a ch hin hnh trn bus khng tng ng vi s liuang c trong Cache v phi c li thng tin t b nh chnh.

-WBS (Write Buffer Status) ch ra rng cc thanh ghi trong 646 cha nhng s liu (vit vo b nh chnh) khng c vit vo b nh chnh.

Hot ng ca Cache trc tip v Cache hai ng

Cc hot ng ca Cache trc tip v Cache 2 ng c m t hnh 7. . Trong mytnh 386 ton b khng gian nh vt l 4 GByte c chia thnh 217-1 trang nh 32KByte. V my 386 c t chc s liu 32 bit, nn mi trang c 8Kb t bp.

Controller cha 1024 li vo 26 bit, c tn l SET 0 - SET 1023 cha trng thi cacc nh ca Cache Directory. trong trng hp Cache trc tip, mi li vo tng ngvi 8 dng lin tip (t kp) trong dy nh Cache. Trong trng hp Cache 2 ng,c hai Cache Directory l A v B ng vi cc Bank A v Bank B ca nh Cache, miBank cha 4 KByte t kp, do trong Controller cha hai tp li vo (Set Entry) di27 bit. Mi Set ch c 512 li vo. nh dng ca thng tin a ti cc li vo gm c 8bit Line Valid Bits, Tag Valid Bit v Tag 17 bit (vi Cache trc tip), 18 bit (vi Cache2 ng). Hnh 7. .


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Format ca Entry SET ca Cache Directory trc tip v hai ng

Phn TAG di 17/18 bit ch ra s hiu ca 1 trong 131972 trang 32 KB (hoc 262144trang 16 KB) trong b nh chnh. Cn TAG_BIT ch ra TAG c hu hiu hay khng.Nu TAG_BIT = 0 th tt c cc dng trong SET l khng hu hiu. Nu TAG_BIT =1 th mi bit trong 8 bit ca LINE_VALID_BITS bng 1 c ngha rng dng tng ngtrong Cache cha thng tin hu hiu, tc l thng tin trong s c cp nht t ng.

Nu SET 1 = 00005FFh, ta chuyn sang dng nh phn:

SET 1 = 0000 0000 0000 0000 0101 1111 1111. T ta c: TAG = 0000 0000 00000000 010 = 2(10)

TAG_VALID = 1, do nhng dng trong LINE_VALID_BIT = 1111 1111 s huhiu. Tc l tt c 8 dng trong Cache u hu hiu.

*Cache trc tip.

Khi VXL 386 bt u chu k c nh, n cp a ch song song ra cho 3 ni l Latch ach ca local bus ca controller, li vo a ch ca controller v interface nh Cache. khi, Cache Controller quyt nh l VXL cn c t b nh chnh hay t Cache. N thchin iu bng cch thng dch a ch v so snh vi ENTRY ca Cache Directory.

Hnh 7. l cc trng (field) ca bit a ch cho Cache trc tip c Cache hai ng.Trong 17/ 18 bit ln nht A15 - A31 (hoc A14 - A31) l TAG ch ra trang cab nh chnh cn c thng tin t vo VXL. Cc bit tip theo, A5 - A14 (hoc A5 -


11/21

A13) gi l a ch ca SET ca nh Cache, ch cn truy nhp vo. Cn 3 bit b nhtA2 - A4 chn dng trong SET.

Cc trng bit a ch dng cho Cache trc tip v hai ng

Khi mt a ch do VXL t vo li vo a ch ca Controller, phn SET ca a ch c dng chn 1 trong 1024 ENTRY ca SET trong Cache Directory. Sau Controller tin hnh 3 kim tra nh sau:

- So snh trng TAG trong a ch vi TAG trong ENTRY ca SET c chn,chng phi trng nhau.

- Bit TAG_VALID_BIT ca ENTRY SET c chn phi bng 1.

- LINE_VALID_BIT ca ENTRY tng ng vi gi tr trong phn LINE_SELECT caa ch phi = 1.

Nu c ba iu kin trn tho mn th thng tin cn phi c t b nh c lu trongb nh Cache v hu hiu. V Controller khi u chu k c d liu t Cache thay vt b nh chnh. y l trng hp trng Cache.

Nu hai iu kin u tho mn, cn LINE_VALID_BIT = 0 th trt Cache, tc lENTRY ca SET trong Directory tng ng vi trang ng ca nh chnh, nhng dngt kp cn phi c vo VXL li cha c chuyn sang Cache, gi l trt dng. Khi VXL phi c t b nh chnh mt t kp, ng thi c a vo nh Cache vLINE_VALID_BIT trong ENTRY ca Cache Directory c xc nh bng 1. Do thng tin c c vo Cache v nh du l hu hiu.


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Nu trong khi kim tra hoc cc TAG khng khp hoc TAG_VALID_BIT = 0 th xyra trt TAG (tag miss). l trng hp c mt trang khng c Cache, hoc Cache nhng khng hu hiu. Trong trng hp ny Controller phi khi u mtchu k c t b nh chnh vit vo b nh Cache. Lc TAG trong SET ENTRY caDirectory c cp nht bng phn TAG ca a ch, TAG_VALID_BIT c lp bng1, mt LINE_VALID_BIT do a ch tr ra c lp bng 1, mt LINE_VALID_BITSb xo i. Bng cch ny mt trang hu hiu v ENTRY dng c lp nn v tt c ccENTRY khc trong SET baay gi tng ng vi thng tin trong mt trang khc ca nhchnh tr nn khng hu hiu.

* Cache hai ng.

cc hnh nu ra cch t chc nh Cache, cng cc format ca ENTRY SET, cctrng a ch ca c hai trng hp Cache trc tip v Cache hai ng.

Trong trng hp (hnh 7. ) Cache hai ng ngoi hai Directory A v B ng vi hai bENTRY, cn c thm 512 c Least Recently Used di 1 bit (LRU bit). Nhng c nytheo di xem BANK A hoc BANK B ang gi thng tin lu khng s dng. Nhng cny c Controller kim tra bng thut ton thay th nhng thng tin lu khng dng.

Thao tc c thng tin t nh Cache hai ng cng ging nh Cache trc tip. Bitrng ( s h ) SET_ADDRESS ch c 9 bit. u tin a ch 9 bit ny c dng chn 1 trong 512 li vo SET ca c hai Directory A v B. Tip theo TAG_ADDRESS18 bit c so snh vi TAG trong mi li vo SET, TAG_VALID_BITS c kimtra, v LINE_VALID_BIT tng ng vi m ca LINE_SELECT (A2 n A4) ckim tra trong mi li vo SET. Nu ba iu kin kim tra c tho mn i vi mttrong hai li vo SET th ta ni l trng Cache v thng tin ca dng c c vo VXLt BANK tng ng ca nh Cache.

Mt khc, s xy ra trt Cache nu khng khp cc TAG hoc nu c hai VALID_BITb xo, hoc nu LINE_VALID_BIT khng c lp trong bt c li vo no, khi algorithm s kim tra bit c LRU i vi SET c chn bi a ch SET xc nhxem li vo ca BANK A hay BANK B l lu khng c dng hn, sau thng tinc c vo t b nh chnh v vit vo BANK nh no lu khng c dng.

Lm ti b nh DRAM

B nh DRAM c cc hng cn phi c lm ti trong mi chu k 2mS. Mch lmti trong chip nh phi kim tra in p cc nh, nu n ln hn Vcc/2 th np n tiVcc , nu b hn Vcc/2 th x ht v 0V.

c mt t t BANK nh DRAM, trc ht DRAM Controller hoc mt mch khccp tn hiu WE# = 1. Sau gi na thp ca a ch, ng vi a ch hng, ri tn hiu


13/21

RAS# = 0. Sau 1 thi gian, controller cp na a ch cao, ng vi a ch ct, ri tnhiu CAS# = 0. Sau thi gian nht nh, t cn c s xut hin trn Output Data ca nh.

vit vo DRAM, cc tn hiu cng tng t, ngoi tr sau tn hiu CAS# = 0,controller cp WE# = 0 quy nh vit vo RAM.

Controller lm ti DRAM bng cch gi ra mi a ch trong 512 a ch hng v cpRAS# = 0 theo chu k, khong 4mS. Vic lm ti c tin hnh hoc theo burst modehoc theo distributed mode. Trong burst mode ton b 512 hng c nh a ch vnh nhp ln lt cch nhau 4mS. Cn distributed mode hng c nh a ch vnh nhp sau 4/512 mS. Hnh 7. l mch lm ti DRAM vi controller lm ti 8208.

Hnh 7. . Mch lm ti b nh dng 8028.

Nhng nhim v chnh ca vic iu khin nh DRAM ca my tnh l:

- Lm ti mi nh sau mt khong thi gian vi mS.

- Cp hai na a ch cng cc tn hiu RAS#, CAS# thch hp.

- Bo m thao tc c/vit v lm ti khng xy ra ng thi.

- Cp tn hiu c/vit iu khin chiu s liu.

Hnh 7. m t s Controller 8208 lm ti 1 MByte cho h VXL 8086. B nh chiathnh 2 BANK (mi BANK 8 bit). Controller bo m cp cc a ch hng v a chct, tn hiu RAS#, CAS#, v cc tn hiu READ/WRITE. Cc chn trng thi ra S0 -S3 ca VXL u thng ti cc chn vo ca 8208. Controller gii m cc tn hiu ny cho ra cc tn hiu c v vit m VXL yu cu. Do , a s thi gian ca VXLcdng c byte/t ca RAM m khng cn c cc chu k ch. Nu trong khi 8208ang gia chu k lm ti nh m VXL mun c RAM th 8208 lu gi AACK caov buc VXL cp thm mt chu k i 8208 kp hon thnh chu k lm ti. titkim chn, khng c cc chn s liu ( np t iu khin), chn PDI ni mass s chophp 8208 t khi u hot ng trong a s cc ng dng. Cn cc trng hp khcth chn PDI s c iu khin bi mt thanh ghi dch vo song song - ra ni tip, nh t iu khin c np vo 8208. Sau khi Reset chn WE/PCLK s cp ra mt dyxung nh nhp cho t iu khin t thanh ghi dch np vo 8208. T iu khin cthc hin bng ni li vo ca thanh ghi dch.

Ta cng c th dng DMAC lm ti b nh. Hnh 7. l v d mch 4 BANKvi dung lng 256KB nh. y my tnh dng ch c DMA o. B nh thi8253 lp trnh pht xung nhp 15S. Xung ny c ni vo mt trong cc li voxin DMA (DMA Request) l DREQ0 ca 8237 DMAC c lp trnh c t nhv vit vo mt cng khng tn ti. Khi DMAC nhn xung ny, n gi mt tn hiu


14/21

HOLD_REQUEST ti VXL ri VXL tr li bng tn hiu HLDA v t cc chn can trng thi tr khng cao. Khi : 8237 chim ly bus, gi ra cc a ch nh, tnhiu c nh v tn hiu chp nhn DMA knh 0 (DACK0).

Tm bit a ch thp gi ti nh, cn DACK0 cung cp xung RAS# cho cc bankDRAM lm ti nh ng. Sau mi thao tc DMA thanh ghi a ch hin hnh trongDMAC c t ng tng/gim (tu thuc cch lp trnh lc u) lm ti hng(row) nh sau. Nu 8237 lp trnh truyn 64 kByte, khi u a ch 0, tng msau mi ln DMA, v t khi ng (autoinitialize), th dy cc a ch gi ra s lm titt c 256 trong hng DRAM. Mi hng lm ti 15ns.

V d vi tn s clock 4.77MHz dng trong IBM PC, mt chu k DMA lm ti mt820 ns mi 15 ns, tc 5% thi gian ca VXL.

kim tra Parity mi bank nh c 9 bit, 8 bit gi s liu, bit th 9 l bit Parity.Mi mch 74 LS280 dng pht/ kim parity cho mi byte v ct vo parity bit mikhi byte c vit vo nh. Khi 9 bit c c ra, parity c kim tra. Nu parity saith tn hiu bo li s c gi ti cng 8255 cho VXL c. Khi bt u bt my, thqu trnh POST xy ra, n vit mu byte vo tt c nh, ri kim tra bng cch c lichng cng vi parity bit.

Chuyn mt mng s liu bng DMA

Thng xuyn c cc nhu cu chuyn mng s liu nh v ngoi vi. Lc ta dngDMAC. Hnh m t c ch hot ng ca DMAC vi VXL truyn s liu gia nhv ngoi vi ( a thng minh).

Khi ta bt my lc u cc kho v tr ng t VXL ti ngoi vi, v nh. Chng ta lptrnh chy DMAC, v d c file t a vit vo nh. Mun th phi gi mtlot lnh ti controller a yu cu n c nhng block d liu t a. Khi controller c byte u tin, n gi DMA Request(DREQ) cho DMAC, nu channel ca DMACkhng b che chn , DMAC gi HOLD REQUEST ti chn HOLD ca VXL, VXL treocc bus cao v gi ra HLDA cho DMAC, khi DMAC nhn HLDA ca VXL, n cho tnhiu iu khin t ba kho v v tr DMA, ct VXL ra, sau DMAC cho ra a chcp cho nh, DMAC gi DMA-Acknowlege (DACK0) cho a n a ra s liu,cui cng n cp MEMW#=0 v IOR#=0 ra bus iu khin, nh vy liu c c vot ngoa vi v vit ra nh, khi truyn s liu hon thnh DMAC thu li tn hiu HRQ,do VXL ly li cc bus ca n cho n ln DMA sau.

Hnh l mch chi tit ca s hnh . Trong 8237 l DMAC cn 8272 l controller a mm, 8282 dng latch 8 bit a ch gi ra t VXL (do ALE ca 8086 iu khin) hoc 8237 (do AEN v AD dress STrobe iu khin).


15/21

Khi ng in DMAC cp AEN = 0, cc vi mch U1, U2, U4 c hu hiu. V ALEt VXL c dng nh nhp (STroBe) cho 3 vi mch ny. Do chng cht cc ach A0-A19 ca VXL ra bus a ch nh trng hp thng thng (khng DMA).

Khi DMAC mun chim ly cc bus, n cp AEN= 1, dn n:

- Kho khng cho U1 lm vic, ct cc a ch A0 -A7 t VXL, DMAC trc tip cp ra8 a ch thp cho nh trong truyn s liu,

- AEN =1 lm i v tr Multiplex khin cho vic nh nhp cho U2 thc hin biADSTB ca DMAC. tit kim chn, DMAC 8 bit a ch cao qua cc chn s liuD0-D7, cng vi ADSTB=1 bo rng l cc a ch cao A15- A8 do DMAC cp choqua nh latch U2.

-Cng do AEN =1, cc bit A16- A19 do U3 cp t cc bit D10 -D13 do ta lp trnh cng.

-Cui cng, cc tn hiu iu khin c i ni t cc output cu VXL sang cc outputca DMAC ( gn IOR#, I#, MEM#, MEMR#).

Cc buffer s liu hai chiu 8286 cho php c th truyn 8 bit s liu ti/t controllera t/ti hoc byte cao hoc byte thp ca b nh. Bit a ch A0 dng chn ngcho hai byte nh chn/l .

DMAC c 4 knh (channel), nhiu thanh ghi trong :

-Ghi a ch nh c s(16 bit). -Ghi s m t (word) nh c s

-a ch nh hin hnh . -Ghi a ch tm thi

-Ghi s m tm thi. -Ghi trng thi

-Ghi a ch lch -Ghi tm thi

-Cc thanh ghi mode -Ghi chn DMA

-Ghi yu cu xin DMA

DMAC c 4 chn a ch v 2 bit vo IOR#, IOW# iu khin hot ng c/vitcc thanh ghi ca n. N cn c mt flip flop tr a ch byte cao/byte thp ang c 8 chn s liu ca n. Cc flip flop ny c ln lt t ng lt trng thi chophp cp ra 16 bit a ch nh ch mt cng 8 bit. Tt nhin iu khin hot ng caDMAC cn phi lp trnh khi u n, v lp trnh cc hot ng sau ca n. DMAC


16/21

c th lp trnh truyn 1byte cho mi request, 1 khi cc byte cho mi request, haytruyn cho n khi nhn c 1 tn hiu dng t chn vo/ra EOP#.

i th phi lm cc vic sau:

- Vit t iu khin vo a ch trong 1101 xo flip flop trong

- Vit t iu khin vo a ch trong 1000

- Vit t mode cho mi channel (dng a ch trong 1011)

- Vit ra a ch nh u tin ti a ch trong ca thanh ghi c s cho mi channel tacn

- Vit ra s byte ta mun truyn ti a ch trong ca thanh ghi m s lng t c scho mi knh

- Vit t/ cc t iu khin xo mt n cho channel/ cc channel cn dng.

Table a


17/21

Table b


18/21


19/21

Cc thanh ghi v a ch trong ca DMAC8237

Trong my tnh AT ta dng hai DMAC, a ch ca chng trong mapping I/O l nhsau:

000 -01F : DMAC 1(8237A)

0C0 -0DF : DMAC 2 (8237)

087, 083, 081, 082, 08B, 089, 08A, 08F: DMA Page Register (cp cc a ch A16 -A23cho cc knh 0, 1, 2, 3, 5, 6, 7, v lm ti).

Bn knh ca DMAC 1 (nh s t 0 ti 3 ) dng truyn s liu 8 bit gia cc adapterI/O 8 bit vi nh 16 bit. Mi knh c th gip truyn 16 MByte s liu t chc thnhcc khi 64 kByte. ( Cc chn BHE l o ca A0).


20/21

DMAC2 c cc knh t 4 -7. Knh 4 dng ni tng bn knh 0 n 3 vo VXL. Baknh 5, 6, 7 dng truyn s liu 16 bit gia cc adapter I/O16 bit vi nh 16 bit. Ccknh DMA c th truyn 16 MByte ca cc khi 128 kByte. Cc knh 5, 6, 7 khng thtruyn s liu ca cc byte bt u bng a ch l (cc chn A0, v BHE u = 0).

Trong slot ISA ca my vi tnh AT c cc chn sau dng cho hai DMAC:

DRQ0, DRQ1, , DRQ2, DRQ3, DRQ4, DRQ5, DRQ6, DRQ7 v

DACK0 ACK1, DACK2, DACK3, DACK4, DACK5, DACK6, DACK7.


21/21

Kin trc b nh my vi tnhCc khi nim chungTrt t cc byte trong tM pht hin li v sa saiQun l b nh (MMU, Memory Management Unit)

T chc b nh ca vi x lT chc b nh RAM ca my tnhInterface gia VXL v b nhGii m a ch v Latch a ch, m hai chiu s liuGii m trng thi bus VXLB phn Cache Memory v Controller Cache MemoryHot ng ca Cache trc tip v Cache hai ngLm ti b nh DRAMChuyn mt mng s liu bng DMA

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