Konačni automati

Arhitektura mikrosistema

Konačni automati eng Finite State Machine ndash FSM Za modeliranje sekvencijalnih kola (pre svega upravljačkih

jedinica) Definiše ulaze izlaze stanja i prelaze U svakom taktnom ciklusu automat je u jednom od

konačnog broja svojih stanja Pod dejstvom taktnog signala a u zavisnosti od tekućeg

stanja i trenutne vrednosti ulaza automat prelazi u novo stanje i generiše odgovarajuće izlaze


Blok dijagram konačnog automata

Registarstanja

n x D FF

d q

Milijeva izlazna logika

Murova izlazna logika

Logika sledeceg

stanjapr_state

nx_stateUlazni signali

clk

Muroviizlazi

Milijeviizlazi

Određuje novo stanje u

zavisnosti od tekućeg stanja i

ulaza

Čuva kod tekućeg stanja

Generiše izlazne signale

Kombinacionemreže

MurovKonačni automat

MilijevKonacni automat


Dijagram stanja

ST0molt=vrednost

logički izraz melt=vrednost


ST0mo

logički izraz me logički izraz me

StanjeST0 - ime stanja

mo - Murovi izlazivrednost - acute0acute ili acute1acute

Prelazilogički izraz - uslov prelaza

me - Milijevi izlazivrednost - acute0acute ili acute1acute

ST0molt=vrednost



ST0mo


Navode se samo izlazi koji dobijaju vrednost acute1acute

Skraćeno zapisivanje


Primer - kontroler memorije

Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo

ProcesorKontroler memorije

mem

rw

burst

oe

we

we_oe

Memorija

clk

rst

Ukazuje na inicijalno (početno stanje)

Milijev izlaz

Murovi izlazi


ASM dijagram ASM (Algorithmic State Machines) dijagrami Zamena za dijagrame stanja Za opis algoritama koji se realizuju u hardveru Koristi tri grafička simbola

Izlazni signali ili naredbe reg

prenosa murovog tipa

uslov1 (tacno)0 (netacno) Izlazni signali ili

naredbe reg prenosa milijevog tipa

Blok stanja Blok grananja Blok uslovnog izlaza


ASM blok

Muroviizlazi

Logički izraz

Milijevi izlazi

Ulaz u stanje

Blok stanja

Blok grananja

Blok uslovnogizlaza

Izlaz ka drugom ASM bloku


T F

Ime stanja

ASM blok(odgovara jednom stanju)


Konverzija dijagram stanja u ASM dijagram

ST0y

ST1

- -

y

ST0

ST1

Navode samo signali koji su aktivni u datom stanju

y = lsquo1rsquo

y = lsquo0rsquo



ST0

ST1y1

ay0-

arsquo a

ST0

y0

0

1

y1

ST1



ST0y1

ST1

ab

arsquo

ST2y1

abrsquoy0 --

y1

a

ST0

0

1

b

y0

0

y1

ST2ST1

1


ST0y0

ST1

ay1amiddotbrsquoy2

-

y0

a

ST0

0

1

y1

b

y2

ST1

1

0arsquo


Primer - detektor ivice Na svaku rastuću ivicu signala strobe na

izlazu p se generiše kratkotrajni impuls

Detektorivicestrobe p

Sporo promenljiv

signal (u odnosu na takt)


Primer - detektor ivice (Murov KA)

zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2

p=acute1acute traje jedan ceo taktni ciklus

Vrednost strobe je bitna samo u trenucima rastućih ivica takta

zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo


Primer - detektor ivice (Milijev KA)

zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2

p trenutno reaguje na promenu signala strobe i traje sam do naredne rastuće ivice takta

zero

one

strobep

strobe

strobersquo

strobersquo


Opis u VHDL-u Višesegmentni kodni šablon ARCHITECTURE multi_seg_arch of mem_ctrl IS TYPE state IS (ST0 ST1ST2) SIGNAL pr_state nx_state stateBEGIN -- registar stanja ------------------- PROCESS(clk rst) BEGIN END PROCESS -- logika sledeceg stanja ------------ PROCESS(pr_state ulazi) BEGIN END PROCESS -- logika za Murove izlaze PROCESS(pr_state) BEGIN END PROCESS -- logika za Milijeve izlaze PROCESS(pr_state ulazi) BEGIN END PROCESSEND multi_seg_arch

Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi

Korisnički tip definiše stanja automata

pr_state - tekuće stanje (registar stanja)nx_state - sledeće stanje


Višesegmentni kodni šablon - kontroler memorije - deklaracija stanjaARCHITECTURE multi_seg_arch of mem_ctrl IS TYPE state IS (IDLE READ1 READ2 READ3 READ4 WRITE) SIGNAL pr_state nx_state stateBEGIN

Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo


Višesegmentni kodni šablon - kontroler memorije - registar stanja-- registar stanja -------------------PROCESS(clk rst)BEGIN IF(rst = 1) THEN pr_state lt= IDLE ELSIF( clkEVENT AND clk = 1) THEN pr_state lt= nx_state END IF END PROCESS

Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo


Višesegmentni kodni šablon - kontroler memorije - logika sledećeg stanja

PROCESS(pr_state mem rw burst) BEGIN CASE pr_state IS WHEN IDLE =gt IF(mem = 1) THEN IF(rw = 1) THEN nx_state lt= READ1 ELSE nx_state lt= WRITE END IF ELSE nx_state lt= IDLE END IF WHEN WRITE =gt nx_state lt= IDLE WHEN READ1 =gt IF(burst = 1) THEN nx_state lt= READ2 ELSE nx_state lt= IDLE END IF WHEN READ2 =gt nx_state lt= READ3 WHEN READ3 =gt nx_state lt= READ4 WHEN READ4 =gt nx_state lt= IDLE END CASE END PROCESS

Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo

Microsoft Word Document


Višesegmentni kodni šablon - kontroler memorije - Murovi izlazi PROCESS(pr_state) BEGIN we lt= 0 -- podrazumevana vrednost oe lt= 0 -- podrazumevana vrednost CASE pr_state IS WHEN IDLE =gt WHEN WRITE =gt we lt= 1 WHEN READ1 =gt oe lt= 1 WHEN READ2 =gt oe lt= 1 WHEN READ3 =gt oe lt= 1 WHEN READ4 =gt oe lt= 1 END CASEEND PROCESS

Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo


Višesegmentni kodni šablon - kontroler memorije - Milijevi izlaziPROCESS(pr_state mem rw)BEGIN we_me lt= 0 -- podrazumevana vrednostCASE pr_state IS WHEN IDLE =gt IF(mem = 1) AND (rw = 0) THEN we_me lt= 1 END IF WHEN WRITE =gt WHEN READ1 =gt WHEN READ2 =gt WHEN READ3 =gt WHEN READ4 =gt END CASEEND PROCESS

Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo


Višesegmentni kodni šablon - kontroler memorije - Milijevi izlazi

we_me lt= rsquo1rsquo WHEN ((pr_state = IDLE) AND (mem=rsquo1rsquo) AND (rw=rsquo0rsquo)) ELSE rsquo0rsquo

Može i jednostavnijeMože i jednostavnije

Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo


Dvosegmentni kodni šablonARCHITECTURE multi_seg_arch of

mem_ctrl IS TYPE state IS (ST0 ST1ST2) SIGNAL pr_state nx_state stateBEGIN -- registar stanja ------------------- PROCESS(clk rst) BEGIN END PROCESS -- logika sledeceg stanjaizlaza -- PROCESS(pr_state ulazi) BEGIN END PROCESSEND multi_seg_arch

Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe


Dvosegmentni kodni šablon - Kontroler memorije



Asinhrona inicijalizacija

Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo

-- registar stanja -------------------PROCESS(clk rst)BEGIN IF(rst = 1) THEN pr_state lt= IDLE ELSIF( clkEVENT AND clk = 1) THEN pr_state lt= nx_state END IFEND PROCESS


Sinhrona inicijalizacija -- registar stanja -------------------PROCESS(clk)BEGIN IF(clkEVENT AND clk = 1) THEN IF(syn_rst = 1) pr_state lt= IDLE ELSE pr_state lt= nx_state END IF END IFEND PROCESS izraz1 izraz2

ka stanju Si ka stanju Sj

syn_resrsquomiddotizraz1



ka inicijalnom

stanju

syn_res

Modifikuje se svako stanje u dijagramu stanja tako da syn_res = acute1acute vraća automat u inicijalno stanje

Obično se ne crta već se podrazumeva


1 ---------------------------------------------- 2 ENTITY fsm_1 IS 3 PORT (abcdclkrst IN BIT 4 x OUT BIT) 5 END fsm_1 6 ---------------------------------------------- 7 ARCHITECTURE fsm_1 OF fsm_1 IS 8 TYPE state IS (stateA stateB) 9 SIGNAL pr_state nx_state state 10 BEGIN 11 ---- sekvencijalni deo -------------------- 12 PROCESS (clkrst) 13 BEGIN 14 IF(rst=1)THEN 15 pr_state lt=stateA 16 ELSIF(clkEVENT AND clk=1) THEN 17 pr_state lt= nx_state 18 END IF 19 END PROCESS 20 ---- kombinacioni deo -------------------- 21 PROCESS(abdpr_state) 22 BEGIN 23 CASE pr_state IS 24 WHEN stateA =gt 25 xlt=a 26 IF(d=1)THEN 27 nx_state lt= stateB 28 ELSE 29 nx_state lt= stateA 30 END IF 31 WHEN stateB =gt 32 xlt=b 33 IF(d=1)THEN 34 nx_state lt= stateA 35 ELSE 36 nx_state lt= stateB 37 END IF 38 END CASE 39 END PROCESS 40 END fsm_1 41 ---------------------------------------------

FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst

Konačni automat Murovog tipaPrimer Izlaz automata zavisi jedino od tekućeg stanja (ali ne i od

trenutnog ulaza) Izlazi su pridruženi stanjima (a ne prelazima)

Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst


BCD brojač opisan kao konačni automat

1 --------------------------------------------- 2 LIBRARY ieee 3 USE ieeestd_logic_1164all 4 ---------------------------------------------- 5 ENTITY BCD IS 6 PORT (clkrst IN STD_LOGIC 7 count OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) 8 END BCD 9 ---------------------------------------------- 10 ARCHITECTURE FSM OF BCD IS 11 TYPE state IS (nula jedan dva tri cetiri 12 pet sest sedam osam devet) 13 SIGNAL pr_state nx_state state 14 BEGIN 15 ---- sekvencijalni deo -------------------- 16 PROCESS (clkrst) 17 BEGIN 18 IF(rst=1)THEN 19 pr_state lt=nula 20 ELSIF(clkEVENT AND clk=1) THEN 21 pr_state lt= nx_state 22 END IF 23 END PROCESS 24 ---- kombinacioni deo -------------------- 25 PROCESS(pr_state) 26 BEGIN 27 CASE pr_state IS 28 WHEN nula =gt 29 count lt= 0000 30 nx_state lt= jedan 31 WHEN jedan =gt 32 count lt= 0001 33 nx_state lt= dva 34 WHEN dva =gt 35 count lt= 0010 36 nx_state lt= tri 37 WHEN tri =gt 38 count lt= 0011 39 nx_state lt= cetiri 40 WHEN cetiri =gt 41 count lt= 0100 42 nx_state lt= pet 43 WHEN pet =gt 44 count lt= 0101 45 nx_state lt= sest 46 WHEN sest =gt 47 count lt= 0110 48 nx_state lt= sedam 49 WHEN sedam =gt 50 count lt= 0111 51 nx_state lt= osam 52 WHEN osam =gt 53 count lt= 1000 54 nx_state lt= devet 55 WHEN devet =gt 56 count lt= 1001 57 nx_state lt= nula 58 END CASE 59 END PROCESS 60 END FSM

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk

1 --------------------------------------------- 2 LIBRARY ieee 3 USE ieeestd_logic_1164all 4 USE ieeestd_logic_unsignedall 5 ---------------------------------------------- 6 ENTITY BCD IS 7 PORT (clkrst IN STD_LOGIC 8 count OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) 9 END BCD 10---------------------------------------------- 11 ARCHITECTURE counter OF BCD IS 12 SIGNAL reg STD_LOGIC_VECTOR(3 downto 0) 13 BEGIN 14 PROCESS(clkrst) 15 BEGIN 16 IF(rst=1) THEN 17 reg lt= (OTHERS =gt 0) 18 ELSIF(clkEVENT AND clk=1) THEN 19 IF(reg = 1001) THEN 20 reg lt= 0000 21 ELSE 22 reg lt= reg + 1 23 END IF 24 END IF 25 END PROCESS 26 count lt= reg 27 END counter 28 --------------------------------------------

Kao konačni automat

Lakši način


Detektor bit oblika Kolo koje detektuje tri uzastopne 1-ce u ulaznoj sekvenci


nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d

Detektorbit-oblikad q

clk rst

01011100

drsquo


Koder za Mančester kocircd Kod za kodiranje binarnih sekvenci za prenos preko serijske

komunikacione linije 0 =gt acute0acuterarracute1acute 1 =gt acute1acuterarracute0acute

0 0 1 0 0 1 1

Kodiranje binarne sekvence ˝0010011˝


Koder za Mančester kocircd

Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b

vmiddotdrsquovmiddotd

vmiddotdvmiddotdrsquo

vrsquo vrsquo

vrsquo



Arbitar Sprečava konflikte i koordinira pristup deljivom resursu

Request (r)- zahtev Grant (g) - dozvola

Podsistem koji želi da pristupi resursu aktivira request i čeka na grant Kad završi s korišćenjem resursa podsistem deaktivira request a onda i

arbit deaktivira grant

Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0


Arbitar - Murova automat Stanja

waitr - resurs je slobodan a arbitar čeka za zahtev grant1 - resurs je dodeljen podsistemu 1 grant0 - resurs je dodeljen podsistemu 0

waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0

U slučaju istovremenog upućivanja zahteva prednost uvek dobija podsistem 1


Arbitar - Milijev automat Brži odziv arbitra ali Podsistem 1 i dalje ima viši prioritet Šta ako podsistem 1 neprekidno zahteva resurs

Podsistem 0 nikad neće dobiti priliku da koristi resurs

waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0

Podsistemi dobijaju dozvolu u istom taktnom ciklusu kad

su uputili zatev


Arbitar - ldquoferrdquo politika arbitraže Arbitar vodi računa o tome koji podsistem je poslednji

koristio resurs i u slučajevima istovremenog upućivanja zahteva prednost daje onom drugom podsistemu

Stanja waitr0 - viši prioritet ima podsistem 0 waitr1 - viši prioritet ima podsistem 1 grant0 - resurs je dodeljen podsistemu 1 grant1 - resurs je dodeljen podsistemu 1


waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1


Problem kodiranja stanja Dodela binarnih kombinacija simboličkim stanjima konačnog

automata Kodiranje stanja automata sa 4 stanja

24 moguća kodiranja Funkcionalno identična ali razika u složenosti kombinacione

logike Koje kodiranje je optimalno

Težak problem S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3

1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00


Konačni automati - kodiranje stanja Može se razložiti na dva potproblema

Izbor broja bita za kodiranje Za konačni automat sa N stanja minimalni broj bita za

kodiranja iznosi Binarno kodiranje - kodiranje minimalnim brojem bita Onehot kodiranje - kodiranje sa N bita Svakom stanju

odgovara jedan bit u kodnoj reči S0 0001 S1 0010 S2 0100 S4 1000

Nn 2log


Šeme (heuristike) kodiranja stanja Binarno kodiranje

Minimalnan broj bita za kodiranje Stanjima se proizvoljno dodeljuju bin kombinacije Garantuje minimalni broj FF ali je logika složenija

Onehot kodiranje Broj bita za kodiranje jednak je broju stanja Kodovi su oblika 0001

0010 0100 (pozicija 1-ce ukazuje na stanje) Veliki broj FF ali kombinaciona logika je jednostavnija i brža

Gary-ov kocircd Minimalni broj bita za kodiranje ali složenije pravilo za dodelu

kodova stanjima Susednim stanjima (tj povezanim stanjima) dodeljuju se binarne

kombinacije koje se razlikuju na najmanjem broju bita Manja složenost u odnosu na binarno koridiranje

Nn 2log



1 Izbor broja bita za kodiranje

2 Pridruživanje stanjima jedinstvenih n-bitnih kombinacija

Automatsko - obavlja alat za sintezu u skaladu sa izabranom heuristikom kodiranja

Direktno - definiše projektant


Blok dijagram konačnog automata

Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi

Određuje novo stanje u

zavisnosti od tekućeg stanja i

ulaza

Čuva kod tekućeg stanja

Generiše izlazne signale

Kombinacionemreže

MurovKonačni automat

MilijevKonacni automat


Dijagram stanja

ST0molt=vrednost



ST0mo






ST0molt=vrednost



ST0mo






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo


mem

rw

burst

oe

we

we_oe

Memorija

clk

rst


Milijev izlaz

Murovi izlazi









ASM blok

Muroviizlazi

Logički izraz

Milijevi izlazi

Ulaz u stanje

Blok stanja

Blok grananja

Blok uslovnogizlaza



T F

Ime stanja




ST0y

ST1

- -

y

ST0

ST1


y = lsquo1rsquo

y = lsquo0rsquo



ST0

ST1y1

ay0-

arsquo a

ST0

y0

0

1

y1

ST1



ST0y1

ST1

ab

arsquo

ST2y1

abrsquoy0 --

y1

a

ST0

0

1

b

y0

0

y1

ST2ST1

1


ST0y0

ST1

ay1amiddotbrsquoy2

-

y0

a

ST0

0

1

y1

b

y2

ST1

1

0arsquo





Sporo promenljiv




zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log








Dijagram stanja

ST0molt=vrednost



ST0mo






ST0molt=vrednost



ST0mo






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo


mem

rw

burst

oe

we

we_oe

Memorija

clk

rst


Milijev izlaz

Murovi izlazi









ASM blok

Muroviizlazi

Logički izraz

Milijevi izlazi

Ulaz u stanje

Blok stanja

Blok grananja

Blok uslovnogizlaza



T F

Ime stanja




ST0y

ST1

- -

y

ST0

ST1


y = lsquo1rsquo

y = lsquo0rsquo



ST0

ST1y1

ay0-

arsquo a

ST0

y0

0

1

y1

ST1



ST0y1

ST1

ab

arsquo

ST2y1

abrsquoy0 --

y1

a

ST0

0

1

b

y0

0

y1

ST2ST1

1


ST0y0

ST1

ay1amiddotbrsquoy2

-

y0

a

ST0

0

1

y1

b

y2

ST1

1

0arsquo





Sporo promenljiv




zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo


mem

rw

burst

oe

we

we_oe

Memorija

clk

rst


Milijev izlaz

Murovi izlazi









ASM blok

Muroviizlazi

Logički izraz

Milijevi izlazi

Ulaz u stanje

Blok stanja

Blok grananja

Blok uslovnogizlaza



T F

Ime stanja




ST0y

ST1

- -

y

ST0

ST1


y = lsquo1rsquo

y = lsquo0rsquo



ST0

ST1y1

ay0-

arsquo a

ST0

y0

0

1

y1

ST1



ST0y1

ST1

ab

arsquo

ST2y1

abrsquoy0 --

y1

a

ST0

0

1

b

y0

0

y1

ST2ST1

1


ST0y0

ST1

ay1amiddotbrsquoy2

-

y0

a

ST0

0

1

y1

b

y2

ST1

1

0arsquo





Sporo promenljiv




zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log















ASM blok

Muroviizlazi

Logički izraz

Milijevi izlazi

Ulaz u stanje

Blok stanja

Blok grananja

Blok uslovnogizlaza



T F

Ime stanja




ST0y

ST1

- -

y

ST0

ST1


y = lsquo1rsquo

y = lsquo0rsquo



ST0

ST1y1

ay0-

arsquo a

ST0

y0

0

1

y1

ST1



ST0y1

ST1

ab

arsquo

ST2y1

abrsquoy0 --

y1

a

ST0

0

1

b

y0

0

y1

ST2ST1

1


ST0y0

ST1

ay1amiddotbrsquoy2

-

y0

a

ST0

0

1

y1

b

y2

ST1

1

0arsquo





Sporo promenljiv




zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log








ASM blok

Muroviizlazi

Logički izraz

Milijevi izlazi

Ulaz u stanje

Blok stanja

Blok grananja

Blok uslovnogizlaza



T F

Ime stanja




ST0y

ST1

- -

y

ST0

ST1


y = lsquo1rsquo

y = lsquo0rsquo



ST0

ST1y1

ay0-

arsquo a

ST0

y0

0

1

y1

ST1



ST0y1

ST1

ab

arsquo

ST2y1

abrsquoy0 --

y1

a

ST0

0

1

b

y0

0

y1

ST2ST1

1


ST0y0

ST1

ay1amiddotbrsquoy2

-

y0

a

ST0

0

1

y1

b

y2

ST1

1

0arsquo





Sporo promenljiv




zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









ST0y

ST1

- -

y

ST0

ST1


y = lsquo1rsquo

y = lsquo0rsquo



ST0

ST1y1

ay0-

arsquo a

ST0

y0

0

1

y1

ST1



ST0y1

ST1

ab

arsquo

ST2y1

abrsquoy0 --

y1

a

ST0

0

1

b

y0

0

y1

ST2ST1

1


ST0y0

ST1

ay1amiddotbrsquoy2

-

y0

a

ST0

0

1

y1

b

y2

ST1

1

0arsquo





Sporo promenljiv




zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









ST0

ST1y1

ay0-

arsquo a

ST0

y0

0

1

y1

ST1



ST0y1

ST1

ab

arsquo

ST2y1

abrsquoy0 --

y1

a

ST0

0

1

b

y0

0

y1

ST2ST1

1


ST0y0

ST1

ay1amiddotbrsquoy2

-

y0

a

ST0

0

1

y1

b

y2

ST1

1

0arsquo





Sporo promenljiv




zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









ST0y1

ST1

ab

arsquo

ST2y1

abrsquoy0 --

y1

a

ST0

0

1

b

y0

0

y1

ST2ST1

1


ST0y0

ST1

ay1amiddotbrsquoy2

-

y0

a

ST0

0

1

y1

b

y2

ST1

1

0arsquo





Sporo promenljiv




zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log








ST0y0

ST1

ay1amiddotbrsquoy2

-

y0

a

ST0

0

1

y1

b

y2

ST1

1

0arsquo





Sporo promenljiv




zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log











Sporo promenljiv




zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









zero zeroedge one

clk

strobe

Stanje(Murov FSM)

p(Murov FSM)

t1 t2



zero

edgep

one

strobe

strobe

strobersquo

strobersquo

strobe

strobersquo



zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









zero zeroone

clk

strobe

Stanje(Milijev FSM)

p(Milijev FSM)

t1 t2


zero

one

strobep

strobe

strobersquo

strobersquo



Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









Registarstanja

n x D FF

d q



Logika sledeceg

stanjapr_state


clk

Muroviizlazi

Milijeviizlazi





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log










Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo



Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo





Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log











Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo




Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log










Registarstanja

n x D FF

d q

Logika sledeceg

stanjaizlaza

pr_state

nx_state

Sekvencijalniproces

Kombinacioniproces

mem

rw

burst

clk

rst

we_me

we

oe






Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log












Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









Idle

Read1oe

Read2oe

Read4oe

Read3oe

burst - -

memrw

Writewe

memrwrsquo we_me

- memrsquo

-

rst

burstrsquo








ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log













ka inicijalnom

stanju

syn_res





FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









FSM

a

b

d

x

clk rst

stateA(x=a)

stateB(x=b)

d=1

d=1

d=0d=0

rst



Inicijalno stanje

stateA(x=a)

stateB(x=b)

d

d

drsquodrsquo

rst

FSM

a

b

dx

clk rst




nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log










nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

nula(0000)

jedan(0001)

dva(0010)

tri(0011)

cetiri(0100)

pet(0101)

sest(0110)

sedam(0111)

osam(1000)

devet(1001)

rst

BCDcount(3 0)

rst

clk



Lakši način




nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log










nula jedan

dvatriq

d

drsquo

d

d

drsquo

drsquo

d


clk rst

01011100

drsquo




0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log










0 0 1 0 0 1 1




Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log









Manchesterencoder

d

v

clk

rst

ys0a

s1ay

vmiddotd

Idle

vmiddotdrsquo

s0by

s1b



vrsquo vrsquo

vrsquo







Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log












Arbitar

Podsistem 0

Podsistem 1

Deljiv resurs

clk

g1

g0

r1

r0




waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log










waitr

r1middotr0

grant0g0

grant1g1

r1 r1

r1 r0

r1middotr0

r0





waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log










waitr

r1middotr0

grant0g0

grant1g1

r1 g1 r1

r1 r0

r1middotr0 g0

r0


su uputili zatev






waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log












waitr1

r1middotr0

grant0g0

grant1g1

r1 g1

r1 r0

r1middotr0 g0

r0

waitr0

r1middotr0

g1

r1middotr0

r0 g0

r1







1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log













1 00 01 10 11 9 01 10 00 11 17 10 11 00 01 2 00 01 11 10 10 01 10 11 00 18 10 11 01 00 3 00 10 01 11 11 01 11 00 10 19 11 00 01 10 4 00 10 11 01 12 01 11 10 00 20 11 00 10 01 5 00 11 00 10 13 10 00 01 11 21 11 01 00 10 6 00 11 10 01 14 10 00 11 01 22 11 01 10 00 7 01 00 10 11 15 10 01 00 11 23 11 10 00 01 8 01 00 11 10 16 10 01 11 00 24 11 10 01 00






Nn 2log









Nn 2log












Nn 2log









Nn 2log















Nn 2log













Documents

Konačni automati