L 18 : Circuit Level Design

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Buffer Chain• Delay analysis of buffer chain • Delay analysis considering parasitic

capacitance,Cp

input

stage 1 stage 1

stage ( i- 1) stage i s tage n

s ize 1 s ize s ize i- 2 s ize i- 1s ize n- 1

C in C ini- 1C in

iC inC in=nC in

)/ln()( , 72.2)(

0)(

)ln(

)/ln(

)ln(

)/ln(

)(

)/( )/(

0

1 100

1

inLoptimumoptimum

d

inLd

inL

inn

L

n

k

n

kdd

kk

CCne

T

CCtT

CCn

CC

tntktT

LWLW

) : (typical 10~21

1

1) (

) (

21

1

1

2

122

1

e

Eff

CCfVPP

CCfVfVCP

CCC

nn

n

nn

kpinddkT

pini

ddddkk

pk

ink

k

Ck,Pk: stage k buffer output 의 total capacitance, power

PT: buffer chain 의 power consumption

Pn: load capacitance CL 의 power consumption

Eff: power efficiency pn/pT

Slew Rate

• Determining rise/fall time

P eriod T

tr tf

t1 t3t2

V in

Vdd+ Vtp

Imax

Imean

Vtn

Ishort

fr

tddddmeanSC

ttntpp

t

t

tin

t

t

short

t

t

t

t

shortshortmean

tt

fVVVIP

VVV

dtVVT

dttIT

dttIdttIT

I

where,

)2(2

, where,

)(2

4

)(4

)()(2

3

n

22

1

2

1

2

1

3

2

Slew Rate(Cont’d)

• Power consumption of Short circuit current in Oscillation Circuit

Vdd

Vdd

Vo

V i

Vdd

Vdd

Vo

V i

VoV i

Pass Transistor Logic

• Reducing Area/Power

– Macro cell(Large part in chip area) XOR/XNOR/MUX(Primitive) Pass Tr. Logic

– Not using charge/discharge scheme Appropriate in Low Power Logic

• Pass Tr logic Family

– CPL (Complementary Pass Transistor Logic)

– DPL (Dual Pass Transistor Logic)

– SRPL (Swing Restored Pass Transistor Logic)

• CPL– Basic Scheme

– Inverter Buffering

A

ABAB

B

ABB

B

A

ABAB

B

B

ABB

VddVdd

p- M O S Latch

Pass Transistor Logic(Cont’d)• DPL

– Pass Tr Network + Dual p-MOS– Enables rail-to-rail swing– Characteristics

• Increasing input capacitance(delay)

• Increasing driving ability for existing 2 ON-path

• equals CPL in input loading capacitance

• SRPL

– Pass Tr network + Cross coupled inverter

– Restoring logic level

– Inverter size must not be too big

AB

B

A

B

AA

B

A

B

AB

n-M O S C PLnetw ork

Dynamic Logic• Using Precharge/Evaluation scheme

• Family

– Domino logic

– NORA(NO RAce) logic

• Characteristics

– Decreasing input loading capacitance

– Power consumption in precharge clock

– Increasing useless switching in precharging period

• Basic architecture of Domino logic

A

B

clk

C in C L

A

P1

N1

NLogic Blockc lk

B

A

precharge evaluation

Input Pin Ordering• Reorder the equivalent inputs to a transi

stor based on critical path delays and power consumption

• N- input Primitive CMOS logic

– symmetrical in function level

– antisymmetrical in Tr level

• capacitance of output stage

• body effect

• Scheme

– The signal that has many transition must be far from output

– If it is hard to estimate switching frequency, we must determine pin ordering considering path and path delay balance from primary input to input of Tr.

• Example of N-input CMOS logic

A

D

C L

C

B

C 3

C 1

C 2

Experimentd with gate array of TIFor a 4-input NAND gate in TI’s BiCMOS gate array library (with a load of 13 inverters), the delay varies by 20% while power dissipation by 10% between a good and bad ordering

INPUT PIN Reordering

CL

A B C D

C

A

B

D

CB

CC

CD

VDD

MPA MPB MPC

MPD

MNA

MNB

MNC

MND

1 1

1 1

1 1

1 1

1

1

1

1

(a) (b) (c) (d)

Simulation result ( tcycle=50ns, tf/tr=1ns)

: A 가 critical input 인 경우 =38.4uW,

D 가 critical input 인 경우 =47.2uW

Sensitization

• Example

• Definition

– sensitization : input signal that forces output transition event

– sensitization vector : the other inputs if one signal is sensitized

X1

X3

X2

),,,1,,,(

),,,0,,,(

][ ][

11

11

10

nili

nili

XXi

XXXXf

XXXXf

ffX

Yii

32332

101

][ ][ 11

XXXXX

ffX

YXX

321 )( XXXY

Sensitization(Cont’d)

• Considering Sensitization in Combinational logic:Remove unnecessary transitions in the C.L

• Considering Sensitization in Sequential logic: Also reduces the power consumption in the flip-flops.C om binational

LogicXn

E

QY

C om binationalLogic

X1

Xn

E

QY

C om binationalLogic

X1

Xn

E

Q Y

C om binationalLogic

QYD Q

D Q

c lk

X1

Xn

D Q

D Q

E

TTL-Compatible• TTL level signal CMOS

input• Characteristic Curve of CMOS

Inverter

Vdd= 3.3V

Vdd= 3.3V

Vo

V i

1.4V

V IL= 0.8V V IH= 2.0V Vdd= 3.3V

V i

VoI leak= avg(Id1, Id2)

IDTTL1 IDTTL2

Vdd

V in

TTL INP U T

padinput compatible TTL ofnumber : e wher

)( 21

TTL

DTTLDTTLddTTLTTL

N

IIVNP

TTL Compatible(Cont’d)

• CMOS output signal TTL input

– Because of sink current IOL,

CMOS gets a large amount of

heat

– Increased chip operating

temperature

– Power consumption of whole

system

C hip Boundary C hip Boundary

Input Pad

O utput Pad

VO L

IO L

INPUT PIN Reordering◈ To reduce the power dissipation one should place the

input with low transition density near the ground end.

(a) If MNA turns off , only CL needs to be charged (b) If MND turns off , all CL, CB, CC and CD needs to be charged (c) If the critical input is rising and placed near output node, the initial charge of CB, CC and CD are zero and the delay time of CL

discharging is less than (d) (d) If the critical input is rising and placed near ground end, the charge of CB, CC and CD must dischagge before the charge of CL discharge to zero